From nobody Wed Oct 8 14:42:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC6B712E5D; Fri, 27 Jun 2025 17:25:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751045111; cv=none; b=d09nRySnJ/8mt9fnkz9Hba3jPAMpZZMu2FK64VFmWTtlHCsg3HokOPc03BRKTN/fSg13Q+Ms6JAUBqPApxbataZu8nu9ox8nYXYY/Yx6pr++FwssRhXew6raKr9466zA/z/I4iYpys1gZHF1TokaWO0aVhhmDNCEyZ+ERhftG/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751045111; c=relaxed/simple; bh=sHk5RpacHVScooaj/Y+sk96HDvaUhpAnndDJawkuV2o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MNcc/fKLMm1TsSbfoEbVnNgsMY1MHbqbiBJ5LhCbIIl5zyCxIIX/E86SLZwcFDh/X4PwhvokJl1wllgdfzG4CjiueotZWewA36Ws/aa6gCU9nM0zlGFAMYx+GUjb+6Vd28IgLFjFUG+us5S8QJfX1N3xkMv6WAXfF+BBZscq2uI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tNe1ixy7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tNe1ixy7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C420BC4CEED; Fri, 27 Jun 2025 17:25:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751045110; bh=sHk5RpacHVScooaj/Y+sk96HDvaUhpAnndDJawkuV2o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tNe1ixy75qgwX291WZrclumD+DTCfGJHRD7MA81ngrUExqd0HMMufV2qTA644OQQ/ Mr8M12tTVbZsaqQeQEBPcZGAm1/TFi1dmQjeqmMxJJWLdOKs8t6YL1KFJFrBSTLPdJ HV41SIObrf8IYJ2wp679bSpczKCzcR81RipLZiKWDeZF40IDdTCbS8nBy4m48JJLNp W7Uoq0C9QeXMsa5MpWeOX2dispoDKzgOaIPRdAZIKzatWqkkU/GWzzUddZsomumGUW r946f4GmWFSNV2I0NAFFnM8cCfPm4UDpNjVXul2JqW3RYejcvwR6Co04r7kUcATwzD aXRBdHFjc0OOw== From: Mark Brown Date: Fri, 27 Jun 2025 18:20:44 +0100 Subject: [PATCH 1/3] arm64/hwcap: Add hwcap for FEAT_LSFE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250627-arm64-lsfe-v1-1-68351c4bf741@kernel.org> References: <20250627-arm64-lsfe-v1-0-68351c4bf741@kernel.org> In-Reply-To: <20250627-arm64-lsfe-v1-0-68351c4bf741@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-cff91 X-Developer-Signature: v=1; a=openpgp-sha256; l=3594; i=broonie@kernel.org; h=from:subject:message-id; bh=sHk5RpacHVScooaj/Y+sk96HDvaUhpAnndDJawkuV2o=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoXtPuXYjTexLVMi4SmHohaF0nZH+CHJyBlxP61 XPZKn+1HG2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaF7T7gAKCRAk1otyXVSH 0ERaB/9dXvOm+cbmv7v9o3lOh1PeSQC0Rm37Zukor8cHGUsDkm+kz4Kr+7whChuBpJwL8Y3SCoo exNu35wyXEVD9bZYZT7OQiHKpxDVPukH1vb1jG2BAipmA2HoTT3zpviYY7PgudARwAdvb+hL2h3 HvpJuDyMYLkzhKe8BrKUbZxFaBWOk566Qy/x22t0QWCsmZ5iDREAaaQa7VcGzmXNJ+mkGlLsDxj 1UYrzTrBXDdg2mOou/LJQt4TlCNS6E1A4r15Mwmrh8W/7P1y5rJ/G6RVg2Woyiu/DOh1xq4t926 JsxvvdCBQ6wtvdPpgsg9xlgDqNcTGIpYuK3vMZ0JJCFjPy9P X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB FEAT_LSFE (Large System Float Extension), providing atomic floating point memory operations, is optional from v9.5. This feature adds no new architectural stare and we have no immediate use for it in the kernel so simply provide a hwcap for it to support discovery by userspace. Signed-off-by: Mark Brown --- Documentation/arch/arm64/elf_hwcaps.rst | 4 ++++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 2 ++ arch/arm64/kernel/cpuinfo.c | 1 + 5 files changed, 9 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/a= rm64/elf_hwcaps.rst index 69d7afe56853..aafb969ca263 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -435,6 +435,10 @@ HWCAP2_SME_SF8DP4 HWCAP2_POE Functionality implied by ID_AA64MMFR3_EL1.S1POE =3D=3D 0b0001. =20 +HWCAP3_LSFE + Functionality implied by ID_AA64ISAR3_EL1.LSFE =3D=3D 0b0001 + + 4. Unused AT_HWCAP bits ----------------------- =20 diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 1c3f9617d54f..f8d02c14e5a2 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -176,6 +176,7 @@ #define KERNEL_HWCAP_POE __khwcap2_feature(POE) =20 #define __khwcap3_feature(x) (const_ilog2(HWCAP3_ ## x) + 128) +#define KERNEL_HWCAP_LSFE __khwcap3_feature(LSFE) =20 /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/= asm/hwcap.h index 705a7afa8e58..339b9dbf7cfc 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -143,5 +143,6 @@ /* * HWCAP3 flags - for AT_HWCAP3 */ +#define HWCAP3_LSFE (1 << 0) =20 #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b34044e20128..726054ac8091 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -278,6 +278,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = =3D { =20 static const struct arm64_ftr_bits ftr_id_aa64isar3[] =3D { ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_FPRCVT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_LSFE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_FAMINMAX_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -3175,6 +3176,7 @@ static const struct arm64_cpu_capabilities arm64_elf_= hwcaps[] =3D { HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINM= AX), + HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index c1f2b6b04b41..2a1efe8e1fdf 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -160,6 +160,7 @@ static const char *const hwcap_str[] =3D { [KERNEL_HWCAP_SME_SFEXPA] =3D "smesfexpa", [KERNEL_HWCAP_SME_STMOP] =3D "smestmop", [KERNEL_HWCAP_SME_SMOP4] =3D "smesmop4", + [KERNEL_HWCAP_LSFE] =3D "lsfe", }; =20 #ifdef CONFIG_COMPAT --=20 2.39.5