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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099D7.mail.protection.outlook.com (10.167.17.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8880.14 via Frontend Transport; Thu, 26 Jun 2025 22:44:17 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 26 Jun 2025 17:44:16 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v10 07/17] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Date: Thu, 26 Jun 2025 17:42:42 -0500 Message-ID: <20250626224252.1415009-8-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250626224252.1415009-1-terry.bowman@amd.com> References: <20250626224252.1415009-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D7:EE_|PH7PR12MB5783:EE_ X-MS-Office365-Filtering-Correlation-Id: 551fd707-0efd-4405-4aa1-08ddb502fb8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|1800799024|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:44:17.0562 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 551fd707-0efd-4405-4aa1-08ddb502fb8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5783 Content-Type: text/plain; charset="utf-8" Create cxl_do_recovery() to provide uncorrectable protocol error (UCE) handling. Follow similar design as found in PCIe error driver, pcie_do_recovery(). One difference is cxl_do_recovery() will treat all UCEs as fatal with a kernel panic. This is to prevent corruption on CXL memory. Export the PCI error driver's merge_result() to CXL namespace. Introduce PCI_ERS_RESULT_PANIC and add support in merge_result() routine. This will be used by CXL to panic the system in the case of uncorrectable protocol errors. PCI error handling is not currently expected to use the PCI_ERS_RESULT_PANIC. Copy pci_walk_bridge() to cxl_walk_bridge(). Make a change to walk the first device in all cases. Copy the PCI error driver's report_error_detected() to cxl_report_error_det= ected(). Note, only CXL Endpoints and RCH Downstream Ports(RCH DSP) are currently supported. Add locking for PCI device as done in PCI's report_error_detecte= d(). This is necessary to prevent the RAS registers from disappearing before logging is completed. Call panic() to halt the system in the case of uncorrectable errors (UCE) in cxl_do_recovery(). Export pci_aer_clear_fatal_status() for CXL to use if a UCE is not found. In this case the AER status must be cleared and uses pci_aer_clear_fatal_status(). Signed-off-by: Terry Bowman --- drivers/cxl/core/native_ras.c | 44 +++++++++++++++++++++++++++++++++++ drivers/pci/pcie/cxl_aer.c | 3 ++- drivers/pci/pcie/err.c | 8 +++++-- include/linux/aer.h | 11 +++++++++ include/linux/pci.h | 3 +++ 5 files changed, 66 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/core/native_ras.c b/drivers/cxl/core/native_ras.c index 5bd79d5019e7..19f8f2ac8376 100644 --- a/drivers/cxl/core/native_ras.c +++ b/drivers/cxl/core/native_ras.c @@ -8,8 +8,52 @@ #include #include =20 +static int cxl_report_error_detected(struct pci_dev *pdev, void *data) +{ + pci_ers_result_t vote, *result =3D data; + + if ((pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_RC_END)) + return 0; + + guard(device)(&pdev->dev); + + vote =3D cxl_error_detected(pdev, pci_channel_io_frozen); + *result =3D merge_result(*result, vote); + + return 0; +} + +static void cxl_walk_bridge(struct pci_dev *bridge, + int (*cb)(struct pci_dev *, void *), + void *userdata) +{ + if (cb(bridge, userdata)) + return; + + if (bridge->subordinate) + pci_walk_bus(bridge->subordinate, cb, userdata); +} + static void cxl_do_recovery(struct pci_dev *pdev) { + pci_ers_result_t status =3D PCI_ERS_RESULT_CAN_RECOVER; + + cxl_walk_bridge(pdev, cxl_report_error_detected, &status); + if (status =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + /* + * If we have native control of AER, clear error status in the device + * that detected the error. If the platform retained control of AER, + * it is responsible for clearing this status. In that case, the + * signaling device may not even be visible to the OS. + */ + if (cxl_error_is_native(pdev)) { + pcie_clear_device_status(pdev); + pci_aer_clear_nonfatal_status(pdev); + pci_aer_clear_fatal_status(pdev); + } } =20 static bool is_cxl_rcd(struct pci_dev *pdev) diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c index 939438a7161a..b238791b7101 100644 --- a/drivers/pci/pcie/cxl_aer.c +++ b/drivers/pci/pcie/cxl_aer.c @@ -52,12 +52,13 @@ static bool is_cxl_mem_dev(struct pci_dev *dev) return true; } =20 -static bool cxl_error_is_native(struct pci_dev *dev) +bool cxl_error_is_native(struct pci_dev *dev) { struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); =20 return (pcie_ports_native || host->native_aer); } +EXPORT_SYMBOL_NS_GPL(cxl_error_is_native, "CXL"); =20 static bool is_internal_error(struct aer_err_info *info) { diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index de6381c690f5..63fceb3e8613 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -21,9 +21,12 @@ #include "portdrv.h" #include "../pci.h" =20 -static pci_ers_result_t merge_result(enum pci_ers_result orig, - enum pci_ers_result new) +pci_ers_result_t merge_result(enum pci_ers_result orig, + enum pci_ers_result new) { + if (new =3D=3D PCI_ERS_RESULT_PANIC) + return PCI_ERS_RESULT_PANIC; + if (new =3D=3D PCI_ERS_RESULT_NO_AER_DRIVER) return PCI_ERS_RESULT_NO_AER_DRIVER; =20 @@ -45,6 +48,7 @@ static pci_ers_result_t merge_result(enum pci_ers_result = orig, =20 return orig; } +EXPORT_SYMBOL_NS_GPL(merge_result, "CXL"); =20 static int report_error_detected(struct pci_dev *dev, pci_channel_state_t state, diff --git a/include/linux/aer.h b/include/linux/aer.h index 0aafcc678e45..f14db635ef90 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -10,6 +10,7 @@ =20 #include #include +#include #include =20 #define AER_NONFATAL 0 @@ -78,6 +79,8 @@ struct cxl_proto_err_work_data { int pci_aer_clear_nonfatal_status(struct pci_dev *dev); void pci_aer_clear_fatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); +pci_ers_result_t merge_result(enum pci_ers_result orig, + enum pci_ers_result new); #else static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) { @@ -85,16 +88,24 @@ static inline int pci_aer_clear_nonfatal_status(struct = pci_dev *dev) } static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } +static inline pci_ers_result_t merge_result(enum pci_ers_result orig, + enum pci_ers_result new) +{ + return PCI_ERS_RESULT_NONE; +} + #endif =20 #if defined(CONFIG_PCIEAER_CXL) void cxl_register_proto_err_work(struct work_struct *work); void cxl_unregister_proto_err_work(void); int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd); +bool cxl_error_is_native(struct pci_dev *dev); #else static inline void cxl_register_proto_err_work(struct work_struct *work) {= } static inline void cxl_unregister_proto_err_work(void) { } static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *= wd) { return 0; } +static inline bool cxl_error_is_native(struct pci_dev *dev) { return 0; } #endif =20 void pci_print_aer(struct pci_dev *dev, int aer_severity, diff --git a/include/linux/pci.h b/include/linux/pci.h index 79326358f641..16a8310e0373 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -868,6 +868,9 @@ enum pci_ers_result { =20 /* No AER capabilities registered for the driver */ PCI_ERS_RESULT_NO_AER_DRIVER =3D (__force pci_ers_result_t) 6, + + /* System is unstable, panic. Is CXL specific */ + PCI_ERS_RESULT_PANIC =3D (__force pci_ers_result_t) 7, }; =20 /* PCI bus error event callbacks */ --=20 2.34.1