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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:43:21.3537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af92ab1b-2eda-4434-8253-08ddb502da59 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4235 Content-Type: text/plain; charset="utf-8" CXL and AER drivers need the ability to identify CXL devices. Add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The CXL Flexbus DVSEC presence is used because it is required for all the CXL PCIe devices.[1] Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL Flexbus presence. Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment, Table 8-2 Signed-off-by: Terry Bowman Reviewed-by: Ira Weiny Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- drivers/pci/probe.c | 10 ++++++++++ include/linux/pci.h | 6 ++++++ include/uapi/linux/pci_regs.h | 8 +++++++- 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4b8693ec9e4c..5d3548648d5c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1691,6 +1691,14 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) dev->is_thunderbolt =3D 1; } =20 +static void set_pcie_cxl(struct pci_dev *dev) +{ + u16 dvsec =3D pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS); + if (dvsec) + dev->is_cxl =3D 1; +} + static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent =3D pci_upstream_bridge(dev); @@ -2021,6 +2029,8 @@ int pci_setup_device(struct pci_dev *dev) /* Need to have dev->cfg_size ready */ set_pcie_thunderbolt(dev); =20 + set_pcie_cxl(dev); + set_pcie_untrusted(dev); =20 if (pci_is_pcie(dev)) diff --git a/include/linux/pci.h b/include/linux/pci.h index 05e68f35f392..79878243b681 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -453,6 +453,7 @@ struct pci_dev { unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ + unsigned int is_cxl:1; /* Compute Express Link (CXL) */ /* * Devices marked being untrusted are the ones that can potentially * execute DMA attacks and similar. They are typically connected @@ -744,6 +745,11 @@ static inline bool pci_is_vga(struct pci_dev *pdev) return false; } =20 +static inline bool pcie_is_cxl(struct pci_dev *pci_dev) +{ + return pci_dev->is_cxl; +} + #define for_each_pci_bridge(dev, bus) \ list_for_each_entry(dev, &bus->devices, bus_list) \ if (!pci_is_bridge(dev)) {} else diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index a3a3e942dedf..fb9d77c69d5f 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1225,9 +1225,15 @@ /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE = */ #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_= RSP_3_TYPE =20 -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ +/* Compute Express Link (CXL r3.2, sec 8.1) + * + * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state + * is "disconnected" (CXL r3.2, sec 9.12.3). Re-enumerate these + * registers on downstream link-up events. + */ #define PCI_DVSEC_CXL_PORT 3 #define PCI_DVSEC_CXL_PORT_CTL 0x0c #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 +#define PCI_DVSEC_CXL_FLEXBUS 7 =20 #endif /* LINUX_PCI_REGS_H */ --=20 2.34.1