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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:43:10.5207 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43308e82-3ab1-468e-835b-08ddb502d3e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9824 Content-Type: text/plain; charset="utf-8" The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras() are unnecessary helper functions used only for Endpoints. Remove these functions as they are not common for all CXL devices and do not provide value for EP handling. Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras() to cxl_handle_cor_ras(). Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Jonathan Cameron Reviewed-by: Dan Williams Reviewed-by: Dave Jiang Tested-by: Joshua Hahn --- drivers/cxl/core/pci.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index b50551601c2e..06464a25d8bd 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -664,8 +664,8 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { void __iomem *addr; u32 status; @@ -681,11 +681,6 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state = *cxlds, } } =20 -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); -} - /* CXL spec rev3.0 8.2.4.16.1 */ static void header_log_copy(void __iomem *ras_base, u32 *log) { @@ -707,8 +702,8 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static bool cxl_handle_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -741,11 +736,6 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxl= ds, return true; } =20 -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_ras(cxlds, cxlds->regs.ras); -} - #ifdef CONFIG_PCIEAER_CXL =20 static void cxl_dport_map_rch_aer(struct cxl_dport *dport) @@ -824,13 +814,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "C= XL"); static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); + return cxl_handle_cor_ras(cxlds, dport->regs.ras); } =20 static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_ras(cxlds, dport->regs.ras); + return cxl_handle_ras(cxlds, dport->regs.ras); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:43:21.3537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af92ab1b-2eda-4434-8253-08ddb502da59 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4235 Content-Type: text/plain; charset="utf-8" CXL and AER drivers need the ability to identify CXL devices. Add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The CXL Flexbus DVSEC presence is used because it is required for all the CXL PCIe devices.[1] Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL Flexbus presence. Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment, Table 8-2 Signed-off-by: Terry Bowman Reviewed-by: Ira Weiny Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Joshua Hahn --- drivers/pci/probe.c | 10 ++++++++++ include/linux/pci.h | 6 ++++++ include/uapi/linux/pci_regs.h | 8 +++++++- 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4b8693ec9e4c..5d3548648d5c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1691,6 +1691,14 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) dev->is_thunderbolt =3D 1; } =20 +static void set_pcie_cxl(struct pci_dev *dev) +{ + u16 dvsec =3D pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS); + if (dvsec) + dev->is_cxl =3D 1; +} + static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent =3D pci_upstream_bridge(dev); @@ -2021,6 +2029,8 @@ int pci_setup_device(struct pci_dev *dev) /* Need to have dev->cfg_size ready */ set_pcie_thunderbolt(dev); =20 + set_pcie_cxl(dev); + set_pcie_untrusted(dev); =20 if (pci_is_pcie(dev)) diff --git a/include/linux/pci.h b/include/linux/pci.h index 05e68f35f392..79878243b681 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -453,6 +453,7 @@ struct pci_dev { unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ + unsigned int is_cxl:1; /* Compute Express Link (CXL) */ /* * Devices marked being untrusted are the ones that can potentially * execute DMA attacks and similar. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:43:32.5001 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a42e907-84aa-4bc7-3c7c-08ddb502e0fe X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7157 Content-Type: text/plain; charset="utf-8" The AER service driver and aer_event tracing currently log 'PCIe Bus Type' for all errors. Update the driver and aer_event tracing to log 'CXL Bus Type' for CXL device errors. This requires the AER can identify and distinguish between PCIe errors and CXL errors. Introduce boolean 'is_cxl' to 'struct aer_err_info'. Add assignment in aer_get_device_error_info() and pci_print_aer(). Update the aer_event trace routine to accept a bus type string parameter. Signed-off-by: Terry Bowman Reviewed-by: Ira Weiny Reviewed-by: Dan Williams Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Joshua Hahn --- drivers/pci/pci.h | 6 ++++++ drivers/pci/pcie/aer.c | 21 +++++++++++++++------ include/ras/ras_event.h | 9 ++++++--- 3 files changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 12215ee72afb..a0d1e59b5666 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -608,6 +608,7 @@ struct aer_err_info { int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; int error_dev_num; const char *level; /* printk level */ + bool is_cxl; =20 unsigned int id:16; =20 @@ -628,6 +629,11 @@ struct aer_err_info { int aer_get_device_error_info(struct aer_err_info *info, int i); void aer_print_error(struct aer_err_info *info, int i); =20 +static inline const char *aer_err_bus(struct aer_err_info *info) +{ + return info->is_cxl ? "CXL" : "PCIe"; +} + int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, unsigned int tlp_len, bool flit, struct pcie_tlp_log *log); diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 70ac66188367..a2df9456595a 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -837,6 +837,7 @@ void aer_print_error(struct aer_err_info *info, int i) struct pci_dev *dev; int layer, agent, id; const char *level =3D info->level; + const char *bus_type =3D aer_err_bus(info); =20 if (WARN_ON_ONCE(i >=3D AER_MAX_MULTI_ERR_DEVICES)) return; @@ -845,23 +846,23 @@ void aer_print_error(struct aer_err_info *info, int i) id =3D pci_dev_id(dev); =20 pci_dev_aer_stats_incr(dev, info); - trace_aer_event(pci_name(dev), (info->status & ~info->mask), + trace_aer_event(pci_name(dev), bus_type, (info->status & ~info->mask), info->severity, info->tlp_header_valid, &info->tlp); =20 if (!info->ratelimit_print[i]) return; =20 if (!info->status) { - pci_err(dev, "PCIe Bus Error: severity=3D%s, type=3DInaccessible, (Unreg= istered Agent ID)\n", - aer_error_severity_string[info->severity]); + pci_err(dev, "%s Bus Error: severity=3D%s, type=3DInaccessible, (Unregis= tered Agent ID)\n", + bus_type, aer_error_severity_string[info->severity]); goto out; } =20 layer =3D AER_GET_LAYER_ERROR(info->severity, info->status); agent =3D AER_GET_AGENT(info->severity, info->status); =20 - aer_printk(level, dev, "PCIe Bus Error: severity=3D%s, type=3D%s, (%s)\n", - aer_error_severity_string[info->severity], + aer_printk(level, dev, "%s Bus Error: severity=3D%s, type=3D%s, (%s)\n", + bus_type, aer_error_severity_string[info->severity], aer_error_layer[layer], aer_agent_string[agent]); =20 aer_printk(level, dev, " device [%04x:%04x] error status/mask=3D%08x/%08= x\n", @@ -895,6 +896,7 @@ EXPORT_SYMBOL_GPL(cper_severity_to_aer); void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer) { + const char *bus_type; int layer, agent, tlp_header_valid =3D 0; u32 status, mask; struct aer_err_info info =3D { @@ -915,9 +917,12 @@ void pci_print_aer(struct pci_dev *dev, int aer_severi= ty, =20 info.status =3D status; info.mask =3D mask; + info.is_cxl =3D pcie_is_cxl(dev); + + bus_type =3D aer_err_bus(&info); =20 pci_dev_aer_stats_incr(dev, &info); - trace_aer_event(pci_name(dev), (status & ~mask), + trace_aer_event(pci_name(dev), bus_type, (status & ~mask), aer_severity, tlp_header_valid, &aer->header_log); =20 if (!aer_ratelimit(dev, info.severity)) @@ -939,6 +944,9 @@ void pci_print_aer(struct pci_dev *dev, int aer_severit= y, if (tlp_header_valid) pcie_print_tlp_log(dev, &aer->header_log, info.level, dev_fmt(" ")); + + trace_aer_event(dev_name(&dev->dev), bus_type, (status & ~mask), + aer_severity, tlp_header_valid, &aer->header_log); } EXPORT_SYMBOL_NS_GPL(pci_print_aer, "CXL"); =20 @@ -1371,6 +1379,7 @@ int aer_get_device_error_info(struct aer_err_info *in= fo, int i) /* Must reset in this function */ info->status =3D 0; info->tlp_header_valid =3D 0; + info->is_cxl =3D pcie_is_cxl(dev); =20 /* The device might not support AER */ if (!aer) diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index 14c9f943d53f..080829d59c36 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -297,15 +297,17 @@ TRACE_EVENT(non_standard_event, =20 TRACE_EVENT(aer_event, TP_PROTO(const char *dev_name, + const char *bus_type, const u32 status, const u8 severity, const u8 tlp_header_valid, struct pcie_tlp_log *tlp), =20 - TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp), + TP_ARGS(dev_name, bus_type, status, severity, tlp_header_valid, tlp), =20 TP_STRUCT__entry( __string( dev_name, dev_name ) + __string( bus_type, bus_type ) __field( u32, status ) __field( u8, severity ) __field( u8, tlp_header_valid) @@ -314,6 +316,7 @@ TRACE_EVENT(aer_event, =20 TP_fast_assign( __assign_str(dev_name); + __assign_str(bus_type); __entry->status =3D status; __entry->severity =3D severity; __entry->tlp_header_valid =3D tlp_header_valid; @@ -325,8 +328,8 @@ TRACE_EVENT(aer_event, } ), =20 - TP_printk("%s PCIe Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", - __get_str(dev_name), + TP_printk("%s %s Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", + __get_str(dev_name), __get_str(bus_type), __entry->severity =3D=3D AER_CORRECTABLE ? "Corrected" : __entry->severity =3D=3D AER_FATAL ? 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:43:43.6867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39e99eb9-511d-4beb-9bfc-08ddb502e7a9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9320 Content-Type: text/plain; charset="utf-8" The CXL AER error handling logic currently resides in the AER driver file, drivers/pci/pcie/aer.c. CXL specific changes are conditionally compiled using #ifdefs. Improve the AER driver maintainability by separating the CXL specific logic from the AER driver's core functionality and removing the #ifdefs. Introduce drivers/pci/pcie/cxl_aer.c and move the CXL AER logic into the new file. Update the makefile to conditionally compile the CXL file using the existing CONFIG_PCIEAER_CXL Kconfig. Signed-off-by: Terry Bowman Reviewed-by: Dan Williams Reviewed-by: Jonathan Cameron Tested-by: Joshua Hahn --- drivers/pci/pci.h | 8 +++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/aer.c | 138 ------------------------------------- drivers/pci/pcie/cxl_aer.c | 138 +++++++++++++++++++++++++++++++++++++ include/linux/pci_ids.h | 2 + 5 files changed, 149 insertions(+), 138 deletions(-) create mode 100644 drivers/pci/pcie/cxl_aer.c diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index a0d1e59b5666..91b583cf18eb 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1029,6 +1029,14 @@ static inline void pci_save_aer_state(struct pci_dev= *dev) { } static inline void pci_restore_aer_state(struct pci_dev *dev) { } #endif =20 +#ifdef CONFIG_PCIEAER_CXL +void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info); +void cxl_rch_enable_rcec(struct pci_dev *rcec); +#else +static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_er= r_info *info) { } +static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { } +#endif + #ifdef CONFIG_ACPI bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); int pci_acpi_program_hp_params(struct pci_dev *dev); diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 173829aa02e6..cd2cb925dbd5 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o bwctrl.o =20 obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o tlp.o +obj-$(CONFIG_PCIEAER_CXL) +=3D cxl_aer.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index a2df9456595a..0b4d721980ef 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1094,144 +1094,6 @@ static bool find_source_device(struct pci_dev *pare= nt, return true; } =20 -#ifdef CONFIG_PCIEAER_CXL - -/** - * pci_aer_unmask_internal_errors - unmask internal errors - * @dev: pointer to the pci_dev data structure - * - * Unmask internal errors in the Uncorrectable and Correctable Error - * Mask registers. - * - * Note: AER must be enabled and supported by the device which must be - * checked in advance, e.g. with pcie_aer_is_native(). - */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) -{ - int aer =3D dev->aer_cap; - u32 mask; - - pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); - mask &=3D ~PCI_ERR_UNC_INTN; - pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask); - - pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); - mask &=3D ~PCI_ERR_COR_INTERNAL; - pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); -} - -static bool is_cxl_mem_dev(struct pci_dev *dev) -{ - /* - * The capability, status, and control fields in Device 0, - * Function 0 DVSEC control the CXL functionality of the - * entire device (CXL 3.0, 8.1.3). - */ - if (dev->devfn !=3D PCI_DEVFN(0, 0)) - return false; - - /* - * CXL Memory Devices must have the 502h class code set (CXL - * 3.0, 8.1.12.1). - */ - if ((dev->class >> 8) !=3D PCI_CLASS_MEMORY_CXL) - return false; - - return true; -} - -static bool cxl_error_is_native(struct pci_dev *dev) -{ - struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); - - return (pcie_ports_native || host->native_aer); -} - -static bool is_internal_error(struct aer_err_info *info) -{ - if (info->severity =3D=3D AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} - -static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) -{ - struct aer_err_info *info =3D (struct aer_err_info *)data; - const struct pci_error_handlers *err_handler; - - if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) - return 0; - - /* Protect dev->driver */ - device_lock(&dev->dev); - - err_handler =3D dev->driver ? dev->driver->err_handler : NULL; - if (!err_handler) - goto out; - - if (info->severity =3D=3D AER_CORRECTABLE) { - if (err_handler->cor_error_detected) - err_handler->cor_error_detected(dev); - } else if (err_handler->error_detected) { - if (info->severity =3D=3D AER_NONFATAL) - err_handler->error_detected(dev, pci_channel_io_normal); - else if (info->severity =3D=3D AER_FATAL) - err_handler->error_detected(dev, pci_channel_io_frozen); - } -out: - device_unlock(&dev->dev); - return 0; -} - -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info = *info) -{ - /* - * Internal errors of an RCEC indicate an AER error in an - * RCH's downstream port. Check and handle them in the CXL.mem - * device driver. - */ - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); -} - -static int handles_cxl_error_iter(struct pci_dev *dev, void *data) -{ - bool *handles_cxl =3D data; - - if (!*handles_cxl) - *handles_cxl =3D is_cxl_mem_dev(dev) && cxl_error_is_native(dev); - - /* Non-zero terminates iteration */ - return *handles_cxl; -} - -static bool handles_cxl_errors(struct pci_dev *rcec) -{ - bool handles_cxl =3D false; - - if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); - - return handles_cxl; -} - -static void cxl_rch_enable_rcec(struct pci_dev *rcec) -{ - if (!handles_cxl_errors(rcec)) - return; - - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); -} - -#else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } -#endif =20 /** * pci_aer_handle_error - handle logging error into an event log diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c new file mode 100644 index 000000000000..b2ea14f70055 --- /dev/null +++ b/drivers/pci/pcie/cxl_aer.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */ + +#include +#include +#include "../pci.h" + +/** + * pci_aer_unmask_internal_errors - unmask internal errors + * @dev: pointer to the pci_dev data structure + * + * Unmask internal errors in the Uncorrectable and Correctable Error + * Mask registers. + * + * Note: AER must be enabled and supported by the device which must be + * checked in advance, e.g. with pcie_aer_is_native(). + */ +static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +{ + int aer =3D dev->aer_cap; + u32 mask; + + pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); + mask &=3D ~PCI_ERR_UNC_INTN; + pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask); + + pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); + mask &=3D ~PCI_ERR_COR_INTERNAL; + pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); +} + +static bool is_cxl_mem_dev(struct pci_dev *dev) +{ + /* + * The capability, status, and control fields in Device 0, + * Function 0 DVSEC control the CXL functionality of the + * entire device (CXL 3.2, 8.1.3). + */ + if (dev->devfn !=3D PCI_DEVFN(0, 0)) + return false; + + /* + * CXL Memory Devices must have the 502h class code set (CXL + * 3.2, 8.1.12.1). + */ + if (FIELD_GET(PCI_CLASS_CODE_MASK, dev->class) !=3D PCI_CLASS_MEMORY_CXL) + return false; + + return true; +} + +static bool cxl_error_is_native(struct pci_dev *dev) +{ + struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); + + return (pcie_ports_native || host->native_aer); +} + +static bool is_internal_error(struct aer_err_info *info) +{ + if (info->severity =3D=3D AER_CORRECTABLE) + return info->status & PCI_ERR_COR_INTERNAL; + + return info->status & PCI_ERR_UNC_INTN; +} + +static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) +{ + struct aer_err_info *info =3D (struct aer_err_info *)data; + const struct pci_error_handlers *err_handler; + + if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) + return 0; + + /* Protect dev->driver */ + device_lock(&dev->dev); + + err_handler =3D dev->driver ? dev->driver->err_handler : NULL; + if (!err_handler) + goto out; + + if (info->severity =3D=3D AER_CORRECTABLE) { + if (err_handler->cor_error_detected) + err_handler->cor_error_detected(dev); + } else if (err_handler->error_detected) { + if (info->severity =3D=3D AER_NONFATAL) + err_handler->error_detected(dev, pci_channel_io_normal); + else if (info->severity =3D=3D AER_FATAL) + err_handler->error_detected(dev, pci_channel_io_frozen); + } +out: + device_unlock(&dev->dev); + return 0; +} + +void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) +{ + /* + * Internal errors of an RCEC indicate an AER error in an + * RCH's downstream port. Check and handle them in the CXL.mem + * device driver. + */ + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && + is_internal_error(info)) + pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); +} + +static int handles_cxl_error_iter(struct pci_dev *dev, void *data) +{ + bool *handles_cxl =3D data; + + if (!*handles_cxl) + *handles_cxl =3D is_cxl_mem_dev(dev) && cxl_error_is_native(dev); + + /* Non-zero terminates iteration */ + return *handles_cxl; +} + +static bool handles_cxl_errors(struct pci_dev *rcec) +{ + bool handles_cxl =3D false; + + if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(rcec)) + pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + + return handles_cxl; +} + +void cxl_rch_enable_rcec(struct pci_dev *rcec) +{ + if (!handles_cxl_errors(rcec)) + return; + + pci_aer_unmask_internal_errors(rcec); + pci_info(rcec, "CXL: Internal errors unmasked"); +} + diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index e2d71b6fdd84..31b3935bf189 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -12,6 +12,8 @@ =20 /* Device classes and subclasses */ =20 +#define PCI_CLASS_CODE_MASK 0xFFFF00 + #define PCI_CLASS_NOT_DEFINED 0x0000 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 =20 --=20 2.34.1 From nobody Wed Oct 8 14:20:54 2025 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2054.outbound.protection.outlook.com [40.107.93.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 532E0284681; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:43:54.7801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f51e58d-4df5-4e03-ebc2-08ddb502ee45 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6193 Content-Type: text/plain; charset="utf-8" CXL error handling will soon be moved from the AER driver into the CXL driver. This requires a notification mechanism for the AER driver to share the AER interrupt with the CXL driver. The notification will be used as an indication for the CXL drivers to handle and log the CXL RAS errors. First, introduce cxl/core/native_ras.c to contain changes for the CXL driver's RAS native handling. This as an alternative to dropping the changes into existing cxl/core/ras.c file with purpose to avoid #ifdefs. Introduce CXL Kconfig CXL_NATIVE_RAS, dependent on PCIEAER_CXL, to conditionally compile the new file. Add a kfifo work queue to be used by the AER driver and CXL driver. The AER driver will be the sole kfifo producer adding work and the cxl_core will be the sole kfifo consumer removing work. Add the boilerplate kfifo support. Add CXL work queue handler registration functions in the AER driver. Export the functions allowing CXL driver to access. Implement registration functions for the CXL driver to assign or clear the work handler function. Introduce 'struct cxl_proto_err_info' to serve as the kfifo work data. This will contain the erring device's PCI SBDF details used to rediscover the device after the CXL driver dequeues the kfifo work. The device rediscovery will be introduced along with the CXL handling in future patches. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Tested-by: Joshua Hahn --- drivers/cxl/Kconfig | 14 ++++++++ drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 8 +++++ drivers/cxl/core/native_ras.c | 26 +++++++++++++++ drivers/cxl/core/port.c | 2 ++ drivers/cxl/core/ras.c | 1 + drivers/cxl/cxlpci.h | 1 + drivers/pci/pci.h | 4 +++ drivers/pci/pcie/aer.c | 7 ++-- drivers/pci/pcie/cxl_aer.c | 60 +++++++++++++++++++++++++++++++++++ include/linux/aer.h | 31 ++++++++++++++++++ 11 files changed, 153 insertions(+), 2 deletions(-) create mode 100644 drivers/cxl/core/native_ras.c diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 48b7314afdb8..57274de54a45 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -233,4 +233,18 @@ config CXL_MCE def_bool y depends on X86_MCE && MEMORY_FAILURE =20 +config CXL_NATIVE_RAS + bool "CXL: Enable CXL RAS native handling" + depends on PCIEAER_CXL + default CXL_BUS + help + Enable native CXL RAS protocol error handling and logging in the CXL + drivers. This functionality relies on the AER service driver being + enabled, as the AER interrupt is used to inform the operating system + of CXL RAS protocol errors. The platform must be configured to + utilize AER reporting for interrupts. + + If unsure, or if this kernel is meant for production environments, + say Y. + endif diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 79e2ef81fde8..16f5832e5cc4 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -21,3 +21,4 @@ cxl_core-$(CONFIG_CXL_REGION) +=3D region.o cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o +cxl_core-$(CONFIG_CXL_NATIVE_RAS) +=3D native_ras.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 29b61828a847..4c08bb92e2f9 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -123,6 +123,14 @@ int cxl_gpf_port_setup(struct cxl_dport *dport); int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res, int nid, resource_size_t *size); =20 +#ifdef CONFIG_PCIEAER_CXL +void cxl_native_ras_init(void); +void cxl_native_ras_exit(void); +#else +static inline void cxl_native_ras_init(void) { }; +static inline void cxl_native_ras_exit(void) { }; +#endif + #ifdef CONFIG_CXL_FEATURES struct cxl_feat_entry * cxl_feature_info(struct cxl_features_state *cxlfs, const uuid_t *uuid); diff --git a/drivers/cxl/core/native_ras.c b/drivers/cxl/core/native_ras.c new file mode 100644 index 000000000000..011815ddaae3 --- /dev/null +++ b/drivers/cxl/core/native_ras.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include +#include + +static void cxl_proto_err_work_fn(struct work_struct *work) +{ +} + +static struct work_struct cxl_proto_err_work; +static DECLARE_WORK(cxl_proto_err_work, cxl_proto_err_work_fn); + +void cxl_native_ras_init(void) +{ + cxl_register_proto_err_work(&cxl_proto_err_work); +} + +void cxl_native_ras_exit(void) +{ + cxl_unregister_proto_err_work(); + cancel_work_sync(&cxl_proto_err_work); +} diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index eb46c6764d20..8e8f21197c86 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2345,6 +2345,8 @@ static __init int cxl_core_init(void) if (rc) goto err_ras; =20 + cxl_native_ras_init(); + return 0; =20 err_ras: diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 485a831695c7..962dc94fed8c 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "trace.h" =20 static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev, diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 54e219b0049e..6f1396ef7b77 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -4,6 +4,7 @@ #define __CXL_PCI_H__ #include #include "cxl.h" +#include "linux/aer.h" =20 #define CXL_MEMORY_PROGIF 0x10 =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 91b583cf18eb..29c11c7136d3 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1032,9 +1032,13 @@ static inline void pci_restore_aer_state(struct pci_= dev *dev) { } #ifdef CONFIG_PCIEAER_CXL void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info); void cxl_rch_enable_rcec(struct pci_dev *rcec); +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info); +void forward_cxl_error(struct pci_dev *pdev, struct aer_err_info *aer_err_= info); #else static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_er= r_info *info) { } static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { } +static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info = *info) { return false; } +static inline void forward_cxl_error(struct pci_dev *pdev, struct aer_err_= info *aer_err_info) { } #endif =20 #ifdef CONFIG_ACPI diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 0b4d721980ef..8417a49c71f2 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1130,8 +1130,11 @@ static void pci_aer_handle_error(struct pci_dev *dev= , struct aer_err_info *info) =20 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { - cxl_rch_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (is_cxl_error(dev, info)) + forward_cxl_error(dev, info); + else + pci_aer_handle_error(dev, info); + pci_dev_put(dev); } =20 diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c index b2ea14f70055..846ab55d747c 100644 --- a/drivers/pci/pcie/cxl_aer.c +++ b/drivers/pci/pcie/cxl_aer.c @@ -3,8 +3,11 @@ =20 #include #include +#include #include "../pci.h" =20 +#define CXL_ERROR_SOURCES_MAX 128 + /** * pci_aer_unmask_internal_errors - unmask internal errors * @dev: pointer to the pci_dev data structure @@ -64,6 +67,19 @@ static bool is_internal_error(struct aer_err_info *info) return info->status & PCI_ERR_UNC_INTN; } =20 +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + if (!info || !info->is_cxl) + return false; + + /* Only CXL Endpoints are currently supported */ + if ((pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_RC_EC)) + return false; + + return is_internal_error(info); +} + static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) { struct aer_err_info *info =3D (struct aer_err_info *)data; @@ -136,3 +152,47 @@ void cxl_rch_enable_rcec(struct pci_dev *rcec) pci_info(rcec, "CXL: Internal errors unmasked"); } =20 +static DEFINE_KFIFO(cxl_proto_err_fifo, struct cxl_proto_err_work_data, + CXL_ERROR_SOURCES_MAX); +static DEFINE_SPINLOCK(cxl_proto_err_fifo_lock); +struct work_struct *cxl_proto_err_work; + +void cxl_register_proto_err_work(struct work_struct *work) +{ + guard(spinlock)(&cxl_proto_err_fifo_lock); + cxl_proto_err_work =3D work; +} +EXPORT_SYMBOL_NS_GPL(cxl_register_proto_err_work, "CXL"); + +void cxl_unregister_proto_err_work(void) +{ + guard(spinlock)(&cxl_proto_err_fifo_lock); + cxl_proto_err_work =3D NULL; +} +EXPORT_SYMBOL_NS_GPL(cxl_unregister_proto_err_work, "CXL"); + +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd) +{ + return kfifo_get(&cxl_proto_err_fifo, wd); +} +EXPORT_SYMBOL_NS_GPL(cxl_proto_err_kfifo_get, "CXL"); + +void forward_cxl_error(struct pci_dev *pdev, struct aer_err_info *aer_err_= info) +{ + struct cxl_proto_err_work_data wd; + + wd.err_info =3D (struct cxl_proto_error_info) { + .severity =3D aer_err_info->severity, + .devfn =3D pdev->devfn, + .bus =3D pdev->bus->number, + .segment =3D pci_domain_nr(pdev->bus) + }; + + if (!kfifo_put(&cxl_proto_err_fifo, wd)) { + dev_err_ratelimited(&pdev->dev, "CXL kfifo overflow\n"); + return; + } + + schedule_work(cxl_proto_err_work); +} + diff --git a/include/linux/aer.h b/include/linux/aer.h index 02940be66324..24c3d9e18ad5 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -10,6 +10,7 @@ =20 #include #include +#include =20 #define AER_NONFATAL 0 #define AER_FATAL 1 @@ -53,6 +54,26 @@ struct aer_capability_regs { u16 uncor_err_source; }; =20 +/** + * struct cxl_proto_err_info - Error information used in CXL error handling + * @severity: AER severity + * @function: Device's PCI function + * @device: Device's PCI device + * @bus: Device's PCI bus + * @segment: Device's PCI segment + */ +struct cxl_proto_error_info { + int severity; + + u8 devfn; + u8 bus; + u16 segment; +}; + +struct cxl_proto_err_work_data { + struct cxl_proto_error_info err_info; +}; + #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); @@ -64,6 +85,16 @@ static inline int pci_aer_clear_nonfatal_status(struct p= ci_dev *dev) static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } #endif =20 +#if defined(CONFIG_PCIEAER_CXL) +void cxl_register_proto_err_work(struct work_struct *work); +void cxl_unregister_proto_err_work(void); +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd); +#else +static inline void cxl_register_proto_err_work(struct work_struct *work) {= } +static inline void cxl_unregister_proto_err_work(void) { } +static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *= wd) { return 0; } +#endif + void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer); int cper_severity_to_aer(int cper_severity); --=20 2.34.1 From nobody Wed Oct 8 14:20:54 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2060.outbound.protection.outlook.com [40.107.237.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E5F4270577; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:44:06.9521 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56eb3e6c-c614-4f1d-6f97-08ddb502f587 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5619 Content-Type: text/plain; charset="utf-8" The AER driver is now designed to forward CXL protocol errors to the CXL driver. Update the CXL driver with functionality to dequeue the forwarded CXL error from the kfifo. Also, update the CXL driver to begin the protocol error handling processing using the work received from the FIFO. Introduce function cxl_proto_err_work_fn() to dequeue work forwarded by the AER service driver. This will begin the CXL protocol error processing with a call to cxl_handle_proto_error(). Update cxl/core/native_ras.c by adding cxl_rch_handle_error_iter() that was previously in the AER driver. Add check that Endpoint is bound to a CXL driver. Introduce logic to take the SBDF values from 'struct cxl_proto_error_info' and use in discovering the erring PCI device. The call to pci_get_domain_bu= s_and_slot() will return a reference counted 'struct pci_dev *'. This will serve as reference count to prevent releasing the CXL Endpoint's mapped RAS while handling the error. Use scope base __free() to put the reference count. This will change when adding support for CXL port devices in the future. Implement cxl_handle_proto_error() to differentiate between Restricted CXL Host (RCH) protocol errors and CXL virtual host (VH) protocol errors. RCH errors will be processed with a call to walk the associated Root Complex Event Collector's (RCEC) secondary bus looking for the Root Complex Integrated Endpoint (RCiEP) to handle the RCH error. Export pcie_walk_rcec() so the CXL driver can walk the RCEC's downstream bus, searching for the RCiEP. VH correctable error (CE) processing will call the CXL CE handler. VH uncorrectable errors (UCE) will call cxl_do_recovery(), implemented as a stub for now and to be updated in future patch. Export pci_aer_clean_fatal_= status() and pci_clean_device_status() used to clean up AER status after handling. Maintain the locking logic found in the original AER driver. Replace the existing device_lock() in cxl_rch_handle_error_iter() to use guard(device) lock for maintainability. CE errors did not include locking in previous dri= ver implementation. Leave the updated CE handling path as-is. Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Tested-by: Joshua Hahn --- drivers/cxl/core/native_ras.c | 87 +++++++++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 1 + drivers/cxl/pci.c | 6 +++ drivers/pci/pci.c | 1 + drivers/pci/pci.h | 7 --- drivers/pci/pcie/aer.c | 1 + drivers/pci/pcie/cxl_aer.c | 41 ----------------- drivers/pci/pcie/rcec.c | 1 + include/linux/aer.h | 2 + include/linux/pci.h | 10 ++++ 10 files changed, 109 insertions(+), 48 deletions(-) diff --git a/drivers/cxl/core/native_ras.c b/drivers/cxl/core/native_ras.c index 011815ddaae3..5bd79d5019e7 100644 --- a/drivers/cxl/core/native_ras.c +++ b/drivers/cxl/core/native_ras.c @@ -6,9 +6,96 @@ #include #include #include +#include + +static void cxl_do_recovery(struct pci_dev *pdev) +{ +} + +static bool is_cxl_rcd(struct pci_dev *pdev) +{ + if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_RC_END) + return false; + + /* + * The capability, status, and control fields in Device 0, + * Function 0 DVSEC control the CXL functionality of the + * entire device (CXL 3.2, 8.1.3). + */ + if (pdev->devfn !=3D PCI_DEVFN(0, 0)) + return false; + + /* + * CXL Memory Devices must have the 502h class code set (CXL + * 3.2, 8.1.12.1). + */ + if (FIELD_GET(PCI_CLASS_CODE_MASK, pdev->class) !=3D PCI_CLASS_MEMORY_CXL) + return false; + + return true; +} + +static int cxl_rch_handle_error_iter(struct pci_dev *pdev, void *data) +{ + struct cxl_proto_error_info *err_info =3D data; + + guard(device)(&pdev->dev); + + if (!is_cxl_rcd(pdev) || !cxl_pci_drv_bound(pdev)) + return 0; + + if (err_info->severity =3D=3D AER_CORRECTABLE) + cxl_cor_error_detected(pdev); + else + cxl_error_detected(pdev, pci_channel_io_frozen); + + return 1; +} + +static void cxl_handle_proto_error(struct cxl_proto_error_info *err_info) +{ + struct pci_dev *pdev __free(pci_dev_put) =3D + pci_get_domain_bus_and_slot(err_info->segment, + err_info->bus, + err_info->devfn); + + if (!pdev) { + pr_err("Failed to find the CXL device (SBDF=3D%x:%x:%x:%x)\n", + err_info->segment, err_info->bus, PCI_SLOT(err_info->devfn), + PCI_FUNC(err_info->devfn)); + return; + } + + /* + * Internal errors of an RCEC indicate an AER error in an + * RCH's downstream port. Check and handle them in the CXL.mem + * device driver. + */ + if (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_RC_EC) + return pcie_walk_rcec(pdev, cxl_rch_handle_error_iter, err_info); + + if (err_info->severity =3D=3D AER_CORRECTABLE) { + int aer =3D pdev->aer_cap; + + if (aer) + pci_clear_and_set_config_dword(pdev, + aer + PCI_ERR_COR_STATUS, + 0, PCI_ERR_COR_INTERNAL); + + cxl_cor_error_detected(pdev); + + pcie_clear_device_status(pdev); + } else { + cxl_do_recovery(pdev); + } +} =20 static void cxl_proto_err_work_fn(struct work_struct *work) { + struct cxl_proto_err_work_data wd; + + while (cxl_proto_err_kfifo_get(&wd)) + cxl_handle_proto_error(&wd.err_info); } =20 static struct work_struct cxl_proto_err_work; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 6f1396ef7b77..ed3c9701b79f 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -136,4 +136,5 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +bool cxl_pci_drv_bound(struct pci_dev *pdev); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bd100ac31672..cae049f9ae3e 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1131,6 +1131,12 @@ static struct pci_driver cxl_pci_driver =3D { }, }; =20 +bool cxl_pci_drv_bound(struct pci_dev *pdev) +{ + return (pdev->driver =3D=3D &cxl_pci_driver); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_drv_bound, "CXL"); + #define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0) static void cxl_handle_cper_event(enum cxl_event_type ev_type, struct cxl_cper_event_rec *rec) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e9448d55113b..8d78d882bf78 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2328,6 +2328,7 @@ void pcie_clear_device_status(struct pci_dev *dev) pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta); pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta); } +EXPORT_SYMBOL_NS_GPL(pcie_clear_device_status, "CXL"); #endif =20 /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 29c11c7136d3..c7fc86d93bea 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -671,16 +671,10 @@ static inline bool pci_dpc_recovered(struct pci_dev *= pdev) { return false; } void pci_rcec_init(struct pci_dev *dev); void pci_rcec_exit(struct pci_dev *dev); void pcie_link_rcec(struct pci_dev *rcec); -void pcie_walk_rcec(struct pci_dev *rcec, - int (*cb)(struct pci_dev *, void *), - void *userdata); #else static inline void pci_rcec_init(struct pci_dev *dev) { } static inline void pci_rcec_exit(struct pci_dev *dev) { } static inline void pcie_link_rcec(struct pci_dev *rcec) { } -static inline void pcie_walk_rcec(struct pci_dev *rcec, - int (*cb)(struct pci_dev *, void *), - void *userdata) { } #endif =20 #ifdef CONFIG_PCI_ATS @@ -1022,7 +1016,6 @@ void pci_restore_aer_state(struct pci_dev *dev); static inline void pci_no_aer(void) { } static inline void pci_aer_init(struct pci_dev *d) { } static inline void pci_aer_exit(struct pci_dev *d) { } -static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINV= AL; } static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -= EINVAL; } static inline void pci_save_aer_state(struct pci_dev *dev) { } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 8417a49c71f2..5999d90dfdcb 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -287,6 +287,7 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev) if (status) pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); } +EXPORT_SYMBOL_GPL(pci_aer_clear_fatal_status); =20 /** * pci_aer_raw_clear_status - Clear AER error registers. diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c index 846ab55d747c..939438a7161a 100644 --- a/drivers/pci/pcie/cxl_aer.c +++ b/drivers/pci/pcie/cxl_aer.c @@ -80,47 +80,6 @@ bool is_cxl_error(struct pci_dev *pdev, struct aer_err_i= nfo *info) return is_internal_error(info); } =20 -static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) -{ - struct aer_err_info *info =3D (struct aer_err_info *)data; - const struct pci_error_handlers *err_handler; - - if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) - return 0; - - /* Protect dev->driver */ - device_lock(&dev->dev); - - err_handler =3D dev->driver ? dev->driver->err_handler : NULL; - if (!err_handler) - goto out; - - if (info->severity =3D=3D AER_CORRECTABLE) { - if (err_handler->cor_error_detected) - err_handler->cor_error_detected(dev); - } else if (err_handler->error_detected) { - if (info->severity =3D=3D AER_NONFATAL) - err_handler->error_detected(dev, pci_channel_io_normal); - else if (info->severity =3D=3D AER_FATAL) - err_handler->error_detected(dev, pci_channel_io_frozen); - } -out: - device_unlock(&dev->dev); - return 0; -} - -void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) -{ - /* - * Internal errors of an RCEC indicate an AER error in an - * RCH's downstream port. Check and handle them in the CXL.mem - * device driver. - */ - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); -} - static int handles_cxl_error_iter(struct pci_dev *dev, void *data) { bool *handles_cxl =3D data; diff --git a/drivers/pci/pcie/rcec.c b/drivers/pci/pcie/rcec.c index d0bcd141ac9c..fb6cf6449a1d 100644 --- a/drivers/pci/pcie/rcec.c +++ b/drivers/pci/pcie/rcec.c @@ -145,6 +145,7 @@ void pcie_walk_rcec(struct pci_dev *rcec, int (*cb)(str= uct pci_dev *, void *), =20 walk_rcec(walk_rcec_helper, &rcec_data); } +EXPORT_SYMBOL_NS_GPL(pcie_walk_rcec, "CXL"); =20 void pci_rcec_init(struct pci_dev *dev) { diff --git a/include/linux/aer.h b/include/linux/aer.h index 24c3d9e18ad5..0aafcc678e45 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -76,12 +76,14 @@ struct cxl_proto_err_work_data { =20 #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); +void pci_aer_clear_fatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); #else static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) { return -EINVAL; } +static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } #endif =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 79878243b681..79326358f641 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1801,6 +1801,9 @@ extern bool pcie_ports_native; =20 int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_r= eq, bool use_lt); +void pcie_walk_rcec(struct pci_dev *rcec, + int (*cb)(struct pci_dev *, void *), + void *userdata); #else #define pcie_ports_disabled true #define pcie_ports_native false @@ -1811,8 +1814,15 @@ static inline int pcie_set_target_speed(struct pci_d= ev *port, { return -EOPNOTSUPP; } + +static inline void pcie_walk_rcec(struct pci_dev *rcec, + int (*cb)(struct pci_dev *, void *), + void *userdata) { } + #endif =20 +void pcie_clear_device_status(struct pci_dev *dev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:44:17.0562 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 551fd707-0efd-4405-4aa1-08ddb502fb8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5783 Content-Type: text/plain; charset="utf-8" Create cxl_do_recovery() to provide uncorrectable protocol error (UCE) handling. Follow similar design as found in PCIe error driver, pcie_do_recovery(). One difference is cxl_do_recovery() will treat all UCEs as fatal with a kernel panic. This is to prevent corruption on CXL memory. Export the PCI error driver's merge_result() to CXL namespace. Introduce PCI_ERS_RESULT_PANIC and add support in merge_result() routine. This will be used by CXL to panic the system in the case of uncorrectable protocol errors. PCI error handling is not currently expected to use the PCI_ERS_RESULT_PANIC. Copy pci_walk_bridge() to cxl_walk_bridge(). Make a change to walk the first device in all cases. Copy the PCI error driver's report_error_detected() to cxl_report_error_det= ected(). Note, only CXL Endpoints and RCH Downstream Ports(RCH DSP) are currently supported. Add locking for PCI device as done in PCI's report_error_detecte= d(). This is necessary to prevent the RAS registers from disappearing before logging is completed. Call panic() to halt the system in the case of uncorrectable errors (UCE) in cxl_do_recovery(). Export pci_aer_clear_fatal_status() for CXL to use if a UCE is not found. In this case the AER status must be cleared and uses pci_aer_clear_fatal_status(). Signed-off-by: Terry Bowman Tested-by: Joshua Hahn --- drivers/cxl/core/native_ras.c | 44 +++++++++++++++++++++++++++++++++++ drivers/pci/pcie/cxl_aer.c | 3 ++- drivers/pci/pcie/err.c | 8 +++++-- include/linux/aer.h | 11 +++++++++ include/linux/pci.h | 3 +++ 5 files changed, 66 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/core/native_ras.c b/drivers/cxl/core/native_ras.c index 5bd79d5019e7..19f8f2ac8376 100644 --- a/drivers/cxl/core/native_ras.c +++ b/drivers/cxl/core/native_ras.c @@ -8,8 +8,52 @@ #include #include =20 +static int cxl_report_error_detected(struct pci_dev *pdev, void *data) +{ + pci_ers_result_t vote, *result =3D data; + + if ((pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_RC_END)) + return 0; + + guard(device)(&pdev->dev); + + vote =3D cxl_error_detected(pdev, pci_channel_io_frozen); + *result =3D merge_result(*result, vote); + + return 0; +} + +static void cxl_walk_bridge(struct pci_dev *bridge, + int (*cb)(struct pci_dev *, void *), + void *userdata) +{ + if (cb(bridge, userdata)) + return; + + if (bridge->subordinate) + pci_walk_bus(bridge->subordinate, cb, userdata); +} + static void cxl_do_recovery(struct pci_dev *pdev) { + pci_ers_result_t status =3D PCI_ERS_RESULT_CAN_RECOVER; + + cxl_walk_bridge(pdev, cxl_report_error_detected, &status); + if (status =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + /* + * If we have native control of AER, clear error status in the device + * that detected the error. If the platform retained control of AER, + * it is responsible for clearing this status. In that case, the + * signaling device may not even be visible to the OS. + */ + if (cxl_error_is_native(pdev)) { + pcie_clear_device_status(pdev); + pci_aer_clear_nonfatal_status(pdev); + pci_aer_clear_fatal_status(pdev); + } } =20 static bool is_cxl_rcd(struct pci_dev *pdev) diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c index 939438a7161a..b238791b7101 100644 --- a/drivers/pci/pcie/cxl_aer.c +++ b/drivers/pci/pcie/cxl_aer.c @@ -52,12 +52,13 @@ static bool is_cxl_mem_dev(struct pci_dev *dev) return true; } =20 -static bool cxl_error_is_native(struct pci_dev *dev) +bool cxl_error_is_native(struct pci_dev *dev) { struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); =20 return (pcie_ports_native || host->native_aer); } +EXPORT_SYMBOL_NS_GPL(cxl_error_is_native, "CXL"); =20 static bool is_internal_error(struct aer_err_info *info) { diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index de6381c690f5..63fceb3e8613 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -21,9 +21,12 @@ #include "portdrv.h" #include "../pci.h" =20 -static pci_ers_result_t merge_result(enum pci_ers_result orig, - enum pci_ers_result new) +pci_ers_result_t merge_result(enum pci_ers_result orig, + enum pci_ers_result new) { + if (new =3D=3D PCI_ERS_RESULT_PANIC) + return PCI_ERS_RESULT_PANIC; + if (new =3D=3D PCI_ERS_RESULT_NO_AER_DRIVER) return PCI_ERS_RESULT_NO_AER_DRIVER; =20 @@ -45,6 +48,7 @@ static pci_ers_result_t merge_result(enum pci_ers_result = orig, =20 return orig; } +EXPORT_SYMBOL_NS_GPL(merge_result, "CXL"); =20 static int report_error_detected(struct pci_dev *dev, pci_channel_state_t state, diff --git a/include/linux/aer.h b/include/linux/aer.h index 0aafcc678e45..f14db635ef90 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -10,6 +10,7 @@ =20 #include #include +#include #include =20 #define AER_NONFATAL 0 @@ -78,6 +79,8 @@ struct cxl_proto_err_work_data { int pci_aer_clear_nonfatal_status(struct pci_dev *dev); void pci_aer_clear_fatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); +pci_ers_result_t merge_result(enum pci_ers_result orig, + enum pci_ers_result new); #else static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) { @@ -85,16 +88,24 @@ static inline int pci_aer_clear_nonfatal_status(struct = pci_dev *dev) } static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } +static inline pci_ers_result_t merge_result(enum pci_ers_result orig, + enum pci_ers_result new) +{ + return PCI_ERS_RESULT_NONE; +} + #endif =20 #if defined(CONFIG_PCIEAER_CXL) void cxl_register_proto_err_work(struct work_struct *work); void cxl_unregister_proto_err_work(void); int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd); +bool cxl_error_is_native(struct pci_dev *dev); #else static inline void cxl_register_proto_err_work(struct work_struct *work) {= } static inline void cxl_unregister_proto_err_work(void) { } static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *= wd) { return 0; } +static inline bool cxl_error_is_native(struct pci_dev *dev) { return 0; } #endif =20 void pci_print_aer(struct pci_dev *dev, int aer_severity, diff --git a/include/linux/pci.h b/include/linux/pci.h index 79326358f641..16a8310e0373 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -868,6 +868,9 @@ enum pci_ers_result { =20 /* No AER capabilities registered for the driver */ PCI_ERS_RESULT_NO_AER_DRIVER =3D (__force pci_ers_result_t) 6, + + /* System is unstable, panic. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:44:28.3284 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ad4b71c-0685-4598-7b51-08ddb5030245 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7680 Content-Type: text/plain; charset="utf-8" The cxl_port driver is intended to manage CXL Endpoint Ports and CXL Switch Ports. Move existing RAS initialization to the cxl_port driver. Restricted CXL Host (RCH) Downstream Port RAS initialization currently resides in cxl/core/pci.c. The PCI source file is not otherwise associated with CXL Port management. Additional CXL Port RAS initialization will be added in future patches to support a CXL Port device's CXL errors. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Joshua Hahn --- drivers/cxl/core/pci.c | 73 -------------------------------------- drivers/cxl/core/regs.c | 2 ++ drivers/cxl/cxl.h | 6 ++++ drivers/cxl/port.c | 78 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 86 insertions(+), 73 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 06464a25d8bd..35c9c50534bf 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -738,79 +738,6 @@ static bool cxl_handle_ras(struct cxl_dev_state *cxlds, =20 #ifdef CONFIG_PCIEAER_CXL =20 -static void cxl_dport_map_rch_aer(struct cxl_dport *dport) -{ - resource_size_t aer_phys; - struct device *host; - u16 aer_cap; - - aer_cap =3D cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base); - if (aer_cap) { - host =3D dport->reg_map.host; - aer_phys =3D aer_cap + dport->rcrb.base; - dport->regs.dport_aer =3D devm_cxl_iomap_block(host, aer_phys, - sizeof(struct aer_capability_regs)); - } -} - -static void cxl_dport_map_ras(struct cxl_dport *dport) -{ - struct cxl_register_map *map =3D &dport->reg_map; - struct device *dev =3D dport->dport_dev; - - if (!map->component_map.ras.valid) - dev_dbg(dev, "RAS registers not found\n"); - else if (cxl_map_component_regs(map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) - dev_dbg(dev, "Failed to map RAS capability.\n"); -} - -static void cxl_disable_rch_root_ints(struct cxl_dport *dport) -{ - void __iomem *aer_base =3D dport->regs.dport_aer; - u32 aer_cmd_mask, aer_cmd; - - if (!aer_base) - return; - - /* - * Disable RCH root port command interrupts. - * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors - * - * This sequence may not be necessary. CXL spec states disabling - * the root cmd register's interrupts is required. But, PCI spec - * shows these are disabled by default on reset. - */ - aer_cmd_mask =3D (PCI_ERR_ROOT_CMD_COR_EN | - PCI_ERR_ROOT_CMD_NONFATAL_EN | - PCI_ERR_ROOT_CMD_FATAL_EN); - aer_cmd =3D readl(aer_base + PCI_ERR_ROOT_COMMAND); - aer_cmd &=3D ~aer_cmd_mask; - writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); -} - -/** - * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport - * @dport: the cxl_dport that needs to be initialized - * @host: host device for devm operations - */ -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) -{ - dport->reg_map.host =3D host; - cxl_dport_map_ras(dport); - - if (dport->rch) { - struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); - - if (!host_bridge->native_aer) - return; - - cxl_dport_map_rch_aer(dport); - cxl_disable_rch_root_ints(dport); - } -} -EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); - static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 5ca7b0eed568..b8e767a9571c 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -199,6 +199,7 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, = resource_size_t addr, =20 return ret_val; } +EXPORT_SYMBOL_NS_GPL(devm_cxl_iomap_block, "CXL"); =20 int cxl_map_component_regs(const struct cxl_register_map *map, struct cxl_component_regs *regs, @@ -517,6 +518,7 @@ u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t= rcrb) =20 return offset; } +EXPORT_SYMBOL_NS_GPL(cxl_rcrb_to_aer, "CXL"); =20 static resource_size_t cxl_rcrb_to_linkcap(struct device *dev, struct cxl_= dport *dport) { diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 3f1695c96abc..c57c160f3e5e 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -313,6 +313,12 @@ int cxl_setup_regs(struct cxl_register_map *map); struct cxl_dport; resource_size_t cxl_rcd_component_reg_phys(struct device *dev, struct cxl_dport *dport); + +u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb); + +void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t add= r, + resource_size_t length); + int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dpor= t); =20 #define CXL_RESOURCE_NONE ((resource_size_t) -1) diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index fe4b593331da..021f35145c65 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -6,6 +6,7 @@ =20 #include "cxlmem.h" #include "cxlpci.h" +#include "cxl.h" =20 /** * DOC: cxl port @@ -57,6 +58,83 @@ static int discover_region(struct device *dev, void *unu= sed) return 0; } =20 +#ifdef CONFIG_PCIEAER_CXL + +static void cxl_dport_map_rch_aer(struct cxl_dport *dport) +{ + resource_size_t aer_phys; + struct device *host; + u16 aer_cap; + + aer_cap =3D cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base); + if (aer_cap) { + host =3D dport->reg_map.host; + aer_phys =3D aer_cap + dport->rcrb.base; + dport->regs.dport_aer =3D devm_cxl_iomap_block(host, aer_phys, + sizeof(struct aer_capability_regs)); + } +} + +static void cxl_dport_map_ras(struct cxl_dport *dport) +{ + struct cxl_register_map *map =3D &dport->reg_map; + struct device *dev =3D dport->dport_dev; + + if (!map->component_map.ras.valid) + dev_dbg(dev, "RAS registers not found\n"); + else if (cxl_map_component_regs(map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(dev, "Failed to map RAS capability.\n"); +} + +static void cxl_disable_rch_root_ints(struct cxl_dport *dport) +{ + void __iomem *aer_base =3D dport->regs.dport_aer; + u32 aer_cmd_mask, aer_cmd; + + if (!aer_base) + return; + + /* + * Disable RCH root port command interrupts. + * CXL 3.2 12.2.1.1 - RCH Downstream Port-detected Errors + * + * This sequence may not be necessary. CXL spec states disabling + * the root cmd register's interrupts is required. But, PCI spec + * shows these are disabled by default on reset. + */ + aer_cmd_mask =3D (PCI_ERR_ROOT_CMD_COR_EN | + PCI_ERR_ROOT_CMD_NONFATAL_EN | + PCI_ERR_ROOT_CMD_FATAL_EN); + aer_cmd =3D readl(aer_base + PCI_ERR_ROOT_COMMAND); + aer_cmd &=3D ~aer_cmd_mask; + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); +} + +/** + * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport + * @dport: the cxl_dport that needs to be initialized + * @host: host device for devm operations + */ +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) +{ + dport->reg_map.host =3D host; + cxl_dport_map_ras(dport); + + if (dport->rch) { + struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); + + if (!host_bridge->native_aer) + return; + + cxl_dport_map_rch_aer(dport); + cxl_disable_rch_root_ints(dport); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); + +#endif /* CONFIG_PCIEAER_CXL */ + static int cxl_switch_port_probe(struct cxl_port *port) { struct cxl_hdm *cxlhdm; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099D6.mail.protection.outlook.com (10.167.17.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8880.14 via Frontend Transport; Thu, 26 Jun 2025 22:44:39 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 26 Jun 2025 17:44:38 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v10 09/17] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Date: Thu, 26 Jun 2025 17:42:44 -0500 Message-ID: <20250626224252.1415009-10-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250626224252.1415009-1-terry.bowman@amd.com> References: <20250626224252.1415009-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D6:EE_|MW4PR12MB6729:EE_ X-MS-Office365-Filtering-Correlation-Id: 23a3e746-104b-4717-b696-08ddb50308c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|36860700013|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:44:39.2558 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23a3e746-104b-4717-b696-08ddb50308c8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6729 Content-Type: text/plain; charset="utf-8" CXL Endpoint (EP) Ports may include Root Ports (RP) or Downstream Switch Ports (DSP). CXL RPs and DSPs contain RAS registers that require memory mapping to enable RAS logging. This initialization is currently missing and must be added for CXL RPs and DSPs. Update cxl_dport_init_ras_reporting() to support RP and DSP RAS mapping. Add alongside the existing Restricted CXL Host Downstream Port RAS mapping. Update cxl_endpoint_port_probe() to invoke cxl_dport_init_ras_reporting(). This will initiate the RAS mapping for CXL RPs and DSPs when each CXL EP is created and added to the EP port. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Tested-by: Joshua Hahn --- drivers/cxl/cxl.h | 2 ++ drivers/cxl/mem.c | 3 ++- drivers/cxl/port.c | 58 +++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index c57c160f3e5e..d696d419bd5a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -590,6 +590,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @uport_regs: mapped component registers * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation orde= ring * @commit_end: cursor to track highest committed decoder for commit order= ing @@ -610,6 +611,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + struct cxl_component_regs uport_regs; int nr_dports; int hdm_end; int commit_end; diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 6e6777b7bafb..d2155f45240d 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -166,7 +166,8 @@ static int cxl_mem_probe(struct device *dev) else endpoint_parent =3D &parent_port->dev; =20 - cxl_dport_init_ras_reporting(dport, dev); + if (dport->rch) + cxl_dport_init_ras_reporting(dport, dev); =20 scoped_guard(device, endpoint_parent) { if (!endpoint_parent->driver) { diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 021f35145c65..b52f82925891 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -111,6 +111,17 @@ static void cxl_disable_rch_root_ints(struct cxl_dport= *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } =20 +static void cxl_uport_init_ras_reporting(struct cxl_port *port, + struct device *host) +{ + struct cxl_register_map *map =3D &port->reg_map; + + map->host =3D host; + if (cxl_map_component_regs(map, &port->uport_regs, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(&port->dev, "Failed to map RAS capability\n"); +} + /** * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized @@ -119,7 +130,6 @@ static void cxl_disable_rch_root_ints(struct cxl_dport = *dport) void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) { dport->reg_map.host =3D host; - cxl_dport_map_ras(dport); =20 if (dport->rch) { struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); @@ -127,12 +137,54 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *d= port, struct device *host) if (!host_bridge->native_aer) return; =20 + cxl_dport_map_ras(dport); cxl_dport_map_rch_aer(dport); cxl_disable_rch_root_ints(dport); + return; } + + if (cxl_map_component_regs(&dport->reg_map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(dport->dport_dev, "Failed to map RAS capability\n"); + } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 +static void cxl_switch_port_init_ras(struct cxl_port *port) +{ + if (is_cxl_root(to_cxl_port(port->dev.parent))) + return; + + /* May have upstream DSP or RP */ + if (port->parent_dport && dev_is_pci(port->parent_dport->dport_dev)) { + struct pci_dev *pdev =3D to_pci_dev(port->parent_dport->dport_dev); + + if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM)) + cxl_dport_init_ras_reporting(port->parent_dport, &port->dev); + } + + cxl_uport_init_ras_reporting(port, &port->dev); +} + +static void cxl_endpoint_port_init_ras(struct cxl_port *port) +{ + struct cxl_dport *dport; + struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + struct cxl_port *parent_port __free(put_cxl_port) =3D + cxl_mem_find_port(cxlmd, &dport); + + if (!dport || !dev_is_pci(dport->dport_dev)) { + dev_err(&port->dev, "CXL port topology not found\n"); + return; + } + + cxl_dport_init_ras_reporting(dport, cxlmd->cxlds->dev); +} + +#else +static void cxl_endpoint_port_init_ras(struct cxl_port *port) { } +static void cxl_switch_port_init_ras(struct cxl_port *port) { } #endif /* CONFIG_PCIEAER_CXL */ =20 static int cxl_switch_port_probe(struct cxl_port *port) @@ -149,6 +201,8 @@ static int cxl_switch_port_probe(struct cxl_port *port) =20 cxl_switch_parse_cdat(port); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:44:50.2873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: acfcac6e-4ee6-4d84-96e9-08ddb5030f5b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9151 Content-Type: text/plain; charset="utf-8" CXL PCIe Port Protocol Error handling support will be added to the CXL drivers in the future. In preparation, rename the existing interfaces to support handling all CXL PCIe Port Protocol Errors. The driver's RAS support functions currently rely on a 'struct cxl_dev_state' type parameter, which is not available for CXL Port devices. However, since the same CXL RAS capability structure is needed across most CXL components and devices, a common handling approach should be adopted. To accommodate this, update the __cxl_handle_cor_ras() and __cxl_handle_ras() functions to use a `struct device` instead of `struct cxl_dev_state`. No functional changes are introduced. [1] CXL 3.1 Spec, 8.2.4 CXL.cache and CXL.mem Registers Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Joshua Hahn --- drivers/cxl/core/pci.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 35c9c50534bf..9b464f9c55c1 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -664,8 +664,8 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static void cxl_handle_cor_ras(struct device *dev, + void __iomem *ras_base) { void __iomem *addr; u32 status; @@ -677,7 +677,7 @@ static void cxl_handle_cor_ras(struct cxl_dev_state *cx= lds, status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); } } =20 @@ -702,8 +702,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -730,7 +729,7 @@ static bool cxl_handle_ras(struct cxl_dev_state *cxlds, } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -741,13 +740,13 @@ static bool cxl_handle_ras(struct cxl_dev_state *cxld= s, static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return cxl_handle_cor_ras(cxlds, dport->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras); } =20 static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return cxl_handle_ras(cxlds, dport->regs.ras); + return cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); } =20 /* @@ -844,7 +843,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_cor_ras(cxlds, cxlds->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -873,7 +872,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); + ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } =20 =20 --=20 2.34.1 From nobody Wed Oct 8 14:20:54 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2056.outbound.protection.outlook.com [40.107.243.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A33D22127C; Thu, 26 Jun 2025 22:45:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:45:01.5858 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 89d24f5a-6459-4f8f-ae9b-08ddb5031617 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8149 Content-Type: text/plain; charset="utf-8" The CXL RAS handlers do not currently log if the RAS registers are unmapped. This is needed in order to help debug CXL error handling. Update the CXL driver to log a warning message if the RAS register block is unmapped during RAS error handling. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Tested-by: Joshua Hahn --- drivers/cxl/core/pci.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 9b464f9c55c1..c9a4b528e0b8 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -670,8 +670,10 @@ static void cxl_handle_cor_ras(struct device *dev, void __iomem *addr; u32 status; =20 - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return; + } =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); @@ -709,8 +711,10 @@ static bool cxl_handle_ras(struct device *dev, void __= iomem *ras_base) u32 status; u32 fe; =20 - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return false; + } =20 addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status =3D readl(addr); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:45:12.9846 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f755945-2964-4693-3a41-08ddb5031ce3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8103 Content-Type: text/plain; charset="utf-8" CXL currently has separate trace routines for CXL Port errors and CXL Endpoint errors. This is inconvenient for the user because they must enable 2 sets of trace routines. Make updates to the trace logging such that a single trace routine logs both CXL Endpoint and CXL Port protocol errors. Keep the trace log fields 'memdev' and 'host'. While these are not accurate for non-Endpoints the fields will remain as-is to prevent breaking userspace RAS trace consumers. Add serial number parameter to the trace logging. This is used for EPs and 0 is provided for CXL port devices without a serial number. Below is output of correctable and uncorrectable protocol error logging. CXL Root Port and CXL Endpoint examples are included below. Root Port: cxl_aer_correctable_error: memdev=3D0000:0c:00.0 host=3Dpci0000:0c serial: = 0 status=3D'CRC Threshold Hit' cxl_aer_uncorrectable_error: memdev=3D0000:0c:00.0 host=3Dpci0000:0c serial= : 0 status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enabl= e Parity Error' Endpoint: cxl_aer_correctable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial=3D0 sta= tus=3D'CRC Threshold Hit' cxl_aer_uncorrectable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial: 0 st= atus: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Pari= ty Error' Signed-off-by: Terry Bowman Tested-by: Joshua Hahn --- drivers/cxl/core/pci.c | 19 ++++----- drivers/cxl/core/ras.c | 14 ++++--- drivers/cxl/core/trace.h | 84 +++++++++------------------------------- 3 files changed, 37 insertions(+), 80 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index c9a4b528e0b8..156ce094a8b9 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -664,8 +664,8 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -static void cxl_handle_cor_ras(struct device *dev, - void __iomem *ras_base) +static void cxl_handle_cor_ras(struct device *dev, u64 serial, + void __iomem *ras_base) { void __iomem *addr; u32 status; @@ -679,7 +679,7 @@ static void cxl_handle_cor_ras(struct device *dev, status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); + trace_cxl_aer_correctable_error(dev, serial, status); } } =20 @@ -704,7 +704,8 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) +static bool cxl_handle_ras(struct device *dev, u64 serial, + void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -733,7 +734,7 @@ static bool cxl_handle_ras(struct device *dev, void __i= omem *ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + trace_cxl_aer_uncorrectable_error(dev, serial, status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -744,13 +745,13 @@ static bool cxl_handle_ras(struct device *dev, void _= _iomem *ras_base) static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras); } =20 static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); + return cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras); } =20 /* @@ -847,7 +848,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -876,7 +877,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras= ); } =20 =20 diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 962dc94fed8c..9588b39faabd 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -13,7 +13,7 @@ static void cxl_cper_trace_corr_port_prot_err(struct pci_= dev *pdev, { u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; =20 - trace_cxl_port_aer_correctable_error(&pdev->dev, status); + trace_cxl_aer_correctable_error(&pdev->dev, 0, status); } =20 static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev, @@ -28,8 +28,8 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pc= i_dev *pdev, else fe =3D status; =20 - trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe, - ras_cap.header_log); + trace_cxl_aer_uncorrectable_error(&pdev->dev, 0, status, fe, + ras_cap.header_log); } =20 static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev, @@ -42,7 +42,8 @@ static void cxl_cper_trace_corr_prot_err(struct pci_dev *= pdev, if (!cxlds) return; =20 - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + trace_cxl_aer_correctable_error(&cxlds->cxlmd->dev, cxlds->serial, + status); } =20 static void cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev, @@ -62,8 +63,9 @@ static void cxl_cper_trace_uncorr_prot_err(struct pci_dev= *pdev, else fe =3D status; =20 - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, - ras_cap.header_log); + trace_cxl_aer_uncorrectable_error(&cxlds->cxlmd->dev, + cxlds->serial, status, + fe, ras_cap.header_log); } =20 static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *d= ata) diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index 25ebfbc1616c..494d6db461a7 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -48,49 +48,22 @@ { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ ) =20 -TRACE_EVENT(cxl_port_aer_uncorrectable_error, - TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), - TP_ARGS(dev, status, fe, hl), - TP_STRUCT__entry( - __string(device, dev_name(dev)) - __string(host, dev_name(dev->parent)) - __field(u32, status) - __field(u32, first_error) - __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) - ), - TP_fast_assign( - __assign_str(device); - __assign_str(host); - __entry->status =3D status; - __entry->first_error =3D fe; - /* - * Embed the 512B headerlog data for user app retrieval and - * parsing, but no need to print this in the trace buffer. - */ - memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); - ), - TP_printk("device=3D%s host=3D%s status: '%s' first_error: '%s'", - __get_str(device), __get_str(host), - show_uc_errs(__entry->status), - show_uc_errs(__entry->first_error) - ) -); - TRACE_EVENT(cxl_aer_uncorrectable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), - TP_ARGS(cxlmd, status, fe, hl), + TP_PROTO(struct device *dev, u64 serial, u32 status, u32 fe, + u32 *hl), + TP_ARGS(dev, serial, status, fe, hl), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(name, dev_name(dev)) + __string(parent, dev_name(dev->parent)) __field(u64, serial) __field(u32, status) __field(u32, first_error) __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) ), TP_fast_assign( - __assign_str(memdev); - __assign_str(host); - __entry->serial =3D cxlmd->cxlds->serial; + __assign_str(name); + __assign_str(parent); + __entry->serial =3D serial; __entry->status =3D status; __entry->first_error =3D fe; /* @@ -99,8 +72,8 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, */ memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); ), - TP_printk("memdev=3D%s host=3D%s serial=3D%lld: status: '%s' first_error:= '%s'", - __get_str(memdev), __get_str(host), __entry->serial, + TP_printk("memdev=3D%s host=3D%s serial=3D%lld status=3D'%s' first_error= =3D'%s'", + __get_str(name), __get_str(parent), __entry->serial, show_uc_errs(__entry->status), show_uc_errs(__entry->first_error) ) @@ -124,42 +97,23 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ ) =20 -TRACE_EVENT(cxl_port_aer_correctable_error, - TP_PROTO(struct device *dev, u32 status), - TP_ARGS(dev, status), - TP_STRUCT__entry( - __string(device, dev_name(dev)) - __string(host, dev_name(dev->parent)) - __field(u32, status) - ), - TP_fast_assign( - __assign_str(device); - __assign_str(host); - __entry->status =3D status; - ), - TP_printk("device=3D%s host=3D%s status=3D'%s'", - __get_str(device), __get_str(host), - show_ce_errs(__entry->status) - ) -); - TRACE_EVENT(cxl_aer_correctable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), - TP_ARGS(cxlmd, status), + TP_PROTO(struct device *dev, u64 serial, u32 status), + TP_ARGS(dev, serial, status), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(name, dev_name(dev)) + __string(parent, dev_name(dev->parent)) __field(u64, serial) __field(u32, status) ), TP_fast_assign( - __assign_str(memdev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:45:23.8786 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d32e3929-40bf-4d79-405a-08ddb5032361 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6821 Content-Type: text/plain; charset="utf-8" Update cxl_handle_cor_ras() to exit early in the case there is no RAS errors detected after applying the status mask. This change will make the correctable handler's implementation consistent with the uncorrectable handler, cxl_handle_ras(). Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Joshua Hahn --- drivers/cxl/core/pci.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 156ce094a8b9..887b54cf3395 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -677,10 +677,11 @@ static void cxl_handle_cor_ras(struct device *dev, u6= 4 serial, =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(dev, serial, status); - } + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) + return; + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + + trace_cxl_aer_correctable_error(dev, serial, status); } =20 /* CXL spec rev3.0 8.2.4.16.1 */ --=20 2.34.1 From nobody Wed Oct 8 14:20:54 2025 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2059.outbound.protection.outlook.com [40.107.96.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 701BC22ACF3; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:45:34.8828 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 489a07da-9b54-43c4-a076-08ddb50329f0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6045 Content-Type: text/plain; charset="utf-8" CXL Endpoint protocol errors are currently handled using PCI error handlers. The CXL Endpoint requires CXL specific handling in the case of uncorrectable error (UCE) handling not provided by the PCI handlers. Add CXL specific handlers for CXL Endpoints. Rename the existing cxl_error_handlers to be pci_error_handlers to more correctly indicate the error type and follow naming consistency. The PCI handlers will be called if the CXL device is not trained for alternate protocol (CXL). Update the CXL Endpoint PCI handlers to call the CXL UCE handlers. The existing EP UCE handler includes checks for various results. These are no longer needed because CXL UCE recovery will not be attempted. Implement cxl_handle_ras() to return PCI_ERS_RESULT_NONE or PCI_ERS_RESULT_PANIC. The CXL UCE handler is called by cxl_do_recovery() that acts on the return value. In the case of the PCI handler path, call panic() if the result is PCI_ERS_RESULT_PANIC. Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Joshua Hahn --- drivers/cxl/core/native_ras.c | 15 ++++--- drivers/cxl/core/pci.c | 77 ++++++++++++++++++----------------- drivers/cxl/cxl.h | 4 ++ drivers/cxl/cxlpci.h | 6 +-- drivers/cxl/pci.c | 8 ++-- 5 files changed, 59 insertions(+), 51 deletions(-) diff --git a/drivers/cxl/core/native_ras.c b/drivers/cxl/core/native_ras.c index 19f8f2ac8376..89b65a35f2c0 100644 --- a/drivers/cxl/core/native_ras.c +++ b/drivers/cxl/core/native_ras.c @@ -7,18 +7,20 @@ #include #include #include +#include =20 static int cxl_report_error_detected(struct pci_dev *pdev, void *data) { pci_ers_result_t vote, *result =3D data; + struct device *dev =3D &pdev->dev; =20 if ((pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) && (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_RC_END)) return 0; =20 - guard(device)(&pdev->dev); + guard(device)(dev); =20 - vote =3D cxl_error_detected(pdev, pci_channel_io_frozen); + vote =3D cxl_error_detected(dev); *result =3D merge_result(*result, vote); =20 return 0; @@ -82,16 +84,17 @@ static bool is_cxl_rcd(struct pci_dev *pdev) static int cxl_rch_handle_error_iter(struct pci_dev *pdev, void *data) { struct cxl_proto_error_info *err_info =3D data; + struct device *dev =3D &pdev->dev; =20 - guard(device)(&pdev->dev); + guard(device)(dev); =20 if (!is_cxl_rcd(pdev) || !cxl_pci_drv_bound(pdev)) return 0; =20 if (err_info->severity =3D=3D AER_CORRECTABLE) - cxl_cor_error_detected(pdev); + cxl_cor_error_detected(dev); else - cxl_error_detected(pdev, pci_channel_io_frozen); + cxl_error_detected(dev); =20 return 1; } @@ -126,7 +129,7 @@ static void cxl_handle_proto_error(struct cxl_proto_err= or_info *err_info) aer + PCI_ERR_COR_STATUS, 0, PCI_ERR_COR_INTERNAL); =20 - cxl_cor_error_detected(pdev); + cxl_cor_error_detected(&pdev->dev); =20 pcie_clear_device_status(pdev); } else { diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 887b54cf3395..7209ffb5c2fe 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -705,8 +705,8 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool cxl_handle_ras(struct device *dev, u64 serial, - void __iomem *ras_base) +static pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, + void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -715,13 +715,13 @@ static bool cxl_handle_ras(struct device *dev, u64 se= rial, =20 if (!ras_base) { dev_warn_once(dev, "CXL RAS register block is not mapped"); - return false; + return PCI_ERS_RESULT_NONE; } =20 addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status =3D readl(addr); if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) - return false; + return PCI_ERS_RESULT_NONE; =20 /* If multiple errors, log header points to first error from ctrl reg */ if (hweight32(status) > 1) { @@ -738,7 +738,7 @@ static bool cxl_handle_ras(struct device *dev, u64 seri= al, trace_cxl_aer_uncorrectable_error(dev, serial, status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 - return true; + return PCI_ERS_RESULT_PANIC; } =20 #ifdef CONFIG_PCIEAER_CXL @@ -833,13 +833,14 @@ static void cxl_handle_rdport_errors(struct cxl_dev_s= tate *cxlds) static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { } #endif =20 -void cxl_cor_error_detected(struct pci_dev *pdev) +void cxl_cor_error_detected(struct device *dev) { + struct pci_dev *pdev =3D to_pci_dev(dev); struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct device *dev =3D &cxlds->cxlmd->dev; + struct device *cxlmd_dev =3D &cxlds->cxlmd->dev; =20 - scoped_guard(device, dev) { - if (!dev->driver) { + scoped_guard(device, cxlmd_dev) { + if (!cxlmd_dev->driver) { dev_warn(&pdev->dev, "%s: memdev disabled, abort error handling\n", dev_name(dev)); @@ -854,20 +855,26 @@ void cxl_cor_error_detected(struct pci_dev *pdev) } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); =20 -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +void pci_cor_error_detected(struct pci_dev *pdev) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; + cxl_cor_error_detected(&pdev->dev); +} +EXPORT_SYMBOL_NS_GPL(pci_cor_error_detected, "CXL"); =20 - scoped_guard(device, dev) { - if (!dev->driver) { +pci_ers_result_t cxl_error_detected(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct device *cxlmd_dev =3D &cxlds->cxlmd->dev; + pci_ers_result_t ue; + + scoped_guard(device, cxlmd_dev) { + + if (!cxlmd_dev->driver) { dev_warn(&pdev->dev, "%s: memdev disabled, abort error handling\n", dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; + return PCI_ERS_RESULT_PANIC; } =20 if (cxlds->rcd) @@ -881,29 +888,23 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *p= dev, ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras= ); } =20 - - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); - return PCI_ERS_RESULT_DISCONNECT; - } - return PCI_ERS_RESULT_NEED_RESET; + return ue; } EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); =20 +pci_ers_result_t pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error) +{ + pci_ers_result_t rc; + + rc =3D cxl_error_detected(&pdev->dev); + if (rc =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(pci_error_detected, "CXL"); + static int cxl_flit_size(struct pci_dev *pdev) { if (cxl_pci_flit_256(pdev)) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index d696d419bd5a..a2eedc8a82e8 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -11,6 +11,7 @@ #include #include #include +#include =20 extern const struct nvdimm_security_ops *cxl_security_ops; =20 @@ -797,6 +798,9 @@ static inline int cxl_root_decoder_autoremove(struct de= vice *host, } int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *end= point); =20 +void cxl_cor_error_detected(struct device *dev); +pci_ers_result_t cxl_error_detected(struct device *dev); + /** * struct cxl_endpoint_dvsec_info - Cached DVSEC info * @mem_enabled: cached value of mem_enabled in the DVSEC at init time diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index ed3c9701b79f..e69a47f0cd94 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -133,8 +133,8 @@ struct cxl_dev_state; int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhd= m, struct cxl_endpoint_dvsec_info *info); void read_cdat_data(struct cxl_port *port); -void cxl_cor_error_detected(struct pci_dev *pdev); -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state); +void pci_cor_error_detected(struct pci_dev *pdev); +pci_ers_result_t pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error); bool cxl_pci_drv_bound(struct pci_dev *pdev); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index cae049f9ae3e..91fab33094a9 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1112,11 +1112,11 @@ static void cxl_reset_done(struct pci_dev *pdev) } } =20 -static const struct pci_error_handlers cxl_error_handlers =3D { - .error_detected =3D cxl_error_detected, +static const struct pci_error_handlers pci_error_handlers =3D { + .error_detected =3D pci_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, - .cor_error_detected =3D cxl_cor_error_detected, + .cor_error_detected =3D pci_cor_error_detected, .reset_done =3D cxl_reset_done, }; =20 @@ -1124,7 +1124,7 @@ static struct pci_driver cxl_pci_driver =3D { .name =3D KBUILD_MODNAME, .id_table =3D cxl_mem_pci_tbl, .probe =3D cxl_pci_probe, - .err_handler =3D &cxl_error_handlers, + .err_handler =3D &pci_error_handlers, .dev_groups =3D cxl_rcd_groups, .driver =3D { .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, --=20 2.34.1 From nobody Wed Oct 8 14:20:54 2025 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2078.outbound.protection.outlook.com [40.107.223.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E29D230BC9; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:45:45.9510 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a3eff1f-3a93-4e6f-5296-08ddb5033090 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8986 Content-Type: text/plain; charset="utf-8" Introduce CXL error handlers for CXL Port devices. Add functions cxl_port_cor_error_detected() and cxl_port_error_detected(). These will serve as the handlers for all CXL Port devices. Introduce cxl_get_ras_base() to provide the RAS base address needed by the handlers. Update cxl_handle_proto_error() to call the CXL Port or CXL Endpoint handler depending on which CXL device reports the error. Implement cxl_get_ras_base() to return the cached RAS register address of a CXL Root Port, CXL Downstream Port, or CXL Upstream Port. Introduce get_pci_cxl_host_dev() to return the host responsible for releasing the RAS mapped resources. CXL endpoints do not use a host to manage its resources, allow for NULL in the case of an EP. Use reference count increment on the host to prevent resource release. Make the caller responsible for the reference decrement. Update the AER driver's is_cxl_error() to remove the filter PCI type check because CXL Port devices are now supported. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Joshua Hahn --- drivers/cxl/core/core.h | 2 + drivers/cxl/core/native_ras.c | 74 ++++++++++++++++++++++++++++++++--- drivers/cxl/core/pci.c | 60 ++++++++++++++++++++++++++++ drivers/cxl/core/port.c | 4 +- drivers/cxl/cxl.h | 5 +++ drivers/pci/pcie/cxl_aer.c | 17 ++++---- 6 files changed, 145 insertions(+), 17 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 4c08bb92e2f9..f5a2571fc208 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -122,6 +122,8 @@ void cxl_ras_exit(void); int cxl_gpf_port_setup(struct cxl_dport *dport); int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res, int nid, resource_size_t *size); +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport); =20 #ifdef CONFIG_PCIEAER_CXL void cxl_native_ras_init(void); diff --git a/drivers/cxl/core/native_ras.c b/drivers/cxl/core/native_ras.c index 89b65a35f2c0..c7f9a237a1a2 100644 --- a/drivers/cxl/core/native_ras.c +++ b/drivers/cxl/core/native_ras.c @@ -9,18 +9,74 @@ #include #include =20 +int match_uport(struct device *dev, const void *data) +{ + const struct device *uport_dev =3D data; + struct cxl_port *port; + + if (!is_cxl_port(dev)) + return 0; + + port =3D to_cxl_port(dev); + + return port->uport_dev =3D=3D uport_dev; +} +EXPORT_SYMBOL_NS_GPL(match_uport, "CXL"); + +/* + * Return 'struct device *' responsible for freeing pdev's CXL resources. + * Caller is responsible for reference count decrementing the return + * 'struct device *'. + * + * pdev: CXL PCI device to find the host device. + */ +static struct device *get_pci_cxl_host_dev(struct pci_dev *pdev) +{ + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport =3D NULL; + struct cxl_port *port =3D find_cxl_port(&pdev->dev, &dport); + + if (!port) + return NULL; + + return &port->dev; + } + case PCI_EXP_TYPE_UPSTREAM: + { + struct device *port_dev =3D bus_find_device(&cxl_bus_type, NULL, + &pdev->dev, match_uport); + + if (!port_dev || !is_cxl_port(port_dev)) + return NULL; + + return port_dev; + } + /* Endpoint resources are managed by endpoint itself */ + case PCI_EXP_TYPE_ENDPOINT: + case PCI_EXP_TYPE_RC_END: + return NULL; + } + + pci_warn_once(pdev, "Error: Unsupported device type (%X)", pci_pcie_type(= pdev)); + return NULL; +} + static int cxl_report_error_detected(struct pci_dev *pdev, void *data) { + struct device *host_dev __free(put_device) =3D get_pci_cxl_host_dev(pdev); pci_ers_result_t vote, *result =3D data; struct device *dev =3D &pdev->dev; =20 - if ((pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) && - (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_RC_END)) - return 0; - guard(device)(dev); =20 - vote =3D cxl_error_detected(dev); + if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_RC_END)) + vote =3D cxl_error_detected(dev); + else + vote =3D cxl_port_error_detected(dev); *result =3D merge_result(*result, vote); =20 return 0; @@ -112,6 +168,7 @@ static void cxl_handle_proto_error(struct cxl_proto_err= or_info *err_info) PCI_FUNC(err_info->devfn)); return; } + struct device *host_dev __free(put_device) =3D get_pci_cxl_host_dev(pdev); =20 /* * Internal errors of an RCEC indicate an AER error in an @@ -122,6 +179,7 @@ static void cxl_handle_proto_error(struct cxl_proto_err= or_info *err_info) return pcie_walk_rcec(pdev, cxl_rch_handle_error_iter, err_info); =20 if (err_info->severity =3D=3D AER_CORRECTABLE) { + struct device *dev =3D &pdev->dev; int aer =3D pdev->aer_cap; =20 if (aer) @@ -129,7 +187,11 @@ static void cxl_handle_proto_error(struct cxl_proto_er= ror_info *err_info) aer + PCI_ERR_COR_STATUS, 0, PCI_ERR_COR_INTERNAL); =20 - cxl_cor_error_detected(&pdev->dev); + if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ENDPOINT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_RC_END)) + cxl_cor_error_detected(dev); + else + cxl_port_cor_error_detected(dev); =20 pcie_clear_device_status(pdev); } else { diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 7209ffb5c2fe..7a83408ad0bb 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -743,6 +743,66 @@ static pci_ers_result_t cxl_handle_ras(struct device *= dev, u64 serial, =20 #ifdef CONFIG_PCIEAER_CXL =20 +static void __iomem *cxl_get_ras_base(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport =3D NULL; + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port(&pdev->dev,= &dport); + + if (!dport || !dport->dport_dev) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + + if (!dport) + return NULL; + + return dport->regs.ras; + } + case PCI_EXP_TYPE_UPSTREAM: + { + struct cxl_port *port; + struct device *dev __free(put_device) =3D bus_find_device(&cxl_bus_type,= NULL, + &pdev->dev, match_uport); + + if (!dev || !is_cxl_port(dev)) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + + port =3D to_cxl_port(dev); + if (!port) + return NULL; + + return port->uport_regs.ras; + } + } + + pci_warn_once(pdev, "Error: Unsupported device type (%X)", pci_pcie_type(= pdev)); + return NULL; +} + +void cxl_port_cor_error_detected(struct device *dev) +{ + void __iomem *ras_base =3D cxl_get_ras_base(dev); + + cxl_handle_cor_ras(dev, 0, ras_base); +} +EXPORT_SYMBOL_NS_GPL(cxl_port_cor_error_detected, "CXL"); + +pci_ers_result_t cxl_port_error_detected(struct device *dev) +{ + void __iomem *ras_base =3D cxl_get_ras_base(dev); + + return cxl_handle_ras(dev, 0, ras_base); +} +EXPORT_SYMBOL_NS_GPL(cxl_port_error_detected, "CXL"); + static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 8e8f21197c86..c76a1289e24e 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1341,8 +1341,8 @@ static struct cxl_port *__find_cxl_port(struct cxl_fi= nd_port_ctx *ctx) return NULL; } =20 -static struct cxl_port *find_cxl_port(struct device *dport_dev, - struct cxl_dport **dport) +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx =3D { .dport_dev =3D dport_dev, diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index a2eedc8a82e8..19eb33a7de6a 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -801,6 +801,9 @@ int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, s= truct cxl_port *endpoint) void cxl_cor_error_detected(struct device *dev); pci_ers_result_t cxl_error_detected(struct device *dev); =20 +void cxl_port_cor_error_detected(struct device *dev); +pci_ers_result_t cxl_port_error_detected(struct device *dev); + /** * struct cxl_endpoint_dvsec_info - Cached DVSEC info * @mem_enabled: cached value of mem_enabled in the DVSEC at init time @@ -915,6 +918,8 @@ void cxl_coordinates_combine(struct access_coordinate *= out, =20 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); =20 +int match_uport(struct device *dev, const void *data); + /* * Unit test builds overrides this to __weak, find the 'strong' version * of these symbols in tools/testing/cxl/. diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c index b238791b7101..38dc82df0baf 100644 --- a/drivers/pci/pcie/cxl_aer.c +++ b/drivers/pci/pcie/cxl_aer.c @@ -73,11 +73,6 @@ bool is_cxl_error(struct pci_dev *pdev, struct aer_err_i= nfo *info) if (!info || !info->is_cxl) return false; =20 - /* Only CXL Endpoints are currently supported */ - if ((pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) && - (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_RC_EC)) - return false; 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Thu, 26 Jun 2025 17:45:55 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v10 16/17] CXL/PCI: Enable CXL protocol errors during CXL Port probe Date: Thu, 26 Jun 2025 17:42:51 -0500 Message-ID: <20250626224252.1415009-17-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250626224252.1415009-1-terry.bowman@amd.com> References: <20250626224252.1415009-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D3:EE_|PH8PR12MB6841:EE_ X-MS-Office365-Filtering-Correlation-Id: 02e06c24-babb-4f69-a001-08ddb50337a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|1800799024|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:45:57.8955 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02e06c24-babb-4f69-a001-08ddb50337a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6841 Content-Type: text/plain; charset="utf-8" CXL protocol errors are not enabled for all CXL devices after boot. These must be enabled inorder to process CXL protocol errors. Export the AER service driver's pci_aer_unmask_internal_errors(). Introduce cxl_unmask_proto_interrupts() to call pci_aer_unmask_internal_err= ors(). pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized. But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable A= ER correctable internal errors and uncorrectable internal errors for all CXL devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Tested-by: Joshua Hahn --- drivers/cxl/port.c | 29 +++++++++++++++++++++++++++-- drivers/pci/pcie/cxl_aer.c | 3 ++- include/linux/aer.h | 1 + 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index b52f82925891..b90f5efa5904 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -3,6 +3,7 @@ #include #include #include +#include =20 #include "cxlmem.h" #include "cxlpci.h" @@ -60,6 +61,21 @@ static int discover_region(struct device *dev, void *unu= sed) =20 #ifdef CONFIG_PCIEAER_CXL =20 +static void cxl_unmask_proto_interrupts(struct device *dev) +{ + struct pci_dev *pdev __free(pci_dev_put) =3D + pci_dev_get(to_pci_dev(dev)); + + if (!pdev->aer_cap) { + pdev->aer_cap =3D pci_find_ext_capability(pdev, + PCI_EXT_CAP_ID_ERR); + if (!pdev->aer_cap) + return; + } + + pci_aer_unmask_internal_errors(pdev); +} + static void cxl_dport_map_rch_aer(struct cxl_dport *dport) { resource_size_t aer_phys; @@ -118,8 +134,12 @@ static void cxl_uport_init_ras_reporting(struct cxl_po= rt *port, =20 map->host =3D host; if (cxl_map_component_regs(map, &port->uport_regs, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_dbg(&port->dev, "Failed to map RAS capability\n"); + return; + } + + cxl_unmask_proto_interrupts(port->uport_dev); } =20 /** @@ -144,9 +164,12 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) } =20 if (cxl_map_component_regs(&dport->reg_map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_dbg(dport->dport_dev, "Failed to map RAS capability\n"); + return; + } =20 + cxl_unmask_proto_interrupts(dport->dport_dev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 @@ -180,6 +203,8 @@ static void cxl_endpoint_port_init_ras(struct cxl_port = *port) } =20 cxl_dport_init_ras_reporting(dport, cxlmd->cxlds->dev); + + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev); } =20 #else diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c index 38dc82df0baf..3c5bf162607c 100644 --- a/drivers/pci/pcie/cxl_aer.c +++ b/drivers/pci/pcie/cxl_aer.c @@ -18,7 +18,7 @@ * Note: AER must be enabled and supported by the device which must be * checked in advance, e.g. with pcie_aer_is_native(). */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +void pci_aer_unmask_internal_errors(struct pci_dev *dev) { int aer =3D dev->aer_cap; u32 mask; @@ -31,6 +31,7 @@ static void pci_aer_unmask_internal_errors(struct pci_dev= *dev) mask &=3D ~PCI_ERR_COR_INTERNAL; pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); } +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); =20 static bool is_cxl_mem_dev(struct pci_dev *dev) { diff --git a/include/linux/aer.h b/include/linux/aer.h index f14db635ef90..8fb1eca97c37 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -113,5 +113,6 @@ void pci_print_aer(struct pci_dev *dev, int aer_severit= y, int cper_severity_to_aer(int cper_severity); void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, int severity, struct aer_capability_regs *aer_regs); +void pci_aer_unmask_internal_errors(struct pci_dev *dev); #endif //_AER_H_ =20 --=20 2.34.1 From nobody Wed Oct 8 14:20:54 2025 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2053.outbound.protection.outlook.com [40.107.101.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4B452512DD; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 22:46:07.9746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbc80ebc-3319-4cf4-df90-08ddb5033da5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000148.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9779 Content-Type: text/plain; charset="utf-8" During CXL device cleanup the CXL PCIe Port device interrupts remain enabled. This potentially allows unnecessary interrupt processing on behalf of the CXL errors while the device is destroyed. Disable CXL protocol errors by setting the CXL devices' AER mask register. Introduce pci_aer_mask_internal_errors() similar to pci_aer_unmask_internal= _errors(). Introduce cxl_mask_proto_interrupts() to call pci_aer_mask_internal_errors(= ). Add calls to cxl_mask_proto_interrupts() within CXL Port teardown for CXL Root Ports, CXL Downstream Switch Ports, CXL Upstream Switch Ports, and CXL Endpoints. Follow the same "bottom-up" approach used during CXL Port teardown. Implement cxl_mask_proto_interrupts() in a header file to avoid introducing Kconfig ifdefs in cxl/core/port.c. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Joshua Hahn --- drivers/cxl/core/native_ras.c | 9 +++++++++ drivers/cxl/core/port.c | 6 ++++++ drivers/cxl/cxl.h | 3 +++ drivers/pci/pcie/cxl_aer.c | 21 +++++++++++++++++++++ include/linux/aer.h | 1 + 5 files changed, 40 insertions(+) diff --git a/drivers/cxl/core/native_ras.c b/drivers/cxl/core/native_ras.c index c7f9a237a1a2..8b8c7b3fba6c 100644 --- a/drivers/cxl/core/native_ras.c +++ b/drivers/cxl/core/native_ras.c @@ -9,6 +9,15 @@ #include #include =20 +void cxl_mask_proto_interrupts(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + guard(device)(dev); + + pci_aer_mask_internal_errors(pdev); +} + int match_uport(struct device *dev, const void *data) { const struct device *uport_dev =3D data; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index c76a1289e24e..786a036d33cc 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1433,6 +1433,9 @@ EXPORT_SYMBOL_NS_GPL(cxl_endpoint_autoremove, "CXL"); */ static void delete_switch_port(struct cxl_port *port) { + cxl_mask_proto_interrupts(port->uport_dev); + cxl_mask_proto_interrupts(port->parent_dport->dport_dev); + devm_release_action(port->dev.parent, cxl_unlink_parent_dport, port); devm_release_action(port->dev.parent, cxl_unlink_uport, port); devm_release_action(port->dev.parent, unregister_port, port); @@ -1446,6 +1449,7 @@ static void reap_dports(struct cxl_port *port) device_lock_assert(&port->dev); =20 xa_for_each(&port->dports, index, dport) { + cxl_mask_proto_interrupts(dport->dport_dev); devm_release_action(&port->dev, cxl_dport_unlink, dport); devm_release_action(&port->dev, cxl_dport_remove, dport); devm_kfree(&port->dev, dport); @@ -1476,6 +1480,8 @@ static void cxl_detach_ep(void *data) { struct cxl_memdev *cxlmd =3D data; =20 + cxl_mask_proto_interrupts(cxlmd->cxlds->dev); + for (int i =3D cxlmd->depth - 1; i >=3D 1; i--) { struct cxl_port *port, *parent_port; struct detach_ctx ctx =3D { diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 19eb33a7de6a..95843428be92 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -12,6 +12,7 @@ #include #include #include +#include =20 extern const struct nvdimm_security_ops *cxl_security_ops; =20 @@ -771,9 +772,11 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_po= rt *port, #ifdef CONFIG_PCIEAER_CXL void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); +void cxl_mask_proto_interrupts(struct device *dev); #else static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host) { } +static inline void cxl_mask_proto_interrupts(struct device *dev) { } #endif =20 struct cxl_decoder *to_cxl_decoder(struct device *dev); diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c index 3c5bf162607c..bd6660eab87b 100644 --- a/drivers/pci/pcie/cxl_aer.c +++ b/drivers/pci/pcie/cxl_aer.c @@ -33,6 +33,27 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev) } EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); =20 +/** + * pci_aer_mask_internal_errors - mask internal errors + * @dev: pointer to the pcie_dev data structure + * + * Masks internal errors in the Uncorrectable and Correctable Error + * Mask registers. + * + * Note: AER must be enabled and supported by the device which must be + * checked in advance, e.g. with pcie_aer_is_native(). + */ +void pci_aer_mask_internal_errors(struct pci_dev *dev) +{ + int aer =3D dev->aer_cap; + + pci_clear_and_set_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, + 0, PCI_ERR_UNC_INTN); + pci_clear_and_set_config_dword(dev, aer + PCI_ERR_COR_MASK, + 0, PCI_ERR_COR_INTERNAL); +} +EXPORT_SYMBOL_NS_GPL(pci_aer_mask_internal_errors, "CXL"); + static bool is_cxl_mem_dev(struct pci_dev *dev) { /* diff --git a/include/linux/aer.h b/include/linux/aer.h index 8fb1eca97c37..c0fd627328ae 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -114,5 +114,6 @@ int cper_severity_to_aer(int cper_severity); void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, int severity, struct aer_capability_regs *aer_regs); void pci_aer_unmask_internal_errors(struct pci_dev *dev); +void pci_aer_mask_internal_errors(struct pci_dev *dev); #endif //_AER_H_ =20 --=20 2.34.1