From nobody Wed Oct 8 14:59:03 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0BD012FCFE9; Thu, 26 Jun 2025 14:52:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750949541; cv=none; b=p7SHOCwyJnOttiUcoN2PYSgLqQwSZefSCS6U9PhGtwnJeE8NHxafCPyzYVAwB4ZePTZ1XzSyUPDwZTaLLUm43yillXXzrgX2v04vgBCfIVRaWAvyrpuJXhv1v2XSjyQ4+KbZEHIwXxySa8SIxFXRM08ftQh0V34/GYKE0xXX51Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750949541; c=relaxed/simple; bh=LZqwAXeX5pwX2ymubHEAsmigyGZ6ycVx7+nd6jGsxao=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UKMElnCiL0aVMqFz4AmzIqiXpW0FXJHzsbGnq70D8+VFfRKjY1PVzMqjcroRD6+wF/dT1I0DDL+zwim8J/AdxY5Tan1L0ubsUlAKs9eLtbMI0xx1LS2QhyQiB44H+JiOfVyYKHbZ8MeWi+O9wZAAgmsNvvwTZi/hkYWBZ8OHG/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=f5Xoz0ba; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="f5Xoz0ba" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=xR PvioOhBai0f8xbRz52cU/L0uoHP4BAGYYKam4r9fk=; b=f5Xoz0bare320ACP2Z VIm9mnaN4Ty11QQt26TtmSXKZmNH7AjCTsh3sbQcmU+tnmPqFPd7OwiKiqUT0s8i zaRqu4GIAm3O0934LmG2MYdKBoieTn6gfYvbNlWtB7YehjeG9wcxv6vDJ+1EGS6u ZHcvchSOwo0ujek5qnCw2Rzac= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-3 (Coremail) with SMTP id _____wDn7zyJXl1o5R7ZAg--.58392S4; Thu, 26 Jun 2025 22:51:55 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3] PCI: dwc: Refactor code by using dw_pcie_clear_and_set_dword() Date: Thu, 26 Jun 2025 22:50:29 +0800 Message-Id: <20250626145040.14180-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250626145040.14180-1-18255117159@163.com> References: <20250626145040.14180-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDn7zyJXl1o5R7ZAg--.58392S4 X-Coremail-Antispam: 1Uf129KBjvAXoWfJrW8GFy8Ary5uw47XFyDGFg_yoW8Ww48Wo Z3XF1UZa17tF10qFyUtas3KryUZrnFvFyFvFsFkr4j9ay3A3W5A393KFnxZw1Y9w4fC34r Xa1kG3Z8ArW7Xr1Un29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4R0JmUUUUUU X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxp4o2hdWY1vkgAEsC Content-Type: text/plain; charset="utf-8" DesignWare core modules contain multiple instances of manual read-modify-write operations for register bit manipulation. These patterns duplicate functionality now provided by dw_pcie_clear_and_set_dword(), particularly in debugfs, endpoint, host, and core initialization paths. Replace open-coded bit manipulation sequences with calls to dw_pcie_clear_and_set_dword(). Affected areas include debugfs register control, endpoint capability configuration, host setup routines, and core link initialization logic. The changes simplify power management handling, capability masking, and feature configuration. Standardizing on the helper function reduces code duplication by ~140 lines across core modules while improving readability. The refactoring also ensures consistent error handling for register operations and provides a single point of control for future bit manipulation logi updates. Signed-off-by: Hans Zhang <18255117159@163.com> --- .../controller/dwc/pcie-designware-debugfs.c | 67 +++++++---------- .../pci/controller/dwc/pcie-designware-ep.c | 20 +++-- .../pci/controller/dwc/pcie-designware-host.c | 27 +++---- drivers/pci/controller/dwc/pcie-designware.c | 74 +++++++------------ drivers/pci/controller/dwc/pcie-designware.h | 18 +---- 5 files changed, 76 insertions(+), 130 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers= /pci/controller/dwc/pcie-designware-debugfs.c index c67601096c48..c1ff6ade14b5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -213,10 +213,8 @@ static ssize_t lane_detect_write(struct file *file, co= nst char __user *buf, if (val) return val; =20 - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_R= EG); - val &=3D ~(LANE_SELECT); - val |=3D FIELD_PREP(LANE_SELECT, lane); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val= ); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE= _REG, + LANE_SELECT, FIELD_PREP(LANE_SELECT, lane)); =20 return count; } @@ -309,12 +307,11 @@ static void set_event_number(struct dwc_pcie_rasdes_p= riv *pdata, { u32 val; =20 - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); - val &=3D ~EVENT_COUNTER_ENABLE; - val &=3D ~(EVENT_COUNTER_GROUP_SELECT | EVENT_COUNTER_EVENT_SELECT); - val |=3D FIELD_PREP(EVENT_COUNTER_GROUP_SELECT, event_list[pdata->idx].gr= oup_no); + val =3D FIELD_PREP(EVENT_COUNTER_GROUP_SELECT, event_list[pdata->idx].gro= up_no); val |=3D FIELD_PREP(EVENT_COUNTER_EVENT_SELECT, event_list[pdata->idx].ev= ent_no); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_CO= UNTER_CTRL_REG, + EVENT_COUNTER_ENABLE | EVENT_COUNTER_GROUP_SELECT | + EVENT_COUNTER_EVENT_SELECT, val); } =20 static ssize_t counter_enable_read(struct file *file, char __user *buf, @@ -354,13 +351,9 @@ static ssize_t counter_enable_write(struct file *file,= const char __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); - if (enable) - val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON); - else - val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF); - - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, enable ? PER_EVENT_ON : PER_EVE= NT_OFF); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_CO= UNTER_CTRL_REG, + 0, val); =20 /* * While enabling the counter, always read the status back to check if @@ -415,10 +408,9 @@ static ssize_t counter_lane_write(struct file *file, c= onst char __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); - val &=3D ~(EVENT_COUNTER_LANE_SELECT); - val |=3D FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_CO= UNTER_CTRL_REG, + EVENT_COUNTER_LANE_SELECT, + FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane)); mutex_unlock(&rinfo->reg_event_lock); =20 return count; @@ -654,20 +646,15 @@ static int dw_pcie_ptm_check_capability(void *drvdata) static int dw_pcie_ptm_context_update_write(void *drvdata, u8 mode) { struct dw_pcie *pci =3D drvdata; - u32 val; =20 - if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_AUTO) { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val |=3D PTM_REQ_AUTO_UPDATE_ENABLED; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } else if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_MANUAL) { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val &=3D ~PTM_REQ_AUTO_UPDATE_ENABLED; - val |=3D PTM_REQ_START_UPDATE; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } else { + if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_AUTO) + dw_pcie_clear_and_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + 0, PTM_REQ_AUTO_UPDATE_ENABLED); + else if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_MANUAL) + dw_pcie_clear_and_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + PTM_REQ_AUTO_UPDATE_ENABLED, PTM_REQ_START_UPDATE); + else return -EINVAL; - } =20 return 0; } @@ -694,17 +681,13 @@ static int dw_pcie_ptm_context_update_read(void *drvd= ata, u8 *mode) static int dw_pcie_ptm_context_valid_write(void *drvdata, bool valid) { struct dw_pcie *pci =3D drvdata; - u32 val; =20 - if (valid) { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val |=3D PTM_RES_CCONTEXT_VALID; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } else { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val &=3D ~PTM_RES_CCONTEXT_VALID; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } + if (valid) + dw_pcie_clear_and_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + 0, PTM_RES_CCONTEXT_VALID); + else + dw_pcie_clear_and_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + PTM_RES_CCONTEXT_VALID, 0); =20 return 0; } diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 0ae54a94809b..7e52892f632b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -277,7 +277,7 @@ static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_= ep *ep, u8 func_no, int flags =3D epf_bar->flags; u32 reg =3D PCI_BASE_ADDRESS_0 + (4 * bar); unsigned int rebar_offset; - u32 rebar_cap, rebar_ctrl; + u32 rebar_cap; int ret; =20 rebar_offset =3D dw_pcie_ep_get_rebar_offset(pci, bar); @@ -310,9 +310,8 @@ static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_= ep *ep, u8 func_no, * 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes" * bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB. */ - rebar_ctrl =3D dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL); - rebar_ctrl &=3D ~GENMASK(31, 16); - dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl); + dw_pcie_clear_and_set_dword(pci, rebar_offset + PCI_REBAR_CTRL, + GENMASK(31, 16), 0); =20 /* * The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically @@ -925,7 +924,7 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) struct dw_pcie_ep_func *ep_func; struct device *dev =3D pci->dev; struct pci_epc *epc =3D ep->epc; - u32 ptm_cap_base, reg; + u32 ptm_cap_base; u8 hdr_type; u8 func_no; void *addr; @@ -1001,13 +1000,12 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) */ if (ptm_cap_base) { dw_pcie_dbi_ro_wr_en(pci); - reg =3D dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); - reg &=3D ~PCI_PTM_CAP_ROOT; - dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + dw_pcie_clear_and_set_dword(pci, ptm_cap_base + PCI_PTM_CAP, + PCI_PTM_CAP_ROOT, 0); =20 - reg =3D dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); - reg &=3D ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK); - dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + dw_pcie_clear_and_set_dword(pci, ptm_cap_base + PCI_PTM_CAP, + PCI_PTM_CAP_RES | + PCI_PTM_GRANULARITY_MASK, 0); dw_pcie_dbi_ro_wr_dis(pci); } =20 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 906277f9ffaf..e43d66d48439 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -909,7 +909,7 @@ static void dw_pcie_config_presets(struct dw_pcie_rp *p= p) int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - u32 val, ctrl, num_ctrls; + u32 ctrl, num_ctrls; int ret; =20 /* @@ -941,23 +941,17 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); =20 /* Setup interrupt pins */ - val =3D dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); - val &=3D 0xffff00ff; - val |=3D 0x00000100; - dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); + dw_pcie_clear_and_set_dword(pci, PCI_INTERRUPT_LINE, + 0x0000ff00, 0x00000100); =20 /* Setup bus numbers */ - val =3D dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); - val &=3D 0xff000000; - val |=3D 0x00ff0100; - dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); + dw_pcie_clear_and_set_dword(pci, PCI_PRIMARY_BUS, + 0x00ffffff, 0x00ff0100); =20 /* Setup command register */ - val =3D dw_pcie_readl_dbi(pci, PCI_COMMAND); - val &=3D 0xffff0000; - val |=3D PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_clear_and_set_dword(pci, PCI_COMMAND, 0x0000ffff, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SERR); =20 dw_pcie_config_presets(pp); /* @@ -976,9 +970,8 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) /* Program correct class for RC */ dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + 0, PORT_LOGIC_SPEED_CHANGE); =20 dw_pcie_dbi_ro_wr_dis(pci); =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 4d794964fa0f..d424e5e55c9f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -740,11 +740,8 @@ EXPORT_SYMBOL_GPL(dw_pcie_link_up); =20 void dw_pcie_upconfig_setup(struct dw_pcie *pci) { - u32 val; - - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); - val |=3D PORT_MLTI_UPCFG_SUPPORT; - dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_MULTI_LANE_CTRL, + 0, PORT_MLTI_UPCFG_SUPPORT); } EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); =20 @@ -805,21 +802,12 @@ int dw_pcie_link_get_max_link_width(struct dw_pcie *p= ci) =20 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { - u32 lnkcap, lwsc, plc; + u32 plc =3D 0; u8 cap; =20 if (!num_lanes) return; =20 - /* Set the number of lanes */ - plc =3D dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); - plc &=3D ~PORT_LINK_FAST_LINK_MODE; - plc &=3D ~PORT_LINK_MODE_MASK; - - /* Set link width speed control register */ - lwsc =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - lwsc &=3D ~PORT_LOGIC_LINK_WIDTH_MASK; - lwsc |=3D PORT_LOGIC_LINK_WIDTH_1_LANES; switch (num_lanes) { case 1: plc |=3D PORT_LINK_MODE_1_LANES; @@ -837,14 +825,19 @@ static void dw_pcie_link_set_max_link_width(struct dw= _pcie *pci, u32 num_lanes) dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); return; } - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); + /* Set the number of lanes */ + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_LINK_CONTROL, + PORT_LINK_FAST_LINK_MODE | PORT_LINK_MODE_MASK, + plc); + /* Set link width speed control register */ + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_LINK_WIDTH_MASK, + PORT_LOGIC_LINK_WIDTH_1_LANES); =20 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); - lnkcap &=3D ~PCI_EXP_LNKCAP_MLW; - lnkcap |=3D FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes); - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_clear_and_set_dword(pci, cap + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_MLW, + FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes)); } =20 void dw_pcie_iatu_detect(struct dw_pcie *pci) @@ -1133,38 +1126,27 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) =20 void dw_pcie_setup(struct dw_pcie *pci) { - u32 val; - dw_pcie_link_set_max_speed(pci); =20 /* Configure Gen1 N_FTS */ - if (pci->n_fts[0]) { - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); - val &=3D ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); - val |=3D PORT_AFR_N_FTS(pci->n_fts[0]); - val |=3D PORT_AFR_CC_N_FTS(pci->n_fts[0]); - dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); - } + if (pci->n_fts[0]) + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_AFR, + PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK, + PORT_AFR_N_FTS(pci->n_fts[0]) | + PORT_AFR_CC_N_FTS(pci->n_fts[0])); =20 /* Configure Gen2+ N_FTS */ - if (pci->n_fts[1]) { - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val &=3D ~PORT_LOGIC_N_FTS_MASK; - val |=3D pci->n_fts[1]; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); - } + if (pci->n_fts[1]) + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_N_FTS_MASK, pci->n_fts[1]); =20 - if (dw_pcie_cap_is(pci, CDM_CHECK)) { - val =3D dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); - val |=3D PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | - PCIE_PL_CHK_REG_CHK_REG_START; - dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); - } + if (dw_pcie_cap_is(pci, CDM_CHECK)) + dw_pcie_clear_and_set_dword(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, 0, + PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | + PCIE_PL_CHK_REG_CHK_REG_START); =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); - val &=3D ~PORT_LINK_FAST_LINK_MODE; - val |=3D PORT_LINK_DLL_LINK_EN; - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_LINK_CONTROL, + PORT_LINK_FAST_LINK_MODE, PORT_LINK_DLL_LINK_EN); =20 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index f401c144df0f..5a0aa154eb2a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -720,24 +720,14 @@ static inline void dw_pcie_clear_and_set_dword(struct= dw_pcie *pci, int pos, =20 static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) { - u32 reg; - u32 val; - - reg =3D PCIE_MISC_CONTROL_1_OFF; - val =3D dw_pcie_readl_dbi(pci, reg); - val |=3D PCIE_DBI_RO_WR_EN; - dw_pcie_writel_dbi(pci, reg, val); + dw_pcie_clear_and_set_dword(pci, PCIE_MISC_CONTROL_1_OFF, + 0, PCIE_DBI_RO_WR_EN); } =20 static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) { - u32 reg; - u32 val; - - reg =3D PCIE_MISC_CONTROL_1_OFF; - val =3D dw_pcie_readl_dbi(pci, reg); - val &=3D ~PCIE_DBI_RO_WR_EN; - dw_pcie_writel_dbi(pci, reg, val); + dw_pcie_clear_and_set_dword(pci, PCIE_MISC_CONTROL_1_OFF, + PCIE_DBI_RO_WR_EN, 0); } =20 static inline int dw_pcie_start_link(struct dw_pcie *pci) --=20 2.25.1