From nobody Sun Apr 12 21:07:55 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0D8662FEE34; Thu, 26 Jun 2025 14:52:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750949556; cv=none; b=d7IkV71C4BqSqSPbsKxl1RaJJCZFBME5YzfGVOPHaU5HtfJojwjqGzAMtl5mB0Zb9J9W858DgpP9XveON4k7sf4Agsahafz3SZYPmWA720kFbYkHgLnFJtVefDW1JIHm/TooinkKIgp+HwSXBvU4S67W+OWfvp0z6wdnoiH3cCQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750949556; c=relaxed/simple; bh=DbWS9EPNUTFD2ujiqp9vbg4OXcvl1Iw2h8FcJXbpvLI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZnnAZ4dUFKlAyRvs0UvAFxsuuLz/4leD43HEwTmR+CfozqRMhRcAf03oG0JIuEFDmw8pOI3NJdzNbTC5CXn6Zg0TdqRprF3ZpzzXiLJW/PlUyaPhcHjiJY/8UWvaD5vypGc5UpEucp3HB08C0Hp9q0rYmefq3OZnPQoZi3Jh2C0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=jm4TOWRG; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="jm4TOWRG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=dK LIp4fePJ8s1y9nOxgJeW+HJ+VqLROoQ8acB/1uzFQ=; b=jm4TOWRGsrwbvQzuQb aWUacqkSPvMltYJNr39QmbOM9kXUTWDYm6M6jtGnxUERE/a6v9c5HLcwY0VSWcr1 nZcboqvGQS5tWjEK0cMd9oDbDqrx8cJICkSpKh6aqyHhUCUgP4fdJAaxqT1RDqo4 jCn4BrG58zvd26XEwUoQoxIOA= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgCnboqkXl1oRfOTAA--.15779S5; Thu, 26 Jun 2025 22:52:22 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 13/13] PCI: tegra194: Refactor code by using dw_pcie_clear_and_set_dword() Date: Thu, 26 Jun 2025 22:50:40 +0800 Message-Id: <20250626145040.14180-14-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250626145040.14180-1-18255117159@163.com> References: <20250626145040.14180-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgCnboqkXl1oRfOTAA--.15779S5 X-Coremail-Antispam: 1Uf129KBjvAXoW3ur47Xw15Gr1xXry3AFy5urg_yoW8JFy8Go ZrJ3Wvg3W7Jr1kta4YkFn3Kry7Jw4YvayrArZ2y3yj9as7KF15A393Kas8Aw12kr4fC34f Xw4kG3W3AFW7XryUn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4RWc_fUUUUU X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxR4o2hdWY1zdQABsy Content-Type: text/plain; charset="utf-8" Tegra194 PCIe driver contains extensive manual bit manipulation across interrupt handling, ASPM configuration, and controller initialization. The driver implements complex read-modify-write sequences with explicit bit masking, leading to verbose and hard-to-maintain code. Refactor interrupt handling, ASPM setup, capability configuration, and controller initialization using dw_pcie_clear_and_set_dword(). Replace multi-step register modifications with single helper calls, eliminating intermediate variables and reducing code size by ~100 lines. For CDMA error handling, initialize the value variable to zero before setting status bits. This comprehensive refactoring significantly improves code readability and maintainability. Standardizing on the helper ensures consistent register access patterns across all driver components and reduces the risk of bit manipulation errors in this complex controller driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-tegra194.c | 157 +++++++++------------ 1 file changed, 64 insertions(+), 93 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 4f26086f25da..b258add67038 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -378,9 +378,8 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, v= oid *arg) val |=3D APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; appl_writel(pcie, val, APPL_CAR_RESET_OVRD); =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + 0, PORT_LOGIC_SPEED_CHANGE); } } =20 @@ -412,7 +411,7 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, v= oid *arg) =20 if (status_l0 & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) { status_l1 =3D appl_readl(pcie, APPL_INTR_STATUS_L1_18); - val =3D dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); + val =3D 0; if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) { dev_info(pci->dev, "CDM check complete\n"); val |=3D PCIE_PL_CHK_REG_CHK_REG_COMPLETE; @@ -425,7 +424,8 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, v= oid *arg) dev_err(pci->dev, "CDM Logic error\n"); val |=3D PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR; } - dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, + 0, val); val =3D dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR); dev_err(pci->dev, "CDM Error Address Offset =3D 0x%08X\n", val); } @@ -610,34 +610,27 @@ static struct pci_ops tegra_pci_ops =3D { #if defined(CONFIG_PCIEASPM) static void disable_aspm_l11(struct tegra_pcie_dw *pcie) { - u32 val; - - val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); - val &=3D ~PCI_L1SS_CAP_ASPM_L1_1; - dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); + dw_pcie_clear_and_set_dword(&pcie->pci, pcie->cfg_link_cap_l1sub, + PCI_L1SS_CAP_ASPM_L1_1, 0); } =20 static void disable_aspm_l12(struct tegra_pcie_dw *pcie) { - u32 val; - - val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); - val &=3D ~PCI_L1SS_CAP_ASPM_L1_2; - dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); + dw_pcie_clear_and_set_dword(&pcie->pci, pcie->cfg_link_cap_l1sub, + PCI_L1SS_CAP_ASPM_L1_2, 0); } =20 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) { u32 val; =20 - val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + - PCIE_RAS_DES_EVENT_COUNTER_CONTROL); - val &=3D ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT); - val |=3D EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; + val =3D EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; val |=3D event << EVENT_COUNTER_EVENT_SEL_SHIFT; val |=3D EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; - dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + - PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); + dw_pcie_clear_and_set_dword(&pcie->pci, pcie->ras_des_cap + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, + EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT, + val); val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + PCIE_RAS_DES_EVENT_COUNTER_DATA); =20 @@ -697,18 +690,18 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); =20 /* Program T_cmrt and T_pwr_on values */ - val =3D dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); - val &=3D ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE); - val |=3D (pcie->aspm_cmrt << 8); + val =3D (pcie->aspm_cmrt << 8); val |=3D (pcie->aspm_pwr_on_t << 19); - dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); + dw_pcie_clear_and_set_dword(pci, pcie->cfg_link_cap_l1sub, + PCI_L1SS_CAP_CM_RESTORE_TIME | + PCI_L1SS_CAP_P_PWR_ON_VALUE, + val); =20 /* Program L0s and L1 entrance latencies */ - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); - val &=3D ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; - val |=3D (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); + val =3D (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); val |=3D PORT_AFR_ENTER_ASPM; - dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_AFR, + PORT_AFR_L0S_ENTRANCE_LAT_MASK, val); } =20 static void init_debugfs(struct tegra_pcie_dw *pcie) @@ -860,31 +853,26 @@ static void config_gen3_gen4_eq_presets(struct tegra_= pcie_dw *pcie) dw_pcie_writeb_dbi(pci, offset + i, val); } =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 0); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); - val &=3D ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC; - val |=3D FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, 0x3ff); - val &=3D ~GEN3_EQ_CONTROL_OFF_FB_MODE; - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_EQ_CONTROL_OFF, + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC | + GEN3_EQ_CONTROL_OFF_FB_MODE, + FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, 0x3ff)); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - val |=3D (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, + 0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); - val &=3D ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC; - val |=3D FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, - pcie->of_data->gen4_preset_vec); - val &=3D ~GEN3_EQ_CONTROL_OFF_FB_MODE; - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_EQ_CONTROL_OFF, + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC | + GEN3_EQ_CONTROL_OFF_FB_MODE, + FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, + pcie->of_data->gen4_preset_vec)); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 0); } =20 static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) @@ -892,7 +880,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *p= p) struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); u32 val; - u16 val_16; =20 pp->bridge->ops =3D &tegra_pci_ops; =20 @@ -900,32 +887,25 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp = *pp) pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); =20 - val =3D dw_pcie_readl_dbi(pci, PCI_IO_BASE); - val &=3D ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); - dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); + dw_pcie_clear_and_set_dword(pci, PCI_IO_BASE, + IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8, 0); =20 - val =3D dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE); - val |=3D CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE; - val |=3D CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE; - dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val); + dw_pcie_clear_and_set_dword(pci, PCI_PREF_MEMORY_BASE, 0, + CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE | + CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE); =20 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); =20 /* Enable as 0xFFFF0001 response for RRS */ - val =3D dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); - val &=3D ~(AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT); - val |=3D (AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 << - AMBA_ERROR_RESPONSE_RRS_SHIFT); - dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); + dw_pcie_clear_and_set_dword(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, + AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT, + AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 << + AMBA_ERROR_RESPONSE_RRS_SHIFT); =20 /* Clear Slot Clock Configuration bit if SRNS configuration */ - if (pcie->enable_srns) { - val_16 =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + - PCI_EXP_LNKSTA); - val_16 &=3D ~PCI_EXP_LNKSTA_SLC; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, - val_16); - } + if (pcie->enable_srns) + dw_pcie_clear_and_set_dword(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, + PCI_EXP_LNKSTA_SLC, 0); =20 config_gen3_gen4_eq_presets(pcie); =20 @@ -937,17 +917,13 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp = *pp) disable_aspm_l12(pcie); } =20 - if (!pcie->of_data->has_l1ss_exit_fix) { - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - } + if (!pcie->of_data->has_l1ss_exit_fix) + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); =20 - if (pcie->update_fc_fixup) { - val =3D dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); - val |=3D 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; - dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); - } + if (pcie->update_fc_fixup) + dw_pcie_clear_and_set_dword(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, + 0, 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT); =20 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); =20 @@ -1018,9 +994,8 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pc= i) reset_control_deassert(pcie->core_rst); =20 offset =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); - val =3D dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); - val &=3D ~PCI_DLF_EXCHANGE_ENABLE; - dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_DLF_CAP, + PCI_DLF_EXCHANGE_ENABLE, 0); =20 tegra_pcie_dw_host_init(pp); dw_pcie_setup_rc(pp); @@ -1847,11 +1822,9 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) =20 reset_control_deassert(pcie->core_rst); =20 - if (pcie->update_fc_fixup) { - val =3D dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); - val |=3D 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; - dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); - } + if (pcie->update_fc_fixup) + dw_pcie_clear_and_set_dword(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, + 0, 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT); =20 config_gen3_gen4_eq_presets(pcie); =20 @@ -1863,11 +1836,9 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) disable_aspm_l12(pcie); } =20 - if (!pcie->of_data->has_l1ss_exit_fix) { - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - } + if (!pcie->of_data->has_l1ss_exit_fix) + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); =20 pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); --=20 2.25.1