From nobody Wed Oct 8 15:58:30 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A64325BF02; Thu, 26 Jun 2025 08:11:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925495; cv=none; b=olXEnGKBiOYt2i6cNQOTFxm6bhw8GoYyvPUMojP4pS/+CAtfRBQKTnSsJUrdTHMhjV46/B0J5yjlxZca8mC2ZUb+v8VXai5KxU9CSwamig4tubYJy26wHOFsjA8OFQoEYNiT9SSGpoF6umhi0/FxWIvfkWS56mvIla5AiTpJVps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925495; c=relaxed/simple; bh=68iU4rFxQXzhPtCcQD9kNnXutQRyeZXsCzXowxuXzSc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j8jUskWr/FhKvbs57FYZgRdHlmuo3u4OteaEH4nvGU/QaZaWzI5xCAZnNUzpXD5N38S5/tzdgBUs/093JV4g/CxFbbz6OsY+d+lRZVCDN88laAt7BuRIzJUEXxjQwri5ubc+1rWp1LuYEIH3b586KGj4HhZIrN3kfBtASVjidk4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id A17721F0004F; Thu, 26 Jun 2025 08:11:31 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 15893AC7F82; Thu, 26 Jun 2025 08:11:30 +0000 (UTC) X-Spam-Level: ** Received: from localhost.localdomain (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id 0002BAC7F79; Thu, 26 Jun 2025 08:09:39 +0000 (UTC) From: Paul Kocialkowski To: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij , Andre Przywara , Paul Kocialkowski Subject: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name Date: Thu, 26 Jun 2025 10:09:19 +0200 Message-ID: <20250626080923.632789-2-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250626080923.632789-1-paulk@sys-base.io> References: <20250626080923.632789-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A100/A133 only has a single emac instance, which is referred to as "emac" everywhere. Fix the pin names to drop the trailing "0" that has no reason to be. Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pi= n controller") Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai --- drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/= sunxi/pinctrl-sun50i-a100.c index b97de80ae2f3..95b764ee1c0d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */ + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */ + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */ + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ SUNXI_FUNCTION(0x3, "cir0"), /* OUT */ - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */ + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart3"), /* TX */ SUNXI_FUNCTION(0x3, "spi1"), /* CS */ - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */ + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "uart3"), /* RX */ SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ SUNXI_FUNCTION(0x4, "ledc"), - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */ + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */ + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ SUNXI_FUNCTION(0x4, "spdif"), /* OUT */ - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */ + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */ SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */ - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */ + SUNXI_FUNCTION(0x5, "emac"), /* MDC */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */ SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */ - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */ + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */ SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */ - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */ + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */ - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */ + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */ - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */ + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */ SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */ - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */ + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */ SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */ - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */ + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] =3D { SUNXI_FUNCTION(0x2, "cir0"), /* OUT */ SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */ SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */ - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */ + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), SUNXI_FUNCTION(0x0, "gpio_in"), --=20 2.49.0 From nobody Wed Oct 8 15:58:30 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6EB525C70D; Thu, 26 Jun 2025 08:12:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925561; cv=none; b=KrGgTLKlx2ynKB7qfbt0VBsOpqDtVy7ClXK+W+bdjUhf7WNbftdhKLCLVuq4wTmt2rVgyw6d2R36btvF3fjQnP7Lw0MECAo87fByGyYaxpToVXqQfF9Z/pXGUTa+7WvebNIdQ3Y9X40mmUt0nA2KTIY602vgFO2kNG6HSzXnifs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925561; c=relaxed/simple; bh=VFiodgVBU+frCM31/xTGFTIbf1DYWZz32/4rKCb6CNM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J4Fz3EacIBFKTxTyiz1rdnYAjDhepsw5ZRf73q6Lm3TcbwOE6hEoy6JySeSeGG62mHwVMgrYFMzUIjToVS/ssAvZA223IBtjUtldgum2xZdi6WogpFeAl9HU3XJr5wkEk05VNA/a5GDdCeTsaZeE4rIfcGJhFBpXIVG7I1tNNjY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id C37B21F0004B; Thu, 26 Jun 2025 08:12:37 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 2B22DAC7F8A; Thu, 26 Jun 2025 08:12:37 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id 89D1EAC7F7A; Thu, 26 Jun 2025 08:09:40 +0000 (UTC) From: Paul Kocialkowski To: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij , Andre Przywara , Paul Kocialkowski Subject: [PATCH 2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII Date: Thu, 26 Jun 2025 10:09:20 +0200 Message-ID: <20250626080923.632789-3-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250626080923.632789-1-paulk@sys-base.io> References: <20250626080923.632789-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A100/A133 supports both RGMII and RMII for its Ethernet MAC (EMAC) controller. Add corresponding pin definitions. Signed-off-by: Paul Kocialkowski Reviewed-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-a100.dtsi index bd366389b238..1c4e71b32911 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -236,6 +236,21 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; =20 + rgmii_pins: rgmii-pins { + pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH9", "PH10", + "PH14", "PH15", "PH16", "PH17", "PH18"; + function =3D "emac"; + drive-strength =3D <40>; + }; + + rmii_pins: rmii-pins { + pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH9", "PH10"; + function =3D "emac"; + drive-strength =3D <40>; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; function =3D "uart0"; --=20 2.49.0 From nobody Wed Oct 8 15:58:30 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CE2F25FA03; Thu, 26 Jun 2025 08:13:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925617; cv=none; b=PAfXndeA+I5R7bfFbuBcvgNtYr7r3MJZZQXRipFhHtucX+BJNwx2UWLQQlk3N9m85YMoO4efeGu5mYLPgeV4NjiV57AsDQ4wGpajRovaPkDYS0kLz96eyTowTcwHujtIDql4iFsRehQNXxuHFiHsfFVOTO2msJxplIerKy2oeSg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925617; c=relaxed/simple; bh=9R+INZ8e/SyHHgxDz0lyFa2OoSq9ExLuFg+fW4krK0I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q1ZibP1bkdq0bzFn7AtSq+cRJ0tosIU4a09aKA/laf71G5lNn+3aWovXI8Hu2QgzZ27YZBC9fEH0dQqLLKVyZCo6msZBmjC6KE8v55h6RAYhiMvKzPk6EFgyepDAo++f15VES1+ySErEyjpsvwxmkZolmzYULCvwcLqqbDlXLSM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id C7EA11F0004B; Thu, 26 Jun 2025 08:13:32 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 31515AC7F89; Thu, 26 Jun 2025 08:13:32 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id 3ACB4AC7F7B; Thu, 26 Jun 2025 08:09:41 +0000 (UTC) From: Paul Kocialkowski To: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij , Andre Przywara , Paul Kocialkowski Subject: [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible Date: Thu, 26 Jun 2025 10:09:21 +0200 Message-ID: <20250626080923.632789-4-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250626080923.632789-1-paulk@sys-base.io> References: <20250626080923.632789-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A100/A133 has an Ethernet MAC (EMAC) controller that is compatible with the A64 one. It features the same syscon registers for control of the top-level integration of the unit. Signed-off-by: Paul Kocialkowski Acked-by: Rob Herring (Arm) Reviewed-by: Andre Przywara --- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 7b6a2fde8175..0ae415f1e69c 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -21,6 +21,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-emac + - allwinner,sun50i-a100-emac - allwinner,sun50i-h6-emac - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-emac0 --=20 2.49.0 From nobody Wed Oct 8 15:58:30 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13526256C73; Thu, 26 Jun 2025 08:14:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925671; cv=none; b=M9B7wZaQw4dSUgcZuJTD/aSq2I/WMkkB9/iz1wgdHrWgEcbOAmbV9tNpIVmynb5FYBkF3atHL0srUTe74qr3VraGF1pYOU0j52vaWS8gwp+waFPJPBTGjuuQ7vwfbDhVfb6HB0K3+Mg6iZABCciZW/2Wygl8ODxN8nRTs2oW0H4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925671; c=relaxed/simple; bh=bKBKj/g6dLdmBtJ1nKja2cElFDqCQJuZbjQv2dPcf0k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d+e/AqS8YKpvX8moWUlm3Qr3pJf++yRkmWCN/WQH4a2yyj46wJ9+1XrLDdyZ8sAUMzfaBgS7asGfR9k3VK8AJKEV5VPqPMWDj0QHyfVw6knG7bgUwxJMVPyYkzMJKRDKJ85vMP2bldkPTX/Wh8Uba5s89CzOnhf2n4kEOc7IFz4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 02B2E1F0004B; Thu, 26 Jun 2025 08:14:27 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 6B57DAC7F8A; Thu, 26 Jun 2025 08:14:27 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id B8B27AC7F74; Thu, 26 Jun 2025 08:09:41 +0000 (UTC) From: Paul Kocialkowski To: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij , Andre Przywara , Paul Kocialkowski Subject: [PATCH 4/5] arm64: dts: allwinner: a100: Add EMAC support Date: Thu, 26 Jun 2025 10:09:22 +0200 Message-ID: <20250626080923.632789-5-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250626080923.632789-1-paulk@sys-base.io> References: <20250626080923.632789-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A100/A133 Ethernet MAC (EMAC) is compatible with the A64 one and needs access to the syscon register for control of the top-level integration of the unit. Signed-off-by: Paul Kocialkowski Reviewed-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-a100.dtsi index 1c4e71b32911..205faa90d37b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -420,6 +420,26 @@ i2c3: i2c@5002c00 { #size-cells =3D <0>; }; =20 + emac: ethernet@5020000 { + compatible =3D "allwinner,sun50i-a100-emac", + "allwinner,sun50i-a64-emac"; + reg =3D <0x5020000 0x10000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&ccu CLK_BUS_EMAC>; + clock-names =3D "stmmaceth"; + resets =3D <&ccu RST_BUS_EMAC>; + reset-names =3D "stmmaceth"; + syscon =3D <&syscon>; + status =3D "disabled"; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + ths: thermal-sensor@5070400 { compatible =3D "allwinner,sun50i-a100-ths"; reg =3D <0x05070400 0x100>; --=20 2.49.0 From nobody Wed Oct 8 15:58:30 2025 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35EB425D1F1; Thu, 26 Jun 2025 08:15:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925727; cv=none; b=oyC9fkCpidF4C1omKUbZyhaav0yTHGD1C43o5P1gvUfFbhovNLVLvVF/BCqGtQq9LQZ/RNAgdQ49aZblE6heye5thq0UTKBRwyNNBEVIr+Dk2FxBIZsST+hxhp6Yt2lwqv+FlHS5xcAhzJGL1eKul1nk/Bx2TgHZsBdD4f3M8JE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750925727; c=relaxed/simple; bh=PEZYGH+OI3VJSlIhgXQphteONYdoErA4jc7oo1FClP8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ntr3aOC8/MC6d+bQ3dJY0Y6O89H76n7TkwmybZHCMpKL18VcnBZoCwaTpizp8Ho3U9+3piTadp3L2AGQvCVRBiCiglPvL3vUrOK6SZcYZfdfpZUlemOrje2s5teY2l9P88lkIPdQ8fbwkdIGK/HCRcCe2cQoVIf/LpbTNij9f20= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 5C6011F0004B; Thu, 26 Jun 2025 08:15:24 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id A5A52AC7F8D; Thu, 26 Jun 2025 08:15:23 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.65]) by laika.paulk.fr (Postfix) with ESMTP id 6F66CAC7F7C; Thu, 26 Jun 2025 08:09:42 +0000 (UTC) From: Paul Kocialkowski To: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Linus Walleij , Andre Przywara , Paul Kocialkowski Subject: [PATCH 5/5] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support Date: Thu, 26 Jun 2025 10:09:23 +0200 Message-ID: <20250626080923.632789-6-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250626080923.632789-1-paulk@sys-base.io> References: <20250626080923.632789-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Liontron H-A133L board features an Ethernet controller with a JLSemi JL1101 PHY. Its reset pin is tied to the PH12 GPIO. Note that the reset pin must be handled as a bus-wide reset GPIO in order to let the MDIO core properly reset it before trying to read its identification registers. There's no other device on the MDIO bus. The datasheet of the PHY mentions that the reset signal must be held for 1 ms to take effect. Make it 2 ms (and the same for post-delay) to be on the safe side without wasting too much time during boot. Signed-off-by: Paul Kocialkowski --- .../sun50i-a133-liontron-h-a133l.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts= b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts index fe77178d3e33..04dd7f781894 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts @@ -65,6 +65,25 @@ &ehci1 { status =3D "okay"; }; =20 +&emac { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rmii_pins>; + phy-handle =3D <&rmii_phy>; + phy-mode =3D "rmii"; + status =3D "okay"; +}; + +&mdio { + reset-gpios =3D <&pio 7 12 GPIO_ACTIVE_LOW>; /* PH12 */ + reset-delay-us =3D <2000>; + reset-post-delay-us =3D <2000>; + + rmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + }; +}; + &mmc0 { vmmc-supply =3D <®_dcdc1>; cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ --=20 2.49.0