From nobody Thu Sep 11 00:08:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45D9829A9C9; Thu, 26 Jun 2025 09:02:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928576; cv=none; b=s+4KQpYbfzjn853lTJJW8ipfYl5dNxPKr44tSBTorSr79ouxJkyipLuygBxw4R/IsdHYsgh7QlMEBnQp+jtR/XIJwFuYjlYH/qU/rZyDf6TkGYj5+V/DZHbqgGt5BxGPIov0Ig6HKUzUVMyDqtiIm3xF9LU6L7tc4fP7ZmBcE5c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928576; c=relaxed/simple; bh=tOusHgnylieMYc/yov/nZwdaPr8ceh64o6UxW7T0mZE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZUViqhBjcpIrnRJmmlgyPyEZZkjv3Lk+IKBV8lWG60zWN+CL34ADScNUrXC9LX/AGHVYTe81iUUydcRyv/2VDf+GZ0IC58eJX9xIHNJSZzP7GGGaCOXntZMUeCjwH3fRhK2NR9P0JaOVH77wYcARXA/D1IVbhg92SsbQp4OfKDc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jShox5ID; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jShox5ID" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E463DC4CEEB; Thu, 26 Jun 2025 09:02:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750928576; bh=tOusHgnylieMYc/yov/nZwdaPr8ceh64o6UxW7T0mZE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jShox5ID+NwmVM/a1R3YorHn9PU2kvJA0Aa2odlp8itgt4thENxW1BadCGlSsHKVp IdUXs94gShrNLTkbgekCjCS7iC8Od3RKzvz3Le7cGHSGpwrRJYMXgK5tqHigyHAvcY AFRSPisEwjKoC6SvoAOH1rlCWbhhXg4N4j+bfrpiXzJr19+2qhr5Raeh/nY/KVxSGR tEgX3OiCaiX0KeEWQcYJDDH23RH12VQ2hLeMO/46K7hCCqyBa+CHPg7x4YbPRxWWFS D0j+e/m4GL0sBfBq9lpc2k4Gsb2PeMxwLlHwczhFYP2cyAQ2GpYWyGdI1vNHkm5iO/ LnLMvKt7t2uLQ== From: Konrad Dybcio Date: Thu, 26 Jun 2025 11:02:30 +0200 Subject: [PATCH v6 03/14] drm/msm: Use the central UBWC config database Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250626-topic-ubwc_central-v6-3-c94fa9d12040@oss.qualcomm.com> References: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> In-Reply-To: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750928557; l=23309; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=EyuFC63nhfrTfyAx+DaEP/hnGb8Uk/R2ywuPhg1z74A=; b=RbJJvaNlYPzBTkQGivT4tT9+pKXSQTRu8t+idi7veG0LYUDItytgUESNqEH7lmKWAPtsih+Bb XlBnYcDdvLGBS4Hcpacmc48vP1eMttz8V/hb8jbg5nPUN7JeL5uwFNF X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio As discussed a lot in the past, the UBWC config must be coherent across a number of IP blocks (currently display and GPU, but it also may/will concern camera/video as the drivers evolve). So far, we've been trying to keep the values reasonable in each of the two drivers separately, but it really make sense to do so centrally, especially given certain fields (e.g. HBB) may need to be gathered dynamically. To reduce room for error, move to fetching the config from a central source, so that the data programmed into the hardware is consistent across all multimedia blocks that request it. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +- drivers/gpu/drm/msm/msm_mdss.c | 338 +++++-------------------= ---- drivers/gpu/drm/msm/msm_mdss.h | 29 --- include/linux/soc/qcom/ubwc.h | 2 +- 11 files changed, 74 insertions(+), 322 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 7f127e2ae44292f8f5c7ff6a9251c3d7ec8c9f58..aa317677b6a8960406635fda058= a6b7d76256a51 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -30,6 +30,7 @@ config DRM_MSM select SHMEM select TMPFS select QCOM_SCM + select QCOM_UBWC_CONFIG select WANT_DEV_COREDUMP select SND_SOC_HDMI_CODEC if SND_SOC select SYNC_FILE diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 7dfd0e0a779535e1f6b003f48188bc90d29d6853..6f1fc790ad6d815ed8a2c9936a4= 0d6e6a0b413a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -10,11 +10,11 @@ #include "dpu_hw_sspp.h" #include "dpu_kms.h" =20 -#include "msm_mdss.h" - #include #include =20 +#include + #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 =20 /* SSPP registers */ @@ -684,7 +684,7 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pi= pe, struct dpu_kms *kms, struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, const struct dpu_sspp_cfg *cfg, void __iomem *addr, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, const struct dpu_mdss_version *mdss_rev) { struct dpu_hw_sspp *hw_pipe; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index ed90e78d178a497ae7e2dc12b09a37c8a3f79621..bdac5c04bf7901b864d5999fb39= 5aa5c90de82f5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops { struct dpu_hw_sspp { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; - const struct msm_mdss_data *ubwc; + const struct qcom_ubwc_cfg_data *ubwc; =20 /* Pipe */ enum dpu_sspp idx; @@ -325,7 +325,7 @@ struct dpu_kms; struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, const struct dpu_sspp_cfg *cfg, void __iomem *addr, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, const struct dpu_mdss_version *mdss_rev); =20 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms = *kms, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index df9d6a509bcd453978bc2491795a6ef87cc95638..226da68d9a9b26f798b8e6795f2= 994e971b80505 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -20,9 +20,10 @@ #include #include =20 +#include + #include "msm_drv.h" #include "msm_mmu.h" -#include "msm_mdss.h" #include "msm_gem.h" #include "disp/msm_disp_snapshot.h" =20 @@ -1189,10 +1190,10 @@ static int dpu_kms_hw_init(struct msm_kms *kms) goto err_pm_put; } =20 - dpu_kms->mdss =3D msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent); + dpu_kms->mdss =3D qcom_ubwc_config_get_data(); if (IS_ERR(dpu_kms->mdss)) { rc =3D PTR_ERR(dpu_kms->mdss); - DPU_ERROR("failed to get MDSS data: %d\n", rc); + DPU_ERROR("failed to get UBWC config data: %d\n", rc); goto err_pm_put; } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.h index a57ec2ec106083e8f93578e4307e8b13ae549c08..993cf512f8c509ac4e28a60a1a3= 1b262f4a54f98 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -60,7 +60,7 @@ struct dpu_kms { struct msm_kms base; struct drm_device *dev; const struct dpu_mdss_cfg *catalog; - const struct msm_mdss_data *mdss; + const struct qcom_ubwc_cfg_data *mdss; =20 /* io/register spaces: */ void __iomem *mmio, *vbif[VBIF_MAX]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 421138bc3cb779c45fcfd5319056f0d31c862452..ba5a46c5c1b501d22c6b28dd82a= c761c26d08541 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -17,8 +17,9 @@ #include #include =20 +#include + #include "msm_drv.h" -#include "msm_mdss.h" #include "dpu_kms.h" #include "dpu_hw_sspp.h" #include "dpu_hw_util.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index a2219c4f55a45db894ff18c1fd0a810c1a3cf811..25382120cb1a4f2b68b0c657337= 1f75fb8d489ea 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -40,7 +40,7 @@ static inline bool reserved_by_other(uint32_t *res_map, i= nt idx, int dpu_rm_init(struct drm_device *dev, struct dpu_rm *rm, const struct dpu_mdss_cfg *cat, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, void __iomem *mmio) { int rc, i; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.h index aa62966056d489d9c94c61f24051a2f3e7b7ed89..ccd64404f12d3ca3956c8e6df7d= 1ffddd4f20642 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -69,7 +69,7 @@ struct msm_display_topology { int dpu_rm_init(struct drm_device *dev, struct dpu_rm *rm, const struct dpu_mdss_cfg *cat, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, void __iomem *mmio); =20 int dpu_rm_reserve(struct dpu_rm *rm, diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 597c8e64985316763d7ced763c4c6fdb5da9fb90..1f5fe7811e016909282087176a4= 2a2349b21c9c4 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -16,14 +16,17 @@ #include #include =20 -#include "msm_mdss.h" +#include + #include "msm_kms.h" =20 #include =20 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ =20 -#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */ +struct msm_mdss_data { + u32 reg_bus_bw; +}; =20 struct msm_mdss { struct device *dev; @@ -36,7 +39,8 @@ struct msm_mdss { unsigned long enabled_mask; struct irq_domain *domain; } irq_controller; - const struct msm_mdss_data *mdss_data; + const struct qcom_ubwc_cfg_data *mdss_data; + u32 reg_bus_bw; struct icc_path *mdp_path[2]; u32 num_mdp_paths; struct icc_path *reg_bus_path; @@ -165,7 +169,7 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *ms= m_mdss) =20 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 @@ -180,7 +184,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss = *msm_mdss) =20 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 @@ -198,7 +202,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss = *msm_mdss) =20 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 @@ -224,7 +228,7 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss = *msm_mdss) =20 static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); =20 @@ -240,69 +244,6 @@ static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss= *msm_mdss) writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); } =20 -#define MDSS_HW_MAJ_MIN \ - (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK) - -#define MDSS_HW_MSM8996 0x1007 -#define MDSS_HW_MSM8937 0x100e -#define MDSS_HW_MSM8953 0x1010 -#define MDSS_HW_MSM8998 0x3000 -#define MDSS_HW_SDM660 0x3002 -#define MDSS_HW_SDM630 0x3003 - -/* - * MDP5 platforms use generic qcom,mdp5 compat string, so we have to gener= ate this data - */ -static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct= msm_mdss *mdss) -{ - struct msm_mdss_data *data; - u32 hw_rev; - - data =3D devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL); - if (!data) - return NULL; - - hw_rev =3D readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION); - hw_rev =3D FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev); - - if (hw_rev =3D=3D MDSS_HW_MSM8996 || - hw_rev =3D=3D MDSS_HW_MSM8937 || - hw_rev =3D=3D MDSS_HW_MSM8953 || - hw_rev =3D=3D MDSS_HW_MSM8998 || - hw_rev =3D=3D MDSS_HW_SDM660 || - hw_rev =3D=3D MDSS_HW_SDM630) { - data->ubwc_dec_version =3D UBWC_1_0; - data->ubwc_enc_version =3D UBWC_1_0; - } - - if (hw_rev =3D=3D MDSS_HW_MSM8996 || - hw_rev =3D=3D MDSS_HW_MSM8998) - data->highest_bank_bit =3D 15; - else - data->highest_bank_bit =3D 14; - - return data; -} - -const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) -{ - struct msm_mdss *mdss; - - if (!dev) - return ERR_PTR(-EINVAL); - - mdss =3D dev_get_drvdata(dev); - - /* - * We could not do it at the probe time, since hw revision register was - * not readable. Fill data structure now for the MDP5 platforms. - */ - if (!mdss->mdss_data && mdss->is_mdp5) - mdss->mdss_data =3D msm_mdss_generate_mdp5_mdss_data(mdss); - - return mdss->mdss_data; -} - static int msm_mdss_enable(struct msm_mdss *msm_mdss) { int ret, i; @@ -315,12 +256,8 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) for (i =3D 0; i < msm_mdss->num_mdp_paths; i++) icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); =20 - if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw) - icc_set_bw(msm_mdss->reg_bus_path, 0, - msm_mdss->mdss_data->reg_bus_bw); - else - icc_set_bw(msm_mdss->reg_bus_path, 0, - DEFAULT_REG_BW); + icc_set_bw(msm_mdss->reg_bus_path, 0, + msm_mdss->reg_bus_bw); =20 ret =3D clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -459,6 +396,7 @@ static int mdp5_mdss_parse_clock(struct platform_device= *pdev, struct clk_bulk_d =20 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool i= s_mdp5) { + const struct msm_mdss_data *mdss_data; struct msm_mdss *msm_mdss; int ret; int irq; @@ -471,7 +409,15 @@ static struct msm_mdss *msm_mdss_init(struct platform_= device *pdev, bool is_mdp5 if (!msm_mdss) return ERR_PTR(-ENOMEM); =20 - msm_mdss->mdss_data =3D of_device_get_match_data(&pdev->dev); + msm_mdss->mdss_data =3D qcom_ubwc_config_get_data(); + if (IS_ERR(msm_mdss->mdss_data)) + return ERR_CAST(msm_mdss->mdss_data); + + mdss_data =3D of_device_get_match_data(&pdev->dev); + if (!mdss_data) + return ERR_PTR(-EINVAL); + + msm_mdss->reg_bus_bw =3D mdss_data->reg_bus_bw; =20 msm_mdss->mmio =3D devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? = "mdss_phys" : "mdss"); if (IS_ERR(msm_mdss->mmio)) @@ -590,217 +536,49 @@ static void mdss_remove(struct platform_device *pdev) msm_mdss_destroy(mdss); } =20 -static const struct msm_mdss_data msm8998_data =3D { - .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_1_0, - .highest_bank_bit =3D 15, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data qcm2290_data =3D { - /* no UBWC */ - .highest_bank_bit =3D 15, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sa8775p_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 4, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 13, - .macrotile_mode =3D true, - .reg_bus_bw =3D 74000, -}; - -static const struct msm_mdss_data sar2130p_data =3D { - .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ - .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 13, - .macrotile_mode =3D 1, - .reg_bus_bw =3D 74000, -}; - -static const struct msm_mdss_data sc7180_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sc7280_data =3D { - .ubwc_enc_version =3D UBWC_3_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 14, - .macrotile_mode =3D true, - .reg_bus_bw =3D 74000, -}; - -static const struct msm_mdss_data sc8180x_data =3D { - .ubwc_enc_version =3D UBWC_3_0, - .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sc8280xp_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sdm670_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sdm845_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 15, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm6350_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm7150_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm8150_data =3D { - .ubwc_enc_version =3D UBWC_3_0, - .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 15, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm6115_data =3D { - .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 7, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm6125_data =3D { - .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_3_0, - .ubwc_swizzle =3D 1, - .highest_bank_bit =3D 14, -}; - -static const struct msm_mdss_data sm6150_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm8250_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm8350_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 74000, -}; - -static const struct msm_mdss_data sm8550_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, +static const struct msm_mdss_data data_57k =3D { .reg_bus_bw =3D 57000, }; =20 -static const struct msm_mdss_data sm8750_data =3D { - .ubwc_enc_version =3D UBWC_5_0, - .ubwc_dec_version =3D UBWC_5_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 57000, +static const struct msm_mdss_data data_74k =3D { + .reg_bus_bw =3D 74000, }; =20 -static const struct msm_mdss_data x1e80100_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - /* TODO: Add reg_bus_bw with real value */ +static const struct msm_mdss_data data_76k8 =3D { + .reg_bus_bw =3D 76800, +}; + +static const struct msm_mdss_data data_153k6 =3D { + .reg_bus_bw =3D 153600, }; =20 static const struct of_device_id mdss_dt_match[] =3D { - { .compatible =3D "qcom,mdss" }, - { .compatible =3D "qcom,msm8998-mdss", .data =3D &msm8998_data }, - { .compatible =3D "qcom,qcm2290-mdss", .data =3D &qcm2290_data }, - { .compatible =3D "qcom,sa8775p-mdss", .data =3D &sa8775p_data }, - { .compatible =3D "qcom,sar2130p-mdss", .data =3D &sar2130p_data }, - { .compatible =3D "qcom,sdm670-mdss", .data =3D &sdm670_data }, - { .compatible =3D "qcom,sdm845-mdss", .data =3D &sdm845_data }, - { .compatible =3D "qcom,sc7180-mdss", .data =3D &sc7180_data }, - { .compatible =3D "qcom,sc7280-mdss", .data =3D &sc7280_data }, - { .compatible =3D "qcom,sc8180x-mdss", .data =3D &sc8180x_data }, - { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, - { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, - { .compatible =3D "qcom,sm6125-mdss", .data =3D &sm6125_data }, - { .compatible =3D "qcom,sm6150-mdss", .data =3D &sm6150_data }, - { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, - { .compatible =3D "qcom,sm6375-mdss", .data =3D &sm6350_data }, - { .compatible =3D "qcom,sm7150-mdss", .data =3D &sm7150_data }, - { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, - { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, - { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8350_data }, - { .compatible =3D "qcom,sm8450-mdss", .data =3D &sm8350_data }, - { .compatible =3D "qcom,sm8550-mdss", .data =3D &sm8550_data }, - { .compatible =3D "qcom,sm8650-mdss", .data =3D &sm8550_data}, - { .compatible =3D "qcom,sm8750-mdss", .data =3D &sm8750_data}, - { .compatible =3D "qcom,x1e80100-mdss", .data =3D &x1e80100_data}, + { .compatible =3D "qcom,mdss", .data =3D &data_153k6 }, + { .compatible =3D "qcom,msm8998-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,qcm2290-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sa8775p-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sar2130p-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sdm670-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sdm845-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sc7180-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sc7280-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sc8180x-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6115-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6125-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6150-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6350-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6375-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm7150-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm8150-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm8250-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm8350-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sm8450-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sm8550-mdss", .data =3D &data_57k }, + { .compatible =3D "qcom,sm8650-mdss", .data =3D &data_57k }, + { .compatible =3D "qcom,sm8750-mdss", .data =3D &data_57k }, + /* TODO: x1e8: Add reg_bus_bw with real value */ + { .compatible =3D "qcom,x1e80100-mdss", .data =3D &data_153k6 }, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h deleted file mode 100644 index dd0160c6ba1a297cea5b87cd8b03895b2aa08213..000000000000000000000000000= 0000000000000 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018, The Linux Foundation - */ - -#ifndef __MSM_MDSS_H__ -#define __MSM_MDSS_H__ - -struct msm_mdss_data { - u32 ubwc_enc_version; - /* can be read from register 0x58 */ - u32 ubwc_dec_version; - u32 ubwc_swizzle; - u32 highest_bank_bit; - bool ubwc_bank_spread; - bool macrotile_mode; - u32 reg_bus_bw; -}; - -#define UBWC_1_0 0x10000000 -#define UBWC_2_0 0x20000000 -#define UBWC_3_0 0x30000000 -#define UBWC_4_0 0x40000000 -#define UBWC_4_3 0x40030000 -#define UBWC_5_0 0x50000000 - -const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev); - -#endif /* __MSM_MDSS_H__ */ diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index b92fc402638bae85e4e9da2552be56ac9ea9b448..d65df559603d95e3db5bc04ce42= e00a0b4785828 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -53,7 +53,7 @@ struct qcom_ubwc_cfg_data { #define UBWC_4_3 0x40030000 #define UBWC_5_0 0x50000000 =20 -#ifdef CONFIG_QCOM_UBWC_CONFIG +#if IS_ENABLED(CONFIG_QCOM_UBWC_CONFIG) const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void); #else static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(v= oid) --=20 2.50.0