From nobody Thu Sep 11 00:08:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE91029A9C9; Thu, 26 Jun 2025 09:02:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928572; cv=none; b=WNKNVfBszzPxwCxF8drEDu5OcJ7CjevkSMHsojYUkiVemIsktVbZ/AsVZGVtHlIRnI5JEOaiHTbMgC24Mw3KRn1ZSKCG03edug7Sf6ZDJrPP26U8ds4LW5wJQJ0iqTSWDsAMaICQNor2P7FaCks9tgQ/RKIaGSt7ErTwZDwQhS4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928572; c=relaxed/simple; bh=bFXCEdgVhfDMEoqkGoje5SoT0Fo4NnjqAhltzIwdUUA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZZbp/ntqsPorjKY7g8i/3aOZmo4qzvHNRLtlk+iqoU9zkS7pX3tPjC9YHB2evNbb2s5MQQFy/QD9muMA2hYrG1DO+0bgPqZ60a+qM6tPnyx00LXYdwpjTDkJlCG3iEkKXBDOdOIlll+e62p5tj0NECVHp7+OMBKF0eKCi1njxdg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U0frcUA0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U0frcUA0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5691BC4CEEE; Thu, 26 Jun 2025 09:02:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750928571; bh=bFXCEdgVhfDMEoqkGoje5SoT0Fo4NnjqAhltzIwdUUA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=U0frcUA0/5J6PBaZsCVx8i3uKX9ky5+9EXFFIAPzElf5i84EuXx5faJazRD5E07D4 H5J0ED6dZqa0bvXvy6jN2cDPOb4OeDiUmwG9c8oHQfpFZ7XYHdLGGlTpykbzK5Sh3l K9QA3mxTVVgcGAuRRpw4i7u6vJHkotGqWelpBpkOISUOjdUiL6SV3jQhI/KgByBYo6 2tH/cfxyYQ3f3JFZM5EZOk8v/tzxpGxxJ3ue3/Oep33d3k2hKsckQtTbK139vl2dAH NmrDiWCZ5jCbNMkXIRd4c6qAG2X8U9mY2hSUbbxO/+sY8jl998CoTwWmZ7sb4iFMht cKil8EaAbENPw== From: Konrad Dybcio Date: Thu, 26 Jun 2025 11:02:29 +0200 Subject: [PATCH v6 02/14] drm/msm: Offset MDSS HBB value by 13 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250626-topic-ubwc_central-v6-2-c94fa9d12040@oss.qualcomm.com> References: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> In-Reply-To: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750928557; l=7622; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=T2FBWroU738HI/Pia2RKVHq+4tLpLcX1tOA/9NV0Bxg=; b=IbtpEYDza2VEUMsSSh32LeZsILALILvATY3Y3sZLr4Y3NCXHxAteFTL0+7p+eBc2Ss2QSI5vz zv05bQQE2fnDSuGWPGtMdDhtN3f71+NjoWFRECboMFk8uYMg+DfSl72 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The Adreno part of the driver exposes this value to userspace, and the SMEM data source also presents a x+13 value. Keep things coherent and make the value uniform across them. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 52 +++++++++++++++++++++-----------------= ---- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 422da5ebf802676afbfc5f242a5a84e6d488dda1..597c8e64985316763d7ced763c4= c6fdb5da9fb90 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -167,7 +167,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 if (data->ubwc_bank_spread) value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; @@ -182,7 +182,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 if (data->macrotile_mode) value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; @@ -200,7 +200,7 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 if (data->ubwc_bank_spread) value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; @@ -277,9 +277,9 @@ static const struct msm_mdss_data *msm_mdss_generate_md= p5_mdss_data(struct msm_m =20 if (hw_rev =3D=3D MDSS_HW_MSM8996 || hw_rev =3D=3D MDSS_HW_MSM8998) - data->highest_bank_bit =3D 2; + data->highest_bank_bit =3D 15; else - data->highest_bank_bit =3D 1; + data->highest_bank_bit =3D 14; =20 return data; } @@ -593,13 +593,13 @@ static void mdss_remove(struct platform_device *pdev) static const struct msm_mdss_data msm8998_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_1_0, - .highest_bank_bit =3D 2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data qcm2290_data =3D { /* no UBWC */ - .highest_bank_bit =3D 0x2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 @@ -608,7 +608,7 @@ static const struct msm_mdss_data sa8775p_data =3D { .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 4, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0, + .highest_bank_bit =3D 13, .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; @@ -618,7 +618,7 @@ static const struct msm_mdss_data sar2130p_data =3D { .ubwc_dec_version =3D UBWC_4_3, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0, + .highest_bank_bit =3D 13, .macrotile_mode =3D 1, .reg_bus_bw =3D 74000, }; @@ -628,7 +628,7 @@ static const struct msm_mdss_data sc7180_data =3D { .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0x1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 @@ -637,7 +637,7 @@ static const struct msm_mdss_data sc7280_data =3D { .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; @@ -645,7 +645,7 @@ static const struct msm_mdss_data sc7280_data =3D { static const struct msm_mdss_data sc8180x_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; @@ -655,7 +655,7 @@ static const struct msm_mdss_data sc8280xp_data =3D { .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; @@ -663,14 +663,14 @@ static const struct msm_mdss_data sc8280xp_data =3D { static const struct msm_mdss_data sdm670_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data sdm845_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 @@ -679,21 +679,21 @@ static const struct msm_mdss_data sm6350_data =3D { .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data sm7150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data sm8150_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 @@ -702,7 +702,7 @@ static const struct msm_mdss_data sm6115_data =3D { .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 7, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0x1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 @@ -710,13 +710,13 @@ static const struct msm_mdss_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_3_0, .ubwc_swizzle =3D 1, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, }; =20 static const struct msm_mdss_data sm6150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 @@ -726,7 +726,7 @@ static const struct msm_mdss_data sm8250_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; @@ -737,7 +737,7 @@ static const struct msm_mdss_data sm8350_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; @@ -748,7 +748,7 @@ static const struct msm_mdss_data sm8550_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 57000, }; @@ -759,7 +759,7 @@ static const struct msm_mdss_data sm8750_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 57000, }; @@ -770,7 +770,7 @@ static const struct msm_mdss_data x1e80100_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, /* TODO: Add reg_bus_bw with real value */ }; --=20 2.50.0