From nobody Thu Sep 11 00:04:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F2CD29E11B; Thu, 26 Jun 2025 09:03:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928618; cv=none; b=KRRzPryh/c5qI8UmJSIsjmolnHwD9VOrDBDM2dRz0QlQH4hCNS64bULWTWakABVhskQhMk665EjyjybFTLvHGv7TisWUnqtZohQS2vzD2nljqoVwb9uZZuWYT4jeM93mrBx8Rlrjc8NyYDag6THZ7vbYp0pNYuj+TxC8qdPWg+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928618; c=relaxed/simple; bh=/kqGi4h9v1Hn5tcxd1FmuI1H0vQ4QcnDYZ1YUUqI9As=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G5xNpcT2QhadSM/KW8q7atFTHWDxhUguP8sTp012DVCJLIFZg2IlsMJ327p5iS1/lXIWFIO+SIheltta+70G30Erbffe1nKc1eiSFxZIXRcCKtA6kA/NjFkRfke0WwnpIGDoj6xtveSUmGsQI7sUS5d40Xg+4Dk1WebqVSflvp0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GeBvBSc2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GeBvBSc2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 193A6C4CEEB; Thu, 26 Jun 2025 09:03:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750928617; bh=/kqGi4h9v1Hn5tcxd1FmuI1H0vQ4QcnDYZ1YUUqI9As=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GeBvBSc2VU9gXJqh2dWopwSB4Pg1c7CkTqa4/j9XxmTO0ytIYerNihHVvghYIssVY 3v70kl505KyTQpr6tt+3ehJDjTaoeH9AyMRUCqdBheVC8ZrBI811Zqj4QokQk2yv7Z K299CM+fTwWI10oSKYgdvEc5/pU1Y8hwSDBV3trmDi+Ue+q7HlaKiUMQLGDA52lPyj KPzuwNWi6+zdZKFy9hdkE4UXgak0HCB8WOveSKFO8B7dL2lpzh+/52/s+Y4AGfuNg/ hCSIjYblBX2OgMbvA2h6F2Qv0j2uckJZDRxDub1UKxP4bJOH4WTHBqtSeeCSCTYx0H 7Z4x1CKY/WTSw== From: Konrad Dybcio Date: Thu, 26 Jun 2025 11:02:39 +0200 Subject: [PATCH v6 12/14] soc: qcom: ubwc: Add #defines for UBWC swizzle bits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250626-topic-ubwc_central-v6-12-c94fa9d12040@oss.qualcomm.com> References: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> In-Reply-To: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750928557; l=7400; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=k6bQVh5apOZvCn3NdY3gb9ksXOWxEcp2zIS+Wb9Rp3I=; b=QskX1ehmx57lw/Bs4i1/WGK8Ckive08jFcVqPCXoXSJ6+qMQ8v+3DsGeHitkFb4N46VgD/Qmm PnY5ASSRNB4BsQIcIrqOgPhjZoEsGRLvCxd4dx4uyVpX3M2D5/8ZR25 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Make the values a bit more meaningful. This commit is intentionally cross-subsystem to ease review, as the patchset is intended to be merged together, with a maintainer consensus. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/soc/qcom/ubwc_config.c | 37 +++++++++++++++++++++++--------= ---- include/linux/soc/qcom/ubwc.h | 8 ++++---- 3 files changed, 30 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e16ad298ba1c11ed5b4c70487bc09e23b2ed5cce..6612030621b1b16c8662d39453b= 609c9c9ff982f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -679,7 +679,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; bool rgb565_predicator =3D cfg->ubwc_enc_version >=3D UBWC_4_0; - u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & BIT(1)); + u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LV= L2); bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; bool min_acc_len_64b =3D false; diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 3eb2f2118e5d1ca69cad2ed092542920537ff62c..816bad6674ab6fc61ba0d9ca5d8= 581f2b61e53a6 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -32,7 +32,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data =3D { static const struct qcom_ubwc_cfg_data sa8775p_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 4, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, @@ -41,7 +41,8 @@ static const struct qcom_ubwc_cfg_data sa8775p_data =3D { static const struct qcom_ubwc_cfg_data sar2130p_data =3D { .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, @@ -50,7 +51,8 @@ static const struct qcom_ubwc_cfg_data sar2130p_data =3D { static const struct qcom_ubwc_cfg_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -58,7 +60,8 @@ static const struct qcom_ubwc_cfg_data sc7180_data =3D { static const struct qcom_ubwc_cfg_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, .macrotile_mode =3D true, @@ -74,7 +77,8 @@ static const struct qcom_ubwc_cfg_data sc8180x_data =3D { static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 16, .macrotile_mode =3D true, @@ -95,7 +99,9 @@ static const struct qcom_ubwc_cfg_data sdm845_data =3D { static const struct qcom_ubwc_cfg_data sm6115_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 7, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -103,7 +109,9 @@ static const struct qcom_ubwc_cfg_data sm6115_data =3D { static const struct qcom_ubwc_cfg_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_3_0, - .ubwc_swizzle =3D 7, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 @@ -116,7 +124,8 @@ static const struct qcom_ubwc_cfg_data sm6150_data =3D { static const struct qcom_ubwc_cfg_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -136,7 +145,8 @@ static const struct qcom_ubwc_cfg_data sm8150_data =3D { static const struct qcom_ubwc_cfg_data sm8250_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -146,7 +156,8 @@ static const struct qcom_ubwc_cfg_data sm8250_data =3D { static const struct qcom_ubwc_cfg_data sm8350_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -156,7 +167,8 @@ static const struct qcom_ubwc_cfg_data sm8350_data =3D { static const struct qcom_ubwc_cfg_data sm8550_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -176,7 +188,8 @@ static const struct qcom_ubwc_cfg_data sm8750_data =3D { static const struct qcom_ubwc_cfg_data x1e80100_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index f0334f4ece2098ddf290eb182897cd8aa74608b3..1ed8b1b16bc90bea2ed54586edf= e21beb2db04d4 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -21,11 +21,11 @@ struct qcom_ubwc_cfg_data { * UBWC 1.0 always enables all three levels. * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. * UBWC 4.0 adds the optional ability to disable levels 2 & 3. - * - * This is a bitmask where BIT(0) enables level 1, BIT(1) - * controls level 2, and BIT(2) enables level 3. */ u32 ubwc_swizzle; +#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) +#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) +#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) =20 /** * @highest_bank_bit: Highest Bank Bit @@ -66,7 +66,7 @@ static inline bool qcom_ubwc_get_ubwc_mode(const struct q= com_ubwc_cfg_data *cfg) { bool ret =3D cfg->ubwc_enc_version =3D=3D UBWC_1_0; =20 - if (ret && !(cfg->ubwc_swizzle & BIT(0))) + if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1)) pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0= \n"); =20 return ret; --=20 2.50.0