From nobody Thu Sep 11 00:08:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A35812C0327; Thu, 26 Jun 2025 09:03:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928607; cv=none; b=W6EKO0LJQlW3wKjiSlEVQji1lebnpz79GCbnFjf0AdZ6Hqn83Fj6j5+5vYCAyDgKBSXUWwC6WGN8RxX5T9CfLTxljCPMJ+iVE/71ZOuIbvz+IyylL9LQurz38vbpbg+hQaZDBREBJAhGBr/lJwBE1KqF2desa6dYwyOGUlMiAww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928607; c=relaxed/simple; bh=S3JHmksvY8rkFLpju1G9DgL1dxkE0dccEaycj5QkxT4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=exC7UGT9UqiHB2X7XnhkHWkrOa9GCMeEfRZXkinvoQGnXr5ZcMDAJoVzH5tb8GlwIyEcqPAQt/5qSBMEL1GljmpjQLGP/HfrlW1/Zxbw5frQkdC8yHvxwQKDLkBldRcP/VKIhVKC3mqMKkwtqgGl2J0bmZTgy1dX/86RpIFf0I8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sD5qCayt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sD5qCayt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9372FC4CEEB; Thu, 26 Jun 2025 09:03:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750928607; bh=S3JHmksvY8rkFLpju1G9DgL1dxkE0dccEaycj5QkxT4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=sD5qCayttBEC2LYm994neRO0kSFyDLEX2dNrk0ZvAwPUWm7xwYTb4vaK3V74963sp kURIsDbjwWJDokvLkqHBDgCvlZbGbnFZU1fEjuEiajcsj0mE8e2nef89ezscDZ+50B 6qD0/KTvYy+kzPL1GmyTAQNkys2jw9uT/U91DOODl0mw3G3MC8KhaANPaCSrKqb8S3 5ucotSeOGyXjo2pYYH1GCOJSNzmZfWMEt42YjKmhd25gxDkkD4nvqCsa8E07VRIKAw Nm9aC6Zcu0wi/eUgxNFiQFvWNKM+CPbtR5t+s/HAec2nUlktRleafCkBd+5X8KjxrT w5Kse6ovgU4xg== From: Konrad Dybcio Date: Thu, 26 Jun 2025 11:02:37 +0200 Subject: [PATCH v6 10/14] drm/msm/a6xx: Simplify min_acc_len calculation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250626-topic-ubwc_central-v6-10-c94fa9d12040@oss.qualcomm.com> References: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> In-Reply-To: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750928557; l=3209; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=fqy5mvOCxz2r6HQMGGHFm7SBPbvkgv6eghecLNuPiso=; b=C7koqnR5xBymeDp64YxyyFa8/uWP9pD9hV47SVNAdaIvB53JqCI0MSJM6J3kNgtdemP+oiiHi cPXuhe0EKbEBjcyI7thb3/R78xWjiJS3wk+Oge+mOHVP0kW4J3xp0IB X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio It's only necessary for some lower end parts. Also rename it to min_acc_len_64b to denote that if set, the minimum access length is 64 bits, 32b otherwise. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 53493f68ead2113143dab594bfedf492014d5aaa..e16ad298ba1c11ed5b4c70487bc= 09e23b2ed5cce 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -610,14 +610,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) if (IS_ERR(gpu->common_ubwc_cfg)) return PTR_ERR(gpu->common_ubwc_cfg); =20 - gpu->ubwc_config.min_acc_len =3D 0; gpu->ubwc_config.ubwc_swizzle =3D 0x6; gpu->ubwc_config.macrotile_mode =3D 0; gpu->ubwc_config.highest_bank_bit =3D 15; =20 if (adreno_is_a610(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.min_acc_len =3D 1; gpu->ubwc_config.ubwc_swizzle =3D 0x7; } =20 @@ -663,10 +661,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gp= u) gpu->ubwc_config.macrotile_mode =3D 1; } =20 - if (adreno_is_a702(gpu)) { + if (adreno_is_a702(gpu)) gpu->ubwc_config.highest_bank_bit =3D 14; - gpu->ubwc_config.min_acc_len =3D 1; - } =20 return 0; } @@ -686,6 +682,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & BIT(1)); bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; + bool min_acc_len_64b =3D false; u8 uavflagprd_inv =3D 0; u32 hbb_hi =3D hbb >> 2; u32 hbb_lo =3D hbb & 3; @@ -693,22 +690,25 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) uavflagprd_inv =3D 2; =20 + if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) + min_acc_len_64b =3D true; + gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); =20 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, level2_swizzling_dis << 6 | hbb_hi << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); =20 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, level2_swizzling_dis << 12 | hbb_hi << 10 | uavflagprd_inv << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); =20 if (adreno_is_a7xx(adreno_gpu)) @@ -716,7 +716,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) FIELD_PREP(GENMASK(8, 5), hbb_lo)); =20 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, - adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); + min_acc_len_64b << 23 | hbb_lo << 21); =20 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, adreno_gpu->ubwc_config.macrotile_mode); --=20 2.50.0