From nobody Wed Sep 10 21:51:20 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A4831B85FD; Thu, 26 Jun 2025 09:02:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928567; cv=none; b=KiRBzBi3gpvkK/nXehgoMPNZe35Wd0yTQtEiEgIh0LKUcytEQ/DoE1+EEvGBcZGXOm2fl+KJGpRUmaHwlllCQgNoQFPf9e0Y3LskwcdK6W/bZT8xodD0DkP+Wqd+GonWvHcH4zRkzpYdtDHJowS9pJsyJgHgqtNml264Hh/lLt8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750928567; c=relaxed/simple; bh=alJPifqOzVSshcOVFP/ErzIBmKFQIDDeV6H2ERfenow=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O5gNtHdZF3Xn4K1w9m3OucEv7MkJPexYEohbhrc4zLqTeHRFGPRU4E1bm9w94lMt0PN/WzXOqHqSiwyq5XBlfO4nKzOQ4r/RKqHJOeqy4C8HvJEH1w9828FmAnVleg6/Wo4Kp731mUegfo0SNP5GgkNUEeBrUrr+LzNPNtB4UeU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=k23ePVex; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k23ePVex" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C43D2C4CEF1; Thu, 26 Jun 2025 09:02:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750928566; bh=alJPifqOzVSshcOVFP/ErzIBmKFQIDDeV6H2ERfenow=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=k23ePVexg20EUjdZCd2AvDk3sxUmqtLrd3yTzfQapjP/6F4lEu4X9swaS3HBU6Wjh qsvlQSGGKVC4oEg2UIXKvxXpPt2+TgC5M/luTmRWEGl0q1evCMfq/PNe/8THAsmjSf 7r/x3UAqb0LAqgXBzdj0lkokLUpxi3/f/9bdMcH+98op7zToI4y9Z/jZj+dHNGAAep a+bRB4lC5e7oXPi0hTKzL8D1GqGHWnodzHw0hLuNfl2CQt+OkiFoKn31VopYj9mCO6 xhI5ZHYEPpwCBq0/zXrkLzGGHh8xMqFwzMqA27fcnkGxeCYBXWkgEg749Tc5DW20Rv 9if8hPicH6gPA== From: Konrad Dybcio Date: Thu, 26 Jun 2025 11:02:28 +0200 Subject: [PATCH v6 01/14] soc: qcom: Add UBWC config provider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250626-topic-ubwc_central-v6-1-c94fa9d12040@oss.qualcomm.com> References: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> In-Reply-To: <20250626-topic-ubwc_central-v6-0-c94fa9d12040@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750928557; l=11931; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=4ZH2LaWR3T5V63/0TZmTgFZ943O/zSSslZWAs7fT8Ak=; b=gXvActgNe7WXU4aLKDi/sVQnGWAKrdMC64aOz0ej5o38TiMJCZ4Mf5q9dmVQkWtB07JBrwbHW TW6QBCNpDhrCJQfgNHqfT1APpSL7y4vkrNmsETt5eSgkH9RDOOsbLrm X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Add a file that will serve as a single source of truth for UBWC configuration data for various multimedia blocks. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/Kconfig | 8 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/ubwc_config.c | 251 +++++++++++++++++++++++++++++++++++++= ++++ include/linux/soc/qcom/ubwc.h | 65 +++++++++++ 4 files changed, 325 insertions(+) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 58e63cf0036ba8554e4082da5184a620ca807a9e..2caadbbcf8307ff94f5afbdd148= 1e5e5e291749f 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -296,3 +296,11 @@ config QCOM_PBS PBS trigger event to the PBS RAM. =20 endmenu + +config QCOM_UBWC_CONFIG + tristate + help + Most Qualcomm SoCs feature a number of Universal Bandwidth Compression + (UBWC) engines across various IP blocks, which need to be initialized + with coherent configuration data. This module functions as a single + source of truth for that information. diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index acbca2ab5cc2a9ab3dce1ff38efd048ba2fab31e..b7f1d2a5736748b8772c090fd24= 462fa91f321c6 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_QCOM_ICC_BWMON) +=3D icc-bwmon.o qcom_ice-objs +=3D ice.o obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) +=3D qcom_ice.o obj-$(CONFIG_QCOM_PBS) +=3D qcom-pbs.o +obj-$(CONFIG_QCOM_UBWC_CONFIG) +=3D ubwc_config.o diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c new file mode 100644 index 0000000000000000000000000000000000000000..18a853a3f76cc71dc6c2665c6b7= 486eb936331f6 --- /dev/null +++ b/drivers/soc/qcom/ubwc_config.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +static const struct qcom_ubwc_cfg_data msm8937_data =3D { + .ubwc_enc_version =3D UBWC_1_0, + .ubwc_dec_version =3D UBWC_1_0, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data msm8998_data =3D { + .ubwc_enc_version =3D UBWC_1_0, + .ubwc_dec_version =3D UBWC_1_0, + .highest_bank_bit =3D 15, +}; + +static const struct qcom_ubwc_cfg_data qcm2290_data =3D { + /* no UBWC */ + .highest_bank_bit =3D 15, +}; + +static const struct qcom_ubwc_cfg_data sa8775p_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 4, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 13, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sar2130p_data =3D { + .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ + .ubwc_dec_version =3D UBWC_4_3, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 13, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sc7180_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sc7280_data =3D { + .ubwc_enc_version =3D UBWC_3_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 14, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sc8180x_data =3D { + .ubwc_enc_version =3D UBWC_3_0, + .ubwc_dec_version =3D UBWC_3_0, + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sdm670_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sdm845_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .highest_bank_bit =3D 15, +}; + +static const struct qcom_ubwc_cfg_data sm6115_data =3D { + .ubwc_enc_version =3D UBWC_1_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 7, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm6125_data =3D { + .ubwc_enc_version =3D UBWC_1_0, + .ubwc_dec_version =3D UBWC_3_0, + .ubwc_swizzle =3D 1, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm6150_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm6350_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm7150_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm8150_data =3D { + .ubwc_enc_version =3D UBWC_3_0, + .ubwc_dec_version =3D UBWC_3_0, + .highest_bank_bit =3D 15, +}; + +static const struct qcom_ubwc_cfg_data sm8250_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sm8350_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sm8550_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_3, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sm8750_data =3D { + .ubwc_enc_version =3D UBWC_5_0, + .ubwc_dec_version =3D UBWC_5_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data x1e80100_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_3, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct of_device_id qcom_ubwc_configs[] __maybe_unused =3D { + { .compatible =3D "qcom,apq8096", .data =3D &msm8998_data }, + { .compatible =3D "qcom,msm8917", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8937", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8953", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8956", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8976", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8996", .data =3D &msm8998_data }, + { .compatible =3D "qcom,msm8998", .data =3D &msm8998_data }, + { .compatible =3D "qcom,qcm2290", .data =3D &qcm2290_data, }, + { .compatible =3D "qcom,qcm6490", .data =3D &sc7280_data, }, + { .compatible =3D "qcom,sa8155p", .data =3D &sm8150_data, }, + { .compatible =3D "qcom,sa8540p", .data =3D &sc8280xp_data, }, + { .compatible =3D "qcom,sa8775p", .data =3D &sa8775p_data, }, + { .compatible =3D "qcom,sar2130p", .data =3D &sar2130p_data }, + { .compatible =3D "qcom,sc7180", .data =3D &sc7180_data }, + { .compatible =3D "qcom,sc7280", .data =3D &sc7280_data, }, + { .compatible =3D "qcom,sc8180x", .data =3D &sc8180x_data, }, + { .compatible =3D "qcom,sc8280xp", .data =3D &sc8280xp_data, }, + { .compatible =3D "qcom,sdm630", .data =3D &msm8937_data }, + { .compatible =3D "qcom,sdm636", .data =3D &msm8937_data }, + { .compatible =3D "qcom,sdm660", .data =3D &msm8937_data }, + { .compatible =3D "qcom,sdm670", .data =3D &sdm670_data, }, + { .compatible =3D "qcom,sdm845", .data =3D &sdm845_data, }, + { .compatible =3D "qcom,sm4250", .data =3D &sm6115_data, }, + { .compatible =3D "qcom,sm6115", .data =3D &sm6115_data, }, + { .compatible =3D "qcom,sm6125", .data =3D &sm6125_data, }, + { .compatible =3D "qcom,sm6150", .data =3D &sm6150_data, }, + { .compatible =3D "qcom,sm6350", .data =3D &sm6350_data, }, + { .compatible =3D "qcom,sm6375", .data =3D &sm6350_data, }, + { .compatible =3D "qcom,sm7125", .data =3D &sc7180_data }, + { .compatible =3D "qcom,sm7150", .data =3D &sm7150_data, }, + { .compatible =3D "qcom,sm8150", .data =3D &sm8150_data, }, + { .compatible =3D "qcom,sm8250", .data =3D &sm8250_data, }, + { .compatible =3D "qcom,sm8350", .data =3D &sm8350_data, }, + { .compatible =3D "qcom,sm8450", .data =3D &sm8350_data, }, + { .compatible =3D "qcom,sm8550", .data =3D &sm8550_data, }, + { .compatible =3D "qcom,sm8650", .data =3D &sm8550_data, }, + { .compatible =3D "qcom,sm8750", .data =3D &sm8750_data, }, + { .compatible =3D "qcom,x1e80100", .data =3D &x1e80100_data, }, + { .compatible =3D "qcom,x1p42100", .data =3D &x1e80100_data, }, + { } +}; + +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void) +{ + const struct of_device_id *match; + struct device_node *root; + + root =3D of_find_node_by_path("/"); + if (!root) + return ERR_PTR(-ENODEV); + + match =3D of_match_node(qcom_ubwc_configs, root); + of_node_put(root); + if (!match) { + pr_err("Couldn't find UBWC config data for this platform!\n"); + return ERR_PTR(-EINVAL); + } + + return match->data; +} +EXPORT_SYMBOL_GPL(qcom_ubwc_config_get_data); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("UBWC config database for QTI SoCs"); diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h new file mode 100644 index 0000000000000000000000000000000000000000..b92fc402638bae85e4e9da2552b= e56ac9ea9b448 --- /dev/null +++ b/include/linux/soc/qcom/ubwc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __QCOM_UBWC_H__ +#define __QCOM_UBWC_H__ + +#include +#include + +struct qcom_ubwc_cfg_data { + u32 ubwc_enc_version; + /* Can be read from MDSS_BASE + 0x58 */ + u32 ubwc_dec_version; + + /** + * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling. + * + * UBWC 1.0 always enables all three levels. + * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. + * UBWC 4.0 adds the optional ability to disable levels 2 & 3. + * + * This is a bitmask where BIT(0) enables level 1, BIT(1) + * controls level 2, and BIT(2) enables level 3. + */ + u32 ubwc_swizzle; + + /** + * @highest_bank_bit: Highest Bank Bit + * + * The Highest Bank Bit value represents the bit of the highest + * DDR bank. This should ideally use DRAM type detection. + */ + int highest_bank_bit; + bool ubwc_bank_spread; + + /** + * @macrotile_mode: Macrotile Mode + * + * Whether to use 4-channel macrotiling mode or the newer + * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is + * 4-channel and 1 is 8-channel. + */ + bool macrotile_mode; +}; + +#define UBWC_1_0 0x10000000 +#define UBWC_2_0 0x20000000 +#define UBWC_3_0 0x30000000 +#define UBWC_4_0 0x40000000 +#define UBWC_4_3 0x40030000 +#define UBWC_5_0 0x50000000 + +#ifdef CONFIG_QCOM_UBWC_CONFIG +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void); +#else +static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(v= oid) +{ + return ERR_PTR(-EOPNOTSUPP); +} +#endif + +#endif /* __QCOM_UBWC_H__ */ --=20 2.50.0