From nobody Wed Oct 8 15:53:35 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 869AB20E313; Thu, 26 Jun 2025 19:50:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750967454; cv=none; b=C7A/k0hkYphSUF+XyMmyMaP7fDRc01ld+a2axFReQocDcdRuMgucfMUSwuDHtDy2skj4G7YYxvK/JtP/NAVhhls29h2fWqh96r5ZxDfugt+YFqxARSVaJ6ObYe8DQR/xEWgbPJxDVkb/+ImX7qCS6K26CplWcBFcmPasfsyufss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750967454; c=relaxed/simple; bh=jJPsksORo9lsgp1p9ZJ0jfPlhGmzEzRQXnkc4F5mk9Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ApnMC8fGSWTBbK/XwFkVhbJRwW5w6QwyMiE6zoBnbzIrEMQPWMMwEZ74c1fd5P+/P144RCgmmUwoLxaoO2Pv+Gu9UStwIrmlcLxhokgUf9u3jE2i87H8KkuFeshTLX1zULmNvdmzeJpzzKBrZg2XklgvuU2nc8GyXggRB4LQ/Co= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=MrnGOIWE; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="MrnGOIWE" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55QG1Q14008318; Thu, 26 Jun 2025 21:50:30 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 042xV4VlLkROsxC1ICsYPcF8y4C6Cn6Xw+YzbxHSTMU=; b=MrnGOIWE7r+kS90h 9LnZK0oLmgeEvYzrrBf3lTrGPn/OX56n9ShtT/Bb6S1jaK3khoAvKPiueSAarg19 FF8Mn+9eMJtRBLwl5VCHXlqv36Aj1MhaWLM+Ru7gLee+JGrXodrB0HVq75fBGByI c8DInhYHpKHnfIBf1x+wuMATy58kN4v/SwWbqAdCymDvnEIfpk4y76vAW0rIhvL8 Mg69LS/7wFCgMbUxE5REX3l/5xpHHcNaczSZ+wlAWM471J5CT6WfT2T0TMelgWyF 1nfqDJlQ6rw/NCaPIkLY6QTMeEb89mXNJvOo4jLc+vPBJTZE02Mw8f7sWZhp/7MA 4mNdXg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 47e6a6x9hk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Jun 2025 21:50:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 4126840047; Thu, 26 Jun 2025 21:49:36 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8C46DBD23CA; Thu, 26 Jun 2025 21:48:47 +0200 (CEST) Received: from localhost (10.252.1.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 26 Jun 2025 21:48:46 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Thu, 26 Jun 2025 21:48:35 +0200 Subject: [PATCH RFC 2/2] dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250626-ddr-bindings-v1-2-cae30933c54c@foss.st.com> References: <20250626-ddr-bindings-v1-0-cae30933c54c@foss.st.com> In-Reply-To: <20250626-ddr-bindings-v1-0-cae30933c54c@foss.st.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Will Deacon , Mark Rutland , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-c25d1 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-26_06,2025-06-26_05,2025-03-28_01 DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. It allows to monitor DDR events that come from the DDR Controller such as read or write events. Signed-off-by: Cl=C3=A9ment Le Goffic --- .../devicetree/bindings/perf/st,stm32-ddr-pmu.yaml | 90 ++++++++++++++++++= ++++ 1 file changed, 90 insertions(+) diff --git a/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml b= /Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml new file mode 100644 index 000000000000..98775f32475a --- /dev/null +++ b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/st,stm32-ddr-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Cl=C3=A9ment Le Goffic + +title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM) + +properties: + compatible: + oneOf: + enum: + - st,stm32mp131-ddr-pmu + - st,stm32mp151-ddr-pmu + const: st,stm32mp251-ddr-pmu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + access-controllers: + minItems: 1 + maxItems: 2 + + memory-channel: + description: | + The memory channel this DDRPERFM is attached to. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp131-ddr-pmu + - st,stm32mp151-ddr-pmu + then: + required: + - clocks + - resets + + - if: + properties: + compatible: + contains: + const: st,stm32mp251-ddr-pmu + then: + required: + - access-controllers + - st,dram-type + +additionalProperties: false + +examples: + - | + #include + #include + + perf@5a007000 { + compatible =3D "st,stm32mp151-ddr-pmu"; + reg =3D <0x5a007000 0x400>; + clocks =3D <&rcc DDRPERFM>; + resets =3D <&rcc DDRPERFM_R>; + }; + + - | + ddr_channel: ddr4-channel@0 { + compatible =3D "jedec,ddr4-channel"; + io-width =3D <32>; + }; + + perf@48041000 { + compatible =3D "st,stm32mp251-ddr-pmu"; + reg =3D <0x48041000 0x400>; + access-controllers =3D <&rcc 104>; + memory-channel =3D <&ddr_channel>; + }; --=20 2.43.0