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Wed, 25 Jun 2025 11:31:11 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Donald Hunter , Jiri Pirko , Jonathan Corbet , Leon Romanovsky , Chuck Lever , Jeff Layton , NeilBrown , Olga Kornievskaia , Dai Ngo , Tom Talpey , Shuah Khan , , , , , , , Carolina Jubran , Cosmin Ratiu , Mark Bloch Subject: [PATCH net-next v11 7/8] net/mlx5: Manage TC arbiter nodes and implement full support for tc-bw Date: Wed, 25 Jun 2025 21:30:17 +0300 Message-ID: <20250625183018.87065-8-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625183018.87065-1-mbloch@nvidia.com> References: <20250625183018.87065-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F5:EE_|IA0PR12MB7700:EE_ X-MS-Office365-Filtering-Correlation-Id: bdd78e37-ebd2-4c51-4fa0-08ddb4168364 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Dfv7PiuVBsCFZHBn85cfBG1hJIy0bzXTWvm2L7F3vGe04f7KowUgcJoePJYB?= =?us-ascii?Q?AEO07QiJ697puuILHBf8h0uXhmC6Pp98lwo/cYmOgjZb3XqkT6PBDuwxtMoQ?= =?us-ascii?Q?w+lOuU2X/2TfWlTvZM0yL90P4PZrvKVv5+/lzHrXk1O5XxSppJdiAVTUS5gQ?= =?us-ascii?Q?Xos16zD4/Go3yeaOQ50r6zBxYU6fk1MXkRb0Dq9B0wfYABU7iciSXzv8d2IJ?= =?us-ascii?Q?ySfGMS346EBsuYZ4bkCFIqcNIZaIiFbJLpV1kX4Fh6CMYt5ACrrK9WjsUaaK?= =?us-ascii?Q?xfxiZu77vtWzOGwFfwg62IZz97KVfiue/8lyg4ZLIYZGUToRdi1pu7RfiGYs?= =?us-ascii?Q?hj9SzOu8dsk3VV9kTOJV++yVaj3j9514fYM6fTPodESJtJDbnnq0grtaY2wM?= =?us-ascii?Q?9xJHFSiByx+CcYkFO4tg6EFhh99f4SgKGU06BK2ewiPW1x+b1L/Pg4ffEE+R?= =?us-ascii?Q?ccPvVqvwau8MkbiVAmETRHRAraUjRNwzOYV03eCRgaLzylOacjViJhTzXSTa?= =?us-ascii?Q?YCJ1tYfv4+OS7qIHSGYOpc0Xyibsgwnt5BzVfu8lMo3w1dtD1CaUjo4thVf7?= =?us-ascii?Q?QgzCMjwVpJ/zpuUyAs/3FrEBPGvnhtp9K2pJjtNiBc7X6hx4iW/eSRm6/2K1?= =?us-ascii?Q?URS/DbbdMeZqEkHy5En0IEEUim/acgIkltHoJzfV4bcdNyMYEVcU6jcejgNg?= =?us-ascii?Q?pa3wMuCpPrblkGC9bvde+incYO/hykSAqsY9uVwjnrUeCVfDu5CejYbD6l0B?= =?us-ascii?Q?I3ZwkHroxIugB20mpQo4H/oYYRMup7N6a81MF9wFBLN3YX3GWBbWON90EVQ1?= =?us-ascii?Q?T7iyIshtCrLMUsvKqAml3z3tVEup2LKipjezrP4E7j/CtZH7h+Lh+GUwuhRf?= =?us-ascii?Q?P00CLYYdPqDM32zdY/WX+VYttsvN1pspjng5A8ecNR01KDkiXCxFTKXoOmRf?= =?us-ascii?Q?ZnLSRZvW+RIxxH7KirwswZK6o3RVU/Qt8FZrBRr8X53zfmsp9j+arQJB2oF5?= =?us-ascii?Q?zMXgzYvAzU8378YqcQpvcLvdXbxGGdrTc4ezA5ufelroGik54m/qqgDz4JK8?= =?us-ascii?Q?odWmhr5qJ/qOsckjnV8RidEQ8upbrEyrDeN554w8rnTlMyUu+CUHh9HGZQVH?= =?us-ascii?Q?8Wg6w2mRGxy/7vz431jY1dlRkNfouaySfcoMFCcl46qciun8C1tsCHjj2HlS?= =?us-ascii?Q?W52r9Mu5TnmlGbTiUnFMp5CgnBA57lkDEbpSoXUYTgCfnyQgPL66oJKNGr6j?= =?us-ascii?Q?iWne25BZTGRuhg+sbrn57gJ1yOj6BV11vNKrazR0vkM4bNaAXPjQd/2tLz7C?= =?us-ascii?Q?DEABW1L1gA0ST4AJcruowATgLDhxBgQkGQt/ipycx5TYyzxTs+swjK9PycrP?= =?us-ascii?Q?Ln3ZHEjxfNXLRsNCACV17ru8qORJvjZrTT0lfyKK3Iwz9iJiDDCAZP3FM95v?= =?us-ascii?Q?pmrl74e6y5sux6flW6lWw+XwtXSdz9HtSv/lqGtz1dI9Lgs1/QVtztMwRgDW?= =?us-ascii?Q?/IJ7MscBePiqaKfzM6vR2HJEeMOqV+8vCHRP?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2025 18:31:34.2629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bdd78e37-ebd2-4c51-4fa0-08ddb4168364 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7700 Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Introduce support for managing Traffic Class (TC) arbiter nodes and associated vports TC nodes within the E-Switch QoS hierarchy. This patch adds support for the new scheduling node type, `SCHED_NODE_TYPE_VPORTS_TC_TSAR`, and implements full support for setting tc-bw on both vports and nodes. Key changes include: - Introduced the new scheduling node type, `SCHED_NODE_TYPE_VPORTS_TC_TSAR`, for managing vports within the TC arbiter node. - New helper functions for creating and destroying vports TC nodes under the TC arbiter. - Updated the minimum rate normalization function to skip nodes of type `SCHED_NODE_TYPE_VPORTS_TC_TSAR`. Vports TC TSARs have bandwidth shares configured on them but not minimum rates, so their `min_rate` cannot be normalized. - Implementation of `esw_qos_tc_arbiter_scheduling_setup()` and `esw_qos_tc_arbiter_scheduling_teardown()` for initializing and cleaning up TC arbiter scheduling elements. These functions now fully support tc-bw configuration on TC arbiter nodes. - Introduced a new helper `esw_qos_calculate_tc_bw_divider()` to compute the total TC bandwidth share, which is used as a divider for normalizing each TC's share. - Added `esw_qos_tc_arbiter_get_bw_shares()` and `esw_qos_set_tc_arbiter_bw_shares()` to handle the settings of bandwidth shares for vports traffic class TSARs. - `esw_qos_set_tc_arbiter_bw_shares()` normalizes each TC share based on the total and the firmware's maximum allowed TSAR bandwidth share. - Refactored `mlx5_esw_devlink_rate_node_tc_bw_set()` and `mlx5_esw_devlink_rate_leaf_tc_bw_set()` to fully support configuring tc-bw on devlink rate nodes and vports, respectively. - Refactored `mlx5_esw_qos_node_update_parent()` to ensure that tc-bw configuration remains compatible with setting a parent on a rate node, preserving level hierarchy functionality. - Refactored `esw_qos_calc_bw_share()` to generalize its input so it can be used for both minimum rate and bandwidth share calculations. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 294 +++++++++++++++++- 1 file changed, 285 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index dec3bed682b7..154bbb17ec0e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -67,6 +67,7 @@ enum sched_node_type { SCHED_NODE_TYPE_TC_ARBITER_TSAR, SCHED_NODE_TYPE_RATE_LIMITER, SCHED_NODE_TYPE_VPORT_TC, + SCHED_NODE_TYPE_VPORTS_TC_TSAR, }; =20 static const char * const sched_node_type_str[] =3D { @@ -75,6 +76,7 @@ static const char * const sched_node_type_str[] =3D { [SCHED_NODE_TYPE_TC_ARBITER_TSAR] =3D "TC Arbiter TSAR", [SCHED_NODE_TYPE_RATE_LIMITER] =3D "Rate Limiter", [SCHED_NODE_TYPE_VPORT_TC] =3D "vport TC", + [SCHED_NODE_TYPE_VPORTS_TC_TSAR] =3D "vports TC TSAR", }; =20 struct mlx5_esw_sched_node { @@ -187,6 +189,11 @@ mlx5_esw_qos_vport_get_parent(const struct mlx5_vport = *vport) static void esw_qos_sched_elem_warn(struct mlx5_esw_sched_node *node, int = err, const char *op) { switch (node->type) { + case SCHED_NODE_TYPE_VPORTS_TC_TSAR: + esw_warn(node->esw->dev, + "E-Switch %s %s scheduling element failed (tc=3D%d,err=3D%d)\n", + op, sched_node_type_str[node->type], node->tc, err); + break; case SCHED_NODE_TYPE_VPORT_TC: esw_warn(node->esw->dev, "E-Switch %s %s scheduling element failed (vport=3D%d,tc=3D%d,err=3D%d= )\n", @@ -345,11 +352,13 @@ static u32 esw_qos_calculate_min_rate_divider(struct = mlx5_eswitch *esw, return 0; } =20 -static u32 esw_qos_calc_bw_share(u32 min_rate, u32 divider, u32 fw_max) +static u32 esw_qos_calc_bw_share(u32 value, u32 divider, u32 fw_max) { if (!divider) return 0; - return min_t(u32, max_t(u32, DIV_ROUND_UP(min_rate, divider), MLX5_MIN_BW= _SHARE), fw_max); + return min_t(u32, fw_max, + max_t(u32, + DIV_ROUND_UP(value, divider), MLX5_MIN_BW_SHARE)); } =20 static void esw_qos_update_sched_node_bw_share(struct mlx5_esw_sched_node = *node, @@ -376,7 +385,13 @@ static void esw_qos_normalize_min_rate(struct mlx5_esw= itch *esw, if (node->esw !=3D esw || node->ix =3D=3D esw->qos.root_tsar_ix) continue; =20 - esw_qos_update_sched_node_bw_share(node, divider, extack); + /* Vports TC TSARs don't have a minimum rate configured, + * so there's no need to update the bw_share on them. + */ + if (node->type !=3D SCHED_NODE_TYPE_VPORTS_TC_TSAR) { + esw_qos_update_sched_node_bw_share(node, divider, + extack); + } =20 if (list_empty(&node->children)) continue; @@ -385,6 +400,20 @@ static void esw_qos_normalize_min_rate(struct mlx5_esw= itch *esw, } } =20 +static u32 esw_qos_calculate_tc_bw_divider(u32 *tc_bw) +{ + u32 total =3D 0; + int i; + + for (i =3D 0; i < DEVLINK_RATE_TCS_MAX; i++) + total +=3D tc_bw[i]; + + /* If total is zero, tc-bw config is disabled and we shouldn't reach + * here. + */ + return WARN_ON(!total) ? 1 : total; +} + static int esw_qos_set_node_min_rate(struct mlx5_esw_sched_node *node, u32 min_rate, struct netlink_ext_ack *extack) { @@ -527,6 +556,149 @@ static void esw_qos_destroy_node(struct mlx5_esw_sche= d_node *node, struct netlin __esw_qos_free_node(node); } =20 +static int esw_qos_create_vports_tc_node(struct mlx5_esw_sched_node *paren= t, + u8 tc, struct netlink_ext_ack *extack) +{ + u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] =3D {}; + struct mlx5_core_dev *dev =3D parent->esw->dev; + struct mlx5_esw_sched_node *vports_tc_node; + void *attr; + int err; + + if (!mlx5_qos_element_type_supported( + dev, + SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR, + SCHEDULING_HIERARCHY_E_SWITCH) || + !mlx5_qos_tsar_type_supported(dev, + TSAR_ELEMENT_TSAR_TYPE_DWRR, + SCHEDULING_HIERARCHY_E_SWITCH)) + return -EOPNOTSUPP; + + vports_tc_node =3D __esw_qos_alloc_node(parent->esw, 0, + SCHED_NODE_TYPE_VPORTS_TC_TSAR, + parent); + if (!vports_tc_node) { + NL_SET_ERR_MSG_MOD(extack, "E-Switch alloc node failed"); + esw_warn(dev, "Failed to alloc vports TC node (tc=3D%d)\n", tc); + return -ENOMEM; + } + + attr =3D MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes); + MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR); + MLX5_SET(tsar_element, attr, traffic_class, tc); + MLX5_SET(scheduling_context, tsar_ctx, parent_element_id, parent->ix); + MLX5_SET(scheduling_context, tsar_ctx, element_type, + SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR); + + err =3D esw_qos_node_create_sched_element(vports_tc_node, tsar_ctx, + extack); + if (err) + goto err_create_sched_element; + + vports_tc_node->tc =3D tc; + + return 0; + +err_create_sched_element: + __esw_qos_free_node(vports_tc_node); + return err; +} + +static void +esw_qos_tc_arbiter_get_bw_shares(struct mlx5_esw_sched_node *tc_arbiter_no= de, + u32 *tc_bw) +{ + struct mlx5_esw_sched_node *vports_tc_node; + + list_for_each_entry(vports_tc_node, &tc_arbiter_node->children, entry) + tc_bw[vports_tc_node->tc] =3D vports_tc_node->bw_share; +} + +static void +esw_qos_set_tc_arbiter_bw_shares(struct mlx5_esw_sched_node *tc_arbiter_no= de, + u32 *tc_bw, struct netlink_ext_ack *extack) +{ + struct mlx5_eswitch *esw =3D tc_arbiter_node->esw; + struct mlx5_esw_sched_node *vports_tc_node; + u32 divider, fw_max_bw_share; + + fw_max_bw_share =3D MLX5_CAP_QOS(esw->dev, max_tsar_bw_share); + divider =3D esw_qos_calculate_tc_bw_divider(tc_bw); + list_for_each_entry(vports_tc_node, &tc_arbiter_node->children, entry) { + u8 tc =3D vports_tc_node->tc; + u32 bw_share; + + bw_share =3D tc_bw[tc] * fw_max_bw_share; + bw_share =3D esw_qos_calc_bw_share(bw_share, divider, + fw_max_bw_share); + esw_qos_sched_elem_config(vports_tc_node, 0, bw_share, extack); + } +} + +static void +esw_qos_destroy_vports_tc_nodes(struct mlx5_esw_sched_node *tc_arbiter_nod= e, + struct netlink_ext_ack *extack) +{ + struct mlx5_esw_sched_node *vports_tc_node, *tmp; + + list_for_each_entry_safe(vports_tc_node, tmp, + &tc_arbiter_node->children, entry) + esw_qos_destroy_node(vports_tc_node, extack); +} + +static int +esw_qos_create_vports_tc_nodes(struct mlx5_esw_sched_node *tc_arbiter_node, + struct netlink_ext_ack *extack) +{ + struct mlx5_eswitch *esw =3D tc_arbiter_node->esw; + int err, i, num_tcs =3D esw_qos_num_tcs(esw->dev); + + for (i =3D 0; i < num_tcs; i++) { + err =3D esw_qos_create_vports_tc_node(tc_arbiter_node, i, extack); + if (err) + goto err_tc_node_create; + } + + return 0; + +err_tc_node_create: + esw_qos_destroy_vports_tc_nodes(tc_arbiter_node, NULL); + return err; +} + +static int esw_qos_create_tc_arbiter_sched_elem( + struct mlx5_esw_sched_node *tc_arbiter_node, + struct netlink_ext_ack *extack) +{ + u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] =3D {}; + u32 tsar_parent_ix; + void *attr; + + if (!mlx5_qos_tsar_type_supported(tc_arbiter_node->esw->dev, + TSAR_ELEMENT_TSAR_TYPE_TC_ARB, + SCHEDULING_HIERARCHY_E_SWITCH)) { + NL_SET_ERR_MSG_MOD(extack, + "E-Switch TC Arbiter scheduling element is not supported"); + return -EOPNOTSUPP; + } + + attr =3D MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes); + MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_TC_ARB); + tsar_parent_ix =3D tc_arbiter_node->parent ? tc_arbiter_node->parent->ix : + tc_arbiter_node->esw->qos.root_tsar_ix; + MLX5_SET(scheduling_context, tsar_ctx, parent_element_id, + tsar_parent_ix); + MLX5_SET(scheduling_context, tsar_ctx, element_type, + SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR); + MLX5_SET(scheduling_context, tsar_ctx, max_average_bw, + tc_arbiter_node->max_rate); + MLX5_SET(scheduling_context, tsar_ctx, bw_share, + tc_arbiter_node->bw_share); + + return esw_qos_node_create_sched_element(tc_arbiter_node, tsar_ctx, + extack); +} + static struct mlx5_esw_sched_node * __esw_qos_create_vports_sched_node(struct mlx5_eswitch *esw, struct mlx5_e= sw_sched_node *parent, struct netlink_ext_ack *extack) @@ -591,6 +763,9 @@ static void __esw_qos_destroy_node(struct mlx5_esw_sche= d_node *node, struct netl { struct mlx5_eswitch *esw =3D node->esw; =20 + if (node->type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR) + esw_qos_destroy_vports_tc_nodes(node, extack); + trace_mlx5_esw_node_qos_destroy(esw->dev, node, node->ix); esw_qos_destroy_node(node, extack); esw_qos_normalize_min_rate(esw, NULL, extack); @@ -685,13 +860,38 @@ static void esw_qos_put(struct mlx5_eswitch *esw) static void esw_qos_tc_arbiter_scheduling_teardown(struct mlx5_esw_sched_node *node, struct netlink_ext_ack *extack) -{} +{ + /* Clean up all Vports TC nodes within the TC arbiter node. */ + esw_qos_destroy_vports_tc_nodes(node, extack); + /* Destroy the scheduling element for the TC arbiter node itself. */ + esw_qos_node_destroy_sched_element(node, extack); +} =20 static int esw_qos_tc_arbiter_scheduling_setup(struct mlx5_esw_sched_node = *node, struct netlink_ext_ack *extack) { - NL_SET_ERR_MSG_MOD(extack, "TC arbiter elements are not supported."); - return -EOPNOTSUPP; + u32 curr_ix =3D node->ix; + int err; + + err =3D esw_qos_create_tc_arbiter_sched_elem(node, extack); + if (err) + return err; + /* Initialize the vports TC nodes within created TC arbiter TSAR. */ + err =3D esw_qos_create_vports_tc_nodes(node, extack); + if (err) + goto err_vports_tc_nodes; + + node->type =3D SCHED_NODE_TYPE_TC_ARBITER_TSAR; + + return 0; + +err_vports_tc_nodes: + /* If initialization fails, clean up the scheduling element + * for the TC arbiter node. + */ + esw_qos_node_destroy_sched_element(node, NULL); + node->ix =3D curr_ix; + return err; } =20 static int @@ -1064,6 +1264,7 @@ static int esw_qos_vport_update(struct mlx5_vport *vp= ort, { struct mlx5_esw_sched_node *curr_parent =3D vport->qos.sched_node->parent; enum sched_node_type curr_type =3D vport->qos.sched_node->type; + u32 curr_tc_bw[DEVLINK_RATE_TCS_MAX] =3D {0}; int err; =20 esw_assert_qos_lock_held(vport->dev->priv.eswitch); @@ -1075,11 +1276,23 @@ static int esw_qos_vport_update(struct mlx5_vport *= vport, if (err) return err; =20 + if (curr_type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR && curr_type =3D=3D = type) { + esw_qos_tc_arbiter_get_bw_shares(vport->qos.sched_node, + curr_tc_bw); + } + esw_qos_vport_disable(vport, extack); =20 err =3D esw_qos_vport_enable(vport, type, parent, extack); - if (err) + if (err) { esw_qos_vport_enable(vport, curr_type, curr_parent, NULL); + extack =3D NULL; + } + + if (curr_type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR && curr_type =3D=3D = type) { + esw_qos_set_tc_arbiter_bw_shares(vport->qos.sched_node, + curr_tc_bw, extack); + } =20 return err; } @@ -1563,6 +1776,8 @@ int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devli= nk_rate *rate_leaf, SCHED_NODE_TYPE_TC_ARBITER_TSAR, NULL, extack); } + if (!err) + esw_qos_set_tc_arbiter_bw_shares(vport_node, tc_bw, extack); unlock: esw_qos_unlock(esw); return err; @@ -1592,6 +1807,8 @@ int mlx5_esw_devlink_rate_node_tc_bw_set(struct devli= nk_rate *rate_node, } =20 err =3D esw_qos_node_enable_tc_arbitration(node, extack); + if (!err) + esw_qos_set_tc_arbiter_bw_shares(node, tc_bw, extack); unlock: esw_qos_unlock(esw); return err; @@ -1716,6 +1933,20 @@ int mlx5_esw_devlink_rate_leaf_parent_set(struct dev= link_rate *devlink_rate, return mlx5_esw_qos_vport_update_parent(vport, node, extack); } =20 +static bool esw_qos_is_node_empty(struct mlx5_esw_sched_node *node) +{ + if (list_empty(&node->children)) + return true; + + if (node->type !=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR) + return false; + + node =3D list_first_entry(&node->children, struct mlx5_esw_sched_node, + entry); + + return esw_qos_is_node_empty(node); +} + static int mlx5_esw_qos_node_validate_set_parent(struct mlx5_esw_sched_node *node, struct mlx5_esw_sched_node *parent, @@ -1729,13 +1960,26 @@ mlx5_esw_qos_node_validate_set_parent(struct mlx5_e= sw_sched_node *node, return -EOPNOTSUPP; } =20 - if (!list_empty(&node->children)) { + if (!esw_qos_is_node_empty(node)) { NL_SET_ERR_MSG_MOD(extack, "Cannot reassign a node that contains rate objects"); return -EOPNOTSUPP; } =20 + if (parent && parent->type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR) { + NL_SET_ERR_MSG_MOD(extack, + "Cannot attach a node to a parent with TC bandwidth configured"); + return -EOPNOTSUPP; + } + new_level =3D parent ? parent->level + 1 : 2; + if (node->type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR) { + /* Increase by one to account for the vports TC scheduling + * element. + */ + new_level +=3D 1; + } + max_level =3D 1 << MLX5_CAP_QOS(node->esw->dev, log_esw_max_sched_depth); if (new_level > max_level) { NL_SET_ERR_MSG_MOD(extack, @@ -1746,6 +1990,32 @@ mlx5_esw_qos_node_validate_set_parent(struct mlx5_es= w_sched_node *node, return 0; } =20 +static int +esw_qos_tc_arbiter_node_update_parent(struct mlx5_esw_sched_node *node, + struct mlx5_esw_sched_node *parent, + struct netlink_ext_ack *extack) +{ + struct mlx5_esw_sched_node *curr_parent =3D node->parent; + u32 curr_tc_bw[DEVLINK_RATE_TCS_MAX] =3D {0}; + struct mlx5_eswitch *esw =3D node->esw; + int err; + + esw_qos_tc_arbiter_get_bw_shares(node, curr_tc_bw); + esw_qos_tc_arbiter_scheduling_teardown(node, extack); + esw_qos_node_set_parent(node, parent); + err =3D esw_qos_tc_arbiter_scheduling_setup(node, extack); + if (err) { + esw_qos_node_set_parent(node, curr_parent); + if (esw_qos_tc_arbiter_scheduling_setup(node, extack)) { + esw_warn(esw->dev, "Node restore QoS failed\n"); + return err; + } + } + esw_qos_set_tc_arbiter_bw_shares(node, curr_tc_bw, extack); + + return err; +} + static int esw_qos_vports_node_update_parent(struct mlx5_esw_sched_node *n= ode, struct mlx5_esw_sched_node *parent, struct netlink_ext_ack *extack) @@ -1791,7 +2061,13 @@ static int mlx5_esw_qos_node_update_parent(struct ml= x5_esw_sched_node *node, =20 esw_qos_lock(esw); curr_parent =3D node->parent; - err =3D esw_qos_vports_node_update_parent(node, parent, extack); + if (node->type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR) { + err =3D esw_qos_tc_arbiter_node_update_parent(node, parent, + extack); + } else { + err =3D esw_qos_vports_node_update_parent(node, parent, extack); + } + if (err) goto out; =20 --=20 2.34.1