From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F74F2E06D1 for ; Wed, 25 Jun 2025 16:56:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870605; cv=none; b=nzMHyrfPbq4ATTvV08+z3XYzjAoOMCIsIanw8D88OC12Vcyyy62aPQATlA4RqqZ2sLJ2I8hvRvZlKwnroL/KMib3r1k6nifyj4d+wtVZMg/epBRFW0nwyIpuvgTBMqg1p0JWP/F3Rjnf2u6AJjNXwVGUX2o7EYYV3UgmeuwEqNE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870605; c=relaxed/simple; bh=u16CpbdUihPkyI+FiM2IX3TbeuU1zDLWDn5AwsQR/6k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aXOrv2KB3GwRj45LiCZFUeEiqZkhHGA4+ThVpuNCdw4xfJgD/702nNie+TSuoUZ1prl2w6/LNRXl6fQF0Aalt6gHERwHpXVt+h/POSPQd3B/OgkKp6bUoE0seoHcsgU2YZZaHCfOPIwxdqvvC0d4EgR+a8c0mQj2zEzSfcRz92w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EdsUOa00; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EdsUOa00" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870603; x=1782406603; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u16CpbdUihPkyI+FiM2IX3TbeuU1zDLWDn5AwsQR/6k=; b=EdsUOa00BCP7pH6sJfoEj8cKxFjfo7fbCO8vM3f4HSOAJyTiCKybQ8oA laDwHKeRrpQQfO548BbswChV/sjHHHcS0ZfQ9un/pBcovPgzRFDxnLxmf DImaIU2HEyOVc4HmCCJo8T0bswnADD8pQLdCPFPqSL2bYFrkQq/ldxroV fc+OxI/jjmpic5JPpv+2YIyXx+ugLzW0XP+YjPW4+3c68gLZhtWs9d5pa UiK2MAYYrSw3mF1uJupYcH3B9OySZSxNIJ/0nPiC6n/8IvKGrR9yMR9LQ PPAUAwXsnfRiMsIG1dD3Z9QkFqkKNJ+vZz1zFt7noTkLESqb2r6G7z+Xi Q==; X-CSE-ConnectionGUID: Q6eegpc3S3aw2Gdi6dlvLg== X-CSE-MsgGUID: +3XkmrSWRfW/WSqvhtZnmw== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214424" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214424" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:43 -0700 X-CSE-ConnectionGUID: i0R0NCMXTtqsoC6VR/6eAw== X-CSE-MsgGUID: aSvDYzgdT/e8bl4rXIPAfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696609" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:40 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 01/10] mei: bus: add mei_cldev_mtu interface Date: Wed, 25 Jun 2025 22:30:06 +0530 Message-Id: <20250625170015.33912-2-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Allow to bus client to obtain client mtu. Signed-off-by: Alexander Usyskin Signed-off-by: Badal Nilawar Reviewed-by: Umesh Nerlige Ramappa --- drivers/misc/mei/bus.c | 13 +++++++++++++ include/linux/mei_cl_bus.h | 1 + 2 files changed, 14 insertions(+) diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c index 67176caf5416..f860b1b6eda0 100644 --- a/drivers/misc/mei/bus.c +++ b/drivers/misc/mei/bus.c @@ -614,6 +614,19 @@ u8 mei_cldev_ver(const struct mei_cl_device *cldev) } EXPORT_SYMBOL_GPL(mei_cldev_ver); =20 +/** + * mei_cldev_mtu - max message that client can send and receive + * + * @cldev: mei client device + * + * Return: mtu or 0 if client is not connected + */ +size_t mei_cldev_mtu(const struct mei_cl_device *cldev) +{ + return mei_cl_mtu(cldev->cl); +} +EXPORT_SYMBOL_GPL(mei_cldev_mtu); + /** * mei_cldev_enabled - check whether the device is enabled * diff --git a/include/linux/mei_cl_bus.h b/include/linux/mei_cl_bus.h index 725fd7727422..a82755e1fc40 100644 --- a/include/linux/mei_cl_bus.h +++ b/include/linux/mei_cl_bus.h @@ -113,6 +113,7 @@ int mei_cldev_register_notif_cb(struct mei_cl_device *c= ldev, mei_cldev_cb_t notif_cb); =20 u8 mei_cldev_ver(const struct mei_cl_device *cldev); +size_t mei_cldev_mtu(const struct mei_cl_device *cldev); =20 void *mei_cldev_get_drvdata(const struct mei_cl_device *cldev); void mei_cldev_set_drvdata(struct mei_cl_device *cldev, void *data); --=20 2.34.1 From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5337C2E0B76 for ; Wed, 25 Jun 2025 16:56:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870608; cv=none; b=DoG8Fnrw8lzZKa5ZLSqeXTR2xO/ClPh5vykvSIAWaj5V0wFGfijD2nm28ka2nEkx9JxBbFGFYGdIkrmtz3/qgwpgdowQWB8L78WKcOHLqncfUpU4UYdgUNZYGVC5Da9V7ziTNAwlffg+4HJwlsVJblIZ3qwrL05iYA6KzyyT738= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870608; c=relaxed/simple; bh=N5neMXU3Ra29sTkeQ2qeaP+/CN5JIDzJQcXIWn2sq4Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eLQqcmVJmkNaQVWbwYne+Fjs7uZo/Woa7Mav47nC11Pn3VtzWPrI5xOOA6mU5XkJ4wKQ3IrfFi45D1KPf3KI3EsHO8//Qi4vW5cluviXPuPGLOQzY20TMd+eNCENI563jjiBoQaI6OLx47mFMIYSbQId62tpmRMrTFqNSmHXENM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gx2uJpF5; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gx2uJpF5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870606; x=1782406606; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N5neMXU3Ra29sTkeQ2qeaP+/CN5JIDzJQcXIWn2sq4Q=; b=gx2uJpF5ZaljwLSsYdIh0ppKfia/EDsx1E/liAC4ErxfmO7dyt0vs92c qCyoo+NCUmprzSgfHonJ+zdx+40cntD1Rl1/3S6BL5mzo7JLO0KpIbm5v w0NyCP/1mPE2+DGS0+wdyp4f9vRkkMT2wtFOooMsg0x2YuMYLmR1Brb90 LUgl2Eqa45NcFuE25MOUeEdWUMou78kf6PzFzpFAd4oW5EyrREh1ccS6L J8E2tPAfNl/OJdiqpuyOvbcF9LV6N67hmVhuFY68QDh8/G++vAQT6b+d3 XiBUf+HTNqnph4nsctwjVFAU3vSrWbVDPT+p8JgWW6aHf3caq4/u7arbV g==; X-CSE-ConnectionGUID: 656cLbg3SwqpzMoRWkZ9Fg== X-CSE-MsgGUID: SbruAFCBSx2o0Gnfl7K6fw== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214429" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214429" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:46 -0700 X-CSE-ConnectionGUID: spXe8JCiQ0+s/w1YL0BgTA== X-CSE-MsgGUID: 2eGxXAGWSrOPBv7FS3H+og== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696634" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:43 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 02/10] mei: late_bind: add late binding component driver Date: Wed, 25 Jun 2025 22:30:07 +0530 Message-Id: <20250625170015.33912-3-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Add late binding component driver. It allows pushing the late binding configuration from, for example, the Xe graphics driver to the Intel discrete graphics card's CSE device. Signed-off-by: Alexander Usyskin Signed-off-by: Badal Nilawar Reviewed-by: Anshuman Gupta --- v2: - Use generic naming (Jani) - Drop xe_late_bind_component struct to move to xe code (Daniele/Sasha) v3: - Updated kconfig description - Move CSC late binding specific flags/defines to late_bind_mei_interface.= h (Daniele) v4: - Add match for PCI_CLASS_DISPLAY_OTHER to support headless cards (Anshuma= n) v5: - Add fixes in push_config (Sasha) - Use INTEL_ prefix for component, refine doc, add status enum to headerlate_bind_mei_interface.h (Anshuman) --- drivers/misc/mei/Kconfig | 1 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/late_bind/Kconfig | 13 + drivers/misc/mei/late_bind/Makefile | 9 + drivers/misc/mei/late_bind/mei_late_bind.c | 281 ++++++++++++++++++++ include/drm/intel/i915_component.h | 1 + include/drm/intel/late_bind_mei_interface.h | 64 +++++ 7 files changed, 370 insertions(+) create mode 100644 drivers/misc/mei/late_bind/Kconfig create mode 100644 drivers/misc/mei/late_bind/Makefile create mode 100644 drivers/misc/mei/late_bind/mei_late_bind.c create mode 100644 include/drm/intel/late_bind_mei_interface.h diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 7575fee96cc6..771becc68095 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -84,5 +84,6 @@ config INTEL_MEI_VSC source "drivers/misc/mei/hdcp/Kconfig" source "drivers/misc/mei/pxp/Kconfig" source "drivers/misc/mei/gsc_proxy/Kconfig" +source "drivers/misc/mei/late_bind/Kconfig" =20 endif diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index 6f9fdbf1a495..84bfde888d81 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -31,6 +31,7 @@ CFLAGS_mei-trace.o =3D -I$(src) obj-$(CONFIG_INTEL_MEI_HDCP) +=3D hdcp/ obj-$(CONFIG_INTEL_MEI_PXP) +=3D pxp/ obj-$(CONFIG_INTEL_MEI_GSC_PROXY) +=3D gsc_proxy/ +obj-$(CONFIG_INTEL_MEI_LATE_BIND) +=3D late_bind/ =20 obj-$(CONFIG_INTEL_MEI_VSC_HW) +=3D mei-vsc-hw.o mei-vsc-hw-y :=3D vsc-tp.o diff --git a/drivers/misc/mei/late_bind/Kconfig b/drivers/misc/mei/late_bin= d/Kconfig new file mode 100644 index 000000000000..65c7180c5678 --- /dev/null +++ b/drivers/misc/mei/late_bind/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2025, Intel Corporation. All rights reserved. +# +config INTEL_MEI_LATE_BIND + tristate "Intel late binding support on ME Interface" + select INTEL_MEI_ME + depends on DRM_XE + help + MEI Support for Late Binding for Intel graphics card. + + Enables the ME FW interfaces for Late Binding feature, + allowing loading of firmware for the devices like Fan + Controller during by Intel Xe driver. diff --git a/drivers/misc/mei/late_bind/Makefile b/drivers/misc/mei/late_bi= nd/Makefile new file mode 100644 index 000000000000..a0aeda5853f0 --- /dev/null +++ b/drivers/misc/mei/late_bind/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2025, Intel Corporation. All rights reserved. +# +# Makefile - Late Binding client driver for Intel MEI Bus Driver. + +subdir-ccflags-y +=3D -I$(srctree)/drivers/misc/mei/ + +obj-$(CONFIG_INTEL_MEI_LATE_BIND) +=3D mei_late_bind.o diff --git a/drivers/misc/mei/late_bind/mei_late_bind.c b/drivers/misc/mei/= late_bind/mei_late_bind.c new file mode 100644 index 000000000000..ffb89ccdfbb1 --- /dev/null +++ b/drivers/misc/mei/late_bind/mei_late_bind.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Intel Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mkhi.h" + +#define GFX_SRV_MKHI_LATE_BINDING_CMD 0x12 +#define GFX_SRV_MKHI_LATE_BINDING_RSP (GFX_SRV_MKHI_LATE_BINDING_CMD | 0x8= 0) + +#define LATE_BIND_SEND_TIMEOUT_MSEC 3000 +#define LATE_BIND_RECV_TIMEOUT_MSEC 3000 + +/** + * struct csc_heci_late_bind_req - late binding request + * @header: @ref mkhi_msg_hdr + * @type: type of the late binding payload + * @flags: flags to be passed to the firmware + * @reserved: reserved field + * @payload_size: size of the payload data in bytes + * @payload: data to be sent to the firmware + */ +struct csc_heci_late_bind_req { + struct mkhi_msg_hdr header; + u32 type; + u32 flags; + u32 reserved[2]; + u32 payload_size; + u8 payload[] __counted_by(payload_size); +} __packed; + +/** + * struct csc_heci_late_bind_rsp - late binding response + * @header: @ref mkhi_msg_hdr + * @type: type of the late binding payload + * @reserved: reserved field + * @status: status of the late binding command execution by firmware + */ +struct csc_heci_late_bind_rsp { + struct mkhi_msg_hdr header; + u32 type; + u32 reserved[2]; + u32 status; +} __packed; + +static int mei_late_bind_check_response(const struct device *dev, const st= ruct mkhi_msg_hdr *hdr) +{ + if (hdr->group_id !=3D MKHI_GROUP_ID_GFX) { + dev_err(dev, "Mismatch group id: 0x%x instead of 0x%x\n", + hdr->group_id, MKHI_GROUP_ID_GFX); + return -EINVAL; + } + + if (hdr->command !=3D GFX_SRV_MKHI_LATE_BINDING_RSP) { + dev_err(dev, "Mismatch command: 0x%x instead of 0x%x\n", + hdr->command, GFX_SRV_MKHI_LATE_BINDING_RSP); + return -EINVAL; + } + + if (hdr->result) { + dev_err(dev, "Error in result: 0x%x\n", hdr->result); + return -EINVAL; + } + + return 0; +} + +/** + * mei_late_bind_push_config - Sends a config to the firmware. + * @dev: device struct corresponding to the mei device + * @type: payload type + * @flags: payload flags + * @payload: payload buffer + * @payload_size: payload buffer size + * + * Return: 0 success, negative errno value on transport failure, + * positive status returned by FW + */ +static int mei_late_bind_push_config(struct device *dev, u32 type, u32 fla= gs, + const void *payload, size_t payload_size) +{ + struct mei_cl_device *cldev; + struct csc_heci_late_bind_req *req =3D NULL; + struct csc_heci_late_bind_rsp rsp; + size_t req_size; + ssize_t ret; + + if (!dev || !payload || !payload_size) + return -EINVAL; + + cldev =3D to_mei_cl_device(dev); + + ret =3D mei_cldev_enable(cldev); + if (ret < 0) { + dev_dbg(dev, "mei_cldev_enable failed. %zd\n", ret); + return ret; + } + + req_size =3D struct_size(req, payload, payload_size); + if (req_size > mei_cldev_mtu(cldev)) { + dev_err(dev, "Payload is too big %zu\n", payload_size); + ret =3D -EMSGSIZE; + goto end; + } + + req =3D kmalloc(req_size, GFP_KERNEL); + if (!req) { + ret =3D -ENOMEM; + goto end; + } + + req->header.group_id =3D MKHI_GROUP_ID_GFX; + req->header.command =3D GFX_SRV_MKHI_LATE_BINDING_CMD; + req->type =3D type; + req->flags =3D flags; + req->reserved[0] =3D 0; + req->reserved[1] =3D 0; + req->payload_size =3D payload_size; + memcpy(req->payload, payload, payload_size); + + ret =3D mei_cldev_send_timeout(cldev, (void *)req, req_size, LATE_BIND_SE= ND_TIMEOUT_MSEC); + if (ret < 0) { + dev_err(dev, "mei_cldev_send failed. %zd\n", ret); + goto end; + } + + ret =3D mei_cldev_recv_timeout(cldev, (void *)&rsp, sizeof(rsp), LATE_BIN= D_RECV_TIMEOUT_MSEC); + if (ret < 0) { + dev_err(dev, "mei_cldev_recv failed. %zd\n", ret); + goto end; + } + if (ret < sizeof(rsp.header)) { + dev_err(dev, "bad response header from the firmware: size %zd < %zu\n", + ret, sizeof(rsp.header)); + goto end; + } + if (ret < sizeof(rsp)) { + dev_err(dev, "bad response from the firmware: size %zd < %zu\n", + ret, sizeof(rsp)); + goto end; + } + + ret =3D mei_late_bind_check_response(dev, &rsp.header); + if (ret) { + dev_err(dev, "bad result response from the firmware: 0x%x\n", + *(uint32_t *)&rsp.header); + goto end; + } + + ret =3D (int)rsp.status; + dev_dbg(dev, "%s status =3D %zd\n", __func__, ret); + +end: + mei_cldev_disable(cldev); + kfree(req); + return ret; +} + +static const struct late_bind_component_ops mei_late_bind_ops =3D { + .owner =3D THIS_MODULE, + .push_config =3D mei_late_bind_push_config, +}; + +static int mei_component_master_bind(struct device *dev) +{ + return component_bind_all(dev, (void *)&mei_late_bind_ops); +} + +static void mei_component_master_unbind(struct device *dev) +{ + component_unbind_all(dev, (void *)&mei_late_bind_ops); +} + +static const struct component_master_ops mei_component_master_ops =3D { + .bind =3D mei_component_master_bind, + .unbind =3D mei_component_master_unbind, +}; + +/** + * mei_late_bind_component_match - compare function for matching mei late = bind. + * + * The function checks if requester is Intel PCI_CLASS_DISPLAY_VGA or + * PCI_CLASS_DISPLAY_OTHER device, and checks if the parent of requester + * and the grand parent of mei_if are the same device + * + * @dev: master device + * @subcomponent: subcomponent to match (INTEL_COMPONENT_LATE_BIND) + * @data: compare data (late_bind mei device on mei bus) + * + * Return: + * * 1 - if components match + * * 0 - otherwise + */ +static int mei_late_bind_component_match(struct device *dev, int subcompon= ent, + void *data) +{ + struct device *base =3D data; + struct pci_dev *pdev; + + if (!dev) + return 0; + + if (!dev_is_pci(dev)) + return 0; + + pdev =3D to_pci_dev(dev); + + if (pdev->vendor !=3D PCI_VENDOR_ID_INTEL) + return 0; + + if (pdev->class !=3D (PCI_CLASS_DISPLAY_VGA << 8) && + pdev->class !=3D (PCI_CLASS_DISPLAY_OTHER << 8)) + return 0; + + if (subcomponent !=3D INTEL_COMPONENT_LATE_BIND) + return 0; + + base =3D base->parent; + if (!base) /* mei device */ + return 0; + + base =3D base->parent; /* pci device */ + + return !!base && dev =3D=3D base; +} + +static int mei_late_bind_probe(struct mei_cl_device *cldev, + const struct mei_cl_device_id *id) +{ + struct component_match *master_match =3D NULL; + int ret; + + component_match_add_typed(&cldev->dev, &master_match, + mei_late_bind_component_match, &cldev->dev); + if (IS_ERR_OR_NULL(master_match)) + return -ENOMEM; + + ret =3D component_master_add_with_match(&cldev->dev, + &mei_component_master_ops, + master_match); + if (ret < 0) + dev_err(&cldev->dev, "Master comp add failed %d\n", ret); + + return ret; +} + +static void mei_late_bind_remove(struct mei_cl_device *cldev) +{ + component_master_del(&cldev->dev, &mei_component_master_ops); +} + +#define MEI_GUID_MKHI UUID_LE(0xe2c2afa2, 0x3817, 0x4d19, \ + 0x9d, 0x95, 0x6, 0xb1, 0x6b, 0x58, 0x8a, 0x5d) + +static struct mei_cl_device_id mei_late_bind_tbl[] =3D { + { .uuid =3D MEI_GUID_MKHI, .version =3D MEI_CL_VERSION_ANY }, + { } +}; +MODULE_DEVICE_TABLE(mei, mei_late_bind_tbl); + +static struct mei_cl_driver mei_late_bind_driver =3D { + .id_table =3D mei_late_bind_tbl, + .name =3D KBUILD_MODNAME, + .probe =3D mei_late_bind_probe, + .remove =3D mei_late_bind_remove, +}; + +module_mei_cl_driver(mei_late_bind_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MEI Late Binding"); diff --git a/include/drm/intel/i915_component.h b/include/drm/intel/i915_co= mponent.h index 4ea3b17aa143..456849a97d75 100644 --- a/include/drm/intel/i915_component.h +++ b/include/drm/intel/i915_component.h @@ -31,6 +31,7 @@ enum i915_component_type { I915_COMPONENT_HDCP, I915_COMPONENT_PXP, I915_COMPONENT_GSC_PROXY, + INTEL_COMPONENT_LATE_BIND, }; =20 /* MAX_PORT is the number of port diff --git a/include/drm/intel/late_bind_mei_interface.h b/include/drm/inte= l/late_bind_mei_interface.h new file mode 100644 index 000000000000..ec58ef1ab4e8 --- /dev/null +++ b/include/drm/intel/late_bind_mei_interface.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2025 Intel Corporation + */ + +#ifndef _LATE_BIND_MEI_INTERFACE_H_ +#define _LATE_BIND_MEI_INTERFACE_H_ + +#include + +struct device; +struct module; + +/** + * Late Binding flags + * Persistent across warm reset + */ +#define CSC_LATE_BINDING_FLAGS_IS_PERSISTENT BIT(0) + +/** + * xe_late_bind_fw_type - enum to determine late binding fw type + */ +enum late_bind_type { + CSC_LATE_BINDING_TYPE_FAN_CONTROL =3D 1, +}; + +/** + * Late Binding payload status + */ +enum csc_late_binding_status { + CSC_LATE_BINDING_STATUS_SUCCESS =3D 0, + CSC_LATE_BINDING_STATUS_4ID_MISMATCH =3D 1, + CSC_LATE_BINDING_STATUS_ARB_FAILURE =3D 2, + CSC_LATE_BINDING_STATUS_GENERAL_ERROR =3D 3, + CSC_LATE_BINDING_STATUS_INVALID_PARAMS =3D 4, + CSC_LATE_BINDING_STATUS_INVALID_SIGNATURE =3D 5, + CSC_LATE_BINDING_STATUS_INVALID_PAYLOAD =3D 6, + CSC_LATE_BINDING_STATUS_TIMEOUT =3D 7, +}; + +/** + * struct late_bind_component_ops - ops for Late Binding services. + * @owner: Module providing the ops + * @push_config: Sends a config to FW. + */ +struct late_bind_component_ops { + struct module *owner; + + /** + * @push_config: Sends a config to FW. + * @dev: device struct corresponding to the mei device + * @type: payload type + * @flags: payload flags + * @payload: payload buffer + * @payload_size: payload buffer size + * + * Return: 0 success, negative errno value on transport failure, + * positive status returned by FW + */ + int (*push_config)(struct device *dev, u32 type, u32 flags, + const void *payload, size_t payload_size); +}; + +#endif /* _LATE_BIND_MEI_INTERFACE_H_ */ --=20 2.34.1 From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4DF52E11B6 for ; Wed, 25 Jun 2025 16:56:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870610; cv=none; b=pUyawEKAXCovO3Ljcx+SIADp2UhQPyIC926eOMZl372Q5ekOlSy7owF+GKLqxdTSCd0xLl6LTiQCjabp9QevxPQxKtcS9TuF0xEQvT7v1LNMX3wA3HDLWwK05aT3vRZyPdCtDZHTBdohHAKnrahDmjdjtbgnvrZGHb0tSGWjX8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870610; c=relaxed/simple; bh=WSdd+0wMaKxB1gskqL6fj4f1WZRwGYLFqpwRz2DQqAY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=l7j7X9psoPt2Xs0eshSOKpR6DmoY8M5jhPnKEZigG9iDZI7vnoDb2AAy4d5s0VaCiaXVEA8u3HzmP8OneeFWFV7lsGZcQJx7G6YT5kvIsL37NpDXZHMYbYCGhDUApZ5Y5hJFOmmudIiyPMNwSvLk4sMkalbUiE1VuoWbxgoMCjE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZsZMs3t9; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZsZMs3t9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870609; x=1782406609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WSdd+0wMaKxB1gskqL6fj4f1WZRwGYLFqpwRz2DQqAY=; b=ZsZMs3t9+QeRSuveGPOA2MrVcmOw0XLR1QlxYJCDcX1uX0VA9SPBl2Ir o5ZdADchtx3R8iDkm0v4jZSWVe4SsU0kOgjXe78bitplaQkWB+oItoeof Nd/uAwFjFSMLEgFbuUPtK5ZEoBbtWLG7YOyT3K3Pn+GNwqDD3SUBPKh+R wLxmfS9xc3pMqRKgDyFohXsOV9MHMo37/QclKDDIoESgGIAzmFO3bGTXN BHp9a5pzgsVEO/TaZYMzTMqe3igC8UvCu3w+Ta1ekU3zeYqd60BbhyayA a8ZbeqXgOIn3ciEyuIhCMOto+apDmVsFcVQffbTq4xhP6TBS+I1MBqhkI Q==; X-CSE-ConnectionGUID: ZVwhVY+pRuKoOJgd2C+QWA== X-CSE-MsgGUID: mV91DPNPRNuqaSn1bqMeJA== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214433" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214433" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:48 -0700 X-CSE-ConnectionGUID: VIXefHuKRmq5+Aaz28S6/w== X-CSE-MsgGUID: 6C9aKNTbS3Odt4y9fq53jQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696650" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:46 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 03/10] drm/xe/xe_late_bind_fw: Introducing xe_late_bind_fw Date: Wed, 25 Jun 2025 22:30:08 +0530 Message-Id: <20250625170015.33912-4-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Introducing xe_late_bind_fw to enable firmware loading for the devices, such as the fan controller, during the driver probe. Typically, firmware for such devices are part of IFWI flash image but can be replaced at probe after OEM tuning. This patch binds mei late binding component to enable firmware loading. v2: - Add devm_add_action_or_reset to remove the component (Daniele) - Add INTEL_MEI_GSC check in xe_late_bind_init() (Daniele) v3: - Fail driver probe if late bind initialization fails, add has_late_bind flag (Daniele) v4: - %S/I915_COMPONENT_LATE_BIND/INTEL_COMPONENT_LATE_BIND/ Reviewed-by: Daniele Ceraolo Spurio Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 5 ++ drivers/gpu/drm/xe/xe_device_types.h | 6 ++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 90 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.h | 15 ++++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 37 +++++++++ drivers/gpu/drm/xe/xe_pci.c | 3 + 7 files changed, 157 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.c create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.h create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw_types.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 7c039caefd00..521547d78fd2 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -76,6 +76,7 @@ xe-y +=3D xe_bb.o \ xe_hw_fence.o \ xe_irq.o \ xe_lrc.o \ + xe_late_bind_fw.o \ xe_migrate.o \ xe_mmio.o \ xe_mocs.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index cd17c1354ab3..584acd63b0d9 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -44,6 +44,7 @@ #include "xe_hw_engine_group.h" #include "xe_hwmon.h" #include "xe_irq.h" +#include "xe_late_bind_fw.h" #include "xe_memirq.h" #include "xe_mmio.h" #include "xe_module.h" @@ -889,6 +890,10 @@ int xe_device_probe(struct xe_device *xe) if (err) return err; =20 + err =3D xe_late_bind_init(&xe->late_bind); + if (err && err !=3D -ENODEV) + return err; + err =3D xe_oa_init(xe); if (err) return err; diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_d= evice_types.h index 6aca4b1a2824..321f9e9a94f6 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -16,6 +16,7 @@ #include "xe_devcoredump_types.h" #include "xe_heci_gsc.h" #include "xe_lmtt_types.h" +#include "xe_late_bind_fw_types.h" #include "xe_memirq_types.h" #include "xe_oa_types.h" #include "xe_platform_types.h" @@ -323,6 +324,8 @@ struct xe_device { u8 has_heci_cscfi:1; /** @info.has_heci_gscfi: device has heci gscfi */ u8 has_heci_gscfi:1; + /** @info.has_late_bind: Device has firmware late binding support */ + u8 has_late_bind:1; /** @info.has_llc: Device has a shared CPU+GPU last level cache */ u8 has_llc:1; /** @info.has_mbx_power_limits: Device has support to manage power limit= s using @@ -555,6 +558,9 @@ struct xe_device { /** @nvm: discrete graphics non-volatile memory */ struct intel_dg_nvm_dev *nvm; =20 + /** @late_bind: xe mei late bind interface */ + struct xe_late_bind late_bind; + /** @oa: oa observation subsystem */ struct xe_oa oa; =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c new file mode 100644 index 000000000000..eaf12cfec848 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#include +#include + +#include +#include +#include +#include + +#include "xe_device.h" +#include "xe_late_bind_fw.h" + +static struct xe_device * +late_bind_to_xe(struct xe_late_bind *late_bind) +{ + return container_of(late_bind, struct xe_device, late_bind); +} + +static int xe_late_bind_component_bind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + mutex_lock(&late_bind->mutex); + late_bind->component.ops =3D data; + late_bind->component.mei_dev =3D mei_kdev; + mutex_unlock(&late_bind->mutex); + + return 0; +} + +static void xe_late_bind_component_unbind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + mutex_lock(&late_bind->mutex); + late_bind->component.ops =3D NULL; + mutex_unlock(&late_bind->mutex); +} + +static const struct component_ops xe_late_bind_component_ops =3D { + .bind =3D xe_late_bind_component_bind, + .unbind =3D xe_late_bind_component_unbind, +}; + +static void xe_late_bind_remove(void *arg) +{ + struct xe_late_bind *late_bind =3D arg; + struct xe_device *xe =3D late_bind_to_xe(late_bind); + + component_del(xe->drm.dev, &xe_late_bind_component_ops); + mutex_destroy(&late_bind->mutex); +} + +/** + * xe_late_bind_init() - add xe mei late binding component + * + * Return: 0 if the initialization was successful, a negative errno otherw= ise. + */ +int xe_late_bind_init(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + int err; + + if (!xe->info.has_late_bind) + return 0; + + mutex_init(&late_bind->mutex); + + if (!IS_ENABLED(CONFIG_INTEL_MEI_LATE_BIND) || !IS_ENABLED(CONFIG_INTEL_M= EI_GSC)) { + drm_info(&xe->drm, "Can't init xe mei late bind missing mei component\n"= ); + return -ENODEV; + } + + err =3D component_add_typed(xe->drm.dev, &xe_late_bind_component_ops, + INTEL_COMPONENT_LATE_BIND); + if (err < 0) { + drm_info(&xe->drm, "Failed to add mei late bind component (%pe)\n", ERR_= PTR(err)); + return err; + } + + return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); +} diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h new file mode 100644 index 000000000000..4c73571c3e62 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_FW_H_ +#define _XE_LATE_BIND_FW_H_ + +#include + +struct xe_late_bind; + +int xe_late_bind_init(struct xe_late_bind *late_bind); + +#endif diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h new file mode 100644 index 000000000000..1156ef94f0d5 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_TYPES_H_ +#define _XE_LATE_BIND_TYPES_H_ + +#include +#include +#include + +/** + * struct xe_late_bind_component - Late Binding services component + * @mei_dev: device that provide Late Binding service. + * @ops: Ops implemented by Late Binding driver, used by Xe driver. + * + * Communication between Xe and MEI drivers for Late Binding services + */ +struct xe_late_bind_component { + /** @late_bind_component.mei_dev: mei device */ + struct device *mei_dev; + /** @late_bind_component.ops: late binding ops */ + const struct late_bind_component_ops *ops; +}; + +/** + * struct xe_late_bind + */ +struct xe_late_bind { + /** @late_bind.component: struct for communication with mei component */ + struct xe_late_bind_component component; + /** @late_bind.mutex: protects the component binding and usage */ + struct mutex mutex; +}; + +#endif diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 08e21d4099e0..e5018d3ae74f 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -66,6 +66,7 @@ struct xe_device_desc { u8 has_gsc_nvm:1; u8 has_heci_gscfi:1; u8 has_heci_cscfi:1; + u8 has_late_bind:1; u8 has_llc:1; u8 has_mbx_power_limits:1; u8 has_pxp:1; @@ -355,6 +356,7 @@ static const struct xe_device_desc bmg_desc =3D { .has_mbx_power_limits =3D true, .has_gsc_nvm =3D 1, .has_heci_cscfi =3D 1, + .has_late_bind =3D true, .needs_scratch =3D true, }; =20 @@ -600,6 +602,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.has_gsc_nvm =3D desc->has_gsc_nvm; xe->info.has_heci_gscfi =3D desc->has_heci_gscfi; xe->info.has_heci_cscfi =3D desc->has_heci_cscfi; + xe->info.has_late_bind =3D desc->has_late_bind; xe->info.has_llc =3D desc->has_llc; xe->info.has_pxp =3D desc->has_pxp; xe->info.has_sriov =3D desc->has_sriov; --=20 2.34.1 From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65E492E2EF7 for ; Wed, 25 Jun 2025 16:56:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870613; cv=none; b=in9sa48cb50w4Xj2HhxlHYyXjMyRbA9/koBgbw7o45QR05frk7B1eoRjmhc8WvG1l8sNnm1qdd1+HE3lw39zdxsS+4AWJNwuyNedu6P+zP1I3JCia8HJoSIbY2e8iGllPsK64gvnOV1SwNk2aktuLAImCVRRXBFfNicv5ZIq4+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870613; c=relaxed/simple; bh=b05ZVjVFcGj8/6Dj2U8ICCmzegztoCzQ0DKGAvKJRRc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GHVrK9UuTSR31zSzFKNVYM1mrAOhIs4po/tzN64c7ePwEhi3Byh37f9+XpOWQAgZL8sgPT+Fp4uzXu1Kty3JfSDHd/kjMYlCfwjGTa4WkV7i2dpbklw87ijLn07afeZ0oI47aXUBGhMPua4O1Rndav9HU865SbTz+9ITqQOItGw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UvD7JoZW; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UvD7JoZW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870611; x=1782406611; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b05ZVjVFcGj8/6Dj2U8ICCmzegztoCzQ0DKGAvKJRRc=; b=UvD7JoZWF7duuM2lgitNUAELtbi5bGvhwUnJ8cSx2fuH4s4//Z97M6F7 l9/R7N4unlirBVoPHqql6rYBsanMB17+KmjEYYJDA+K+3YQuXIpvXi3ly UqdeJG/+Qprqo/PR7TdVQlPLIzpoQ8N+9tMr7j4B91Av10nwsNysA6/zU ORyFn713GWBF/YqRQFtOZ+F3FnXGShjW2BVmFXDEAx2U7TmkVg054NcAa B2XUPaHWlGWhnmqKttE6CArmsiEoi3HZWWNIQ3gtxuDVKGpwqT7HEI3D8 s3rExMG0Fxt0v122S/y5y8teKrX5YC6EjzP5rz5/uQ+clmuVnfxnfa6wR A==; X-CSE-ConnectionGUID: 4MRsRIPdReO+wVoinRGitQ== X-CSE-MsgGUID: RTOh6+W+Qs+K6vAlvo1Ztg== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214441" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214441" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:51 -0700 X-CSE-ConnectionGUID: S18CtYjiSe2wuVHx30Arsw== X-CSE-MsgGUID: oFEPs+yGQnuxtu/or0wzVw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696667" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:48 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 04/10] drm/xe/xe_late_bind_fw: Initialize late binding firmware Date: Wed, 25 Jun 2025 22:30:09 +0530 Message-Id: <20250625170015.33912-5-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Search for late binding firmware binaries and populate the meta data of firmware structures. v2 (Daniele): - drm_err if firmware size is more than max pay load size - s/request_firmware/firmware_request_nowarn/ as firmware will not be available for all possible cards v3 (Daniele): - init firmware from within xe_late_bind_init, propagate error - switch late_bind_fw to array to handle multiple firmware types v4 (Daniele): - Alloc payload dynamically, fix nits Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 103 ++++++++++++++++++++- drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 32 +++++++ 2 files changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index eaf12cfec848..32d1436e7191 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -5,6 +5,7 @@ =20 #include #include +#include =20 #include #include @@ -13,6 +14,16 @@ =20 #include "xe_device.h" #include "xe_late_bind_fw.h" +#include "xe_pcode.h" +#include "xe_pcode_api.h" + +static const u32 fw_id_to_type[] =3D { + [XE_LB_FW_FAN_CONTROL] =3D CSC_LATE_BINDING_TYPE_FAN_CONTROL, + }; + +static const char * const fw_id_to_name[] =3D { + [XE_LB_FW_FAN_CONTROL] =3D "fan_control", + }; =20 static struct xe_device * late_bind_to_xe(struct xe_late_bind *late_bind) @@ -20,6 +31,92 @@ late_bind_to_xe(struct xe_late_bind *late_bind) return container_of(late_bind, struct xe_device, late_bind); } =20 +static int xe_late_bind_fw_num_fans(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct xe_tile *root_tile =3D xe_device_get_root_tile(xe); + u32 uval; + + if (!xe_pcode_read(root_tile, + PCODE_MBOX(FAN_SPEED_CONTROL, FSC_READ_NUM_FANS, 0), &uval, NULL)) + return uval; + else + return 0; +} + +static int __xe_late_bind_fw_init(struct xe_late_bind *late_bind, u32 fw_i= d) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); + struct xe_late_bind_fw *lb_fw; + const struct firmware *fw; + u32 num_fans; + int ret; + + if (fw_id >=3D XE_LB_FW_MAX_ID) + return -EINVAL; + + lb_fw =3D &late_bind->late_bind_fw[fw_id]; + + lb_fw->valid =3D false; + lb_fw->id =3D fw_id; + lb_fw->type =3D fw_id_to_type[lb_fw->id]; + lb_fw->flags &=3D ~CSC_LATE_BINDING_FLAGS_IS_PERSISTENT; + + if (lb_fw->type =3D=3D CSC_LATE_BINDING_TYPE_FAN_CONTROL) { + num_fans =3D xe_late_bind_fw_num_fans(late_bind); + drm_dbg(&xe->drm, "Number of Fans: %d\n", num_fans); + if (!num_fans) + return 0; + } + + snprintf(lb_fw->blob_path, sizeof(lb_fw->blob_path), "xe/%s_8086_%04x_%04= x_%04x.bin", + fw_id_to_name[lb_fw->id], pdev->device, + pdev->subsystem_vendor, pdev->subsystem_device); + + drm_dbg(&xe->drm, "Request late binding firmware %s\n", lb_fw->blob_path); + ret =3D firmware_request_nowarn(&fw, lb_fw->blob_path, xe->drm.dev); + if (ret) { + drm_dbg(&xe->drm, "%s late binding fw not available for current device", + fw_id_to_name[lb_fw->id]); + return 0; + } + + if (fw->size > MAX_PAYLOAD_SIZE) { + drm_err(&xe->drm, "Firmware %s size %zu is larger than max pay load size= %u\n", + lb_fw->blob_path, fw->size, MAX_PAYLOAD_SIZE); + release_firmware(fw); + return -ENODATA; + } + + lb_fw->payload =3D drmm_kzalloc(&xe->drm, lb_fw->payload_size, GFP_KERNEL= ); + if (!lb_fw->payload) { + release_firmware(fw); + return -ENOMEM; + } + + lb_fw->payload_size =3D fw->size; + + memcpy(lb_fw->payload, fw->data, lb_fw->payload_size); + release_firmware(fw); + lb_fw->valid =3D true; + + return 0; +} + +static int xe_late_bind_fw_init(struct xe_late_bind *late_bind) +{ + int ret; + int fw_id; + + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { + ret =3D __xe_late_bind_fw_init(late_bind, fw_id); + if (ret) + return ret; + } + return 0; +} + static int xe_late_bind_component_bind(struct device *xe_kdev, struct device *mei_kdev, void *data) { @@ -86,5 +183,9 @@ int xe_late_bind_init(struct xe_late_bind *late_bind) return err; } =20 - return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); + err =3D devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_b= ind); + if (err) + return err; + + return xe_late_bind_fw_init(late_bind); } diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index 1156ef94f0d5..93abf4c51789 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -10,6 +10,36 @@ #include #include =20 +#define MAX_PAYLOAD_SIZE SZ_4K + +/** + * xe_late_bind_fw_id - enum to determine late binding fw index + */ +enum xe_late_bind_fw_id { + XE_LB_FW_FAN_CONTROL =3D 0, + XE_LB_FW_MAX_ID +}; + +/** + * struct xe_late_bind_fw + */ +struct xe_late_bind_fw { + /** @late_bind_fw.valid: to check if fw is valid */ + bool valid; + /** @late_bind_fw.id: firmware index */ + u32 id; + /** @late_bind_fw.blob_path: firmware binary path */ + char blob_path[PATH_MAX]; + /** @late_bind_fw.type: firmware type */ + u32 type; + /** @late_bind_fw.flags: firmware flags */ + u32 flags; + /** @late_bind_fw.payload: to store the late binding blob */ + u8 *payload; + /** @late_bind_fw.payload_size: late binding blob payload_size */ + size_t payload_size; +}; + /** * struct xe_late_bind_component - Late Binding services component * @mei_dev: device that provide Late Binding service. @@ -32,6 +62,8 @@ struct xe_late_bind { struct xe_late_bind_component component; /** @late_bind.mutex: protects the component binding and usage */ struct mutex mutex; + /** @late_bind.late_bind_fw: late binding firmware array */ + struct xe_late_bind_fw late_bind_fw[XE_LB_FW_MAX_ID]; }; =20 #endif --=20 2.34.1 From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CD3A2E4277 for ; Wed, 25 Jun 2025 16:56:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870616; cv=none; b=oHHI2pVZlFG3Sm6r9rUqSHall6c93URI/XF1RI1t5c+3Qoaga9oLJuq+ht3VcfkxsdtYzE1Kcni4ZTmUkOE6rfRA2ndUT3HoWUSLrNq7DDb9CU79hpaagZJUPsObgyZjIV/LS19hExU/8iTx72uNoqgo2Gu8dOtZ4/UqQlJbc+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870616; c=relaxed/simple; bh=AiSI8AVc1MXjINywV8uTfK1b5aynNgH+KC95fVu8pdM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kTKHacct+X8PifAuNLeY1TOElSR1pwq5qvgGXx54CltI7HTKT9tSa3Qs2CgXBMjFxEHM7e9V/mrPgdVRyvgmRrwusBcQC9lFtsuhwl60nMsLOuUwC4LEIipUasMRqiKBxrHwYW8EbSExM10uYnCTktoolYio0eJxXAv4neghzCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A04Bd6qa; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A04Bd6qa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870614; x=1782406614; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AiSI8AVc1MXjINywV8uTfK1b5aynNgH+KC95fVu8pdM=; b=A04Bd6qahlYFXtFDLRQjSecvba0q3iiu3Ymv8MU6ExpBQrG8IfTGDiEe C0nvVlWhEbCjpAMb1vkOnE8IWgTPKSoZ0wnuS0vsoISbwsatfdcEXWCC0 PRqKf2ASStCFwfhVBeGwBaP0XWj5Fx1RIEUjhc8UZWA59TEuIvwsEsSIR gnp1Jtwh4idn0LFhEilHSbw4wzGS5bGcsg56fOsPYn7tFSd3T/NoDPLi0 fLKEQOa8HfnILc7piVCxfh8NpOu1rEh1zOtQaihFspj60PReJXRUokEmb 5R6lvE/0YJr8RI+GZapR9LejPlC1OeEwWJVKPB0FsikE4hzEljEJKTKJ7 w==; X-CSE-ConnectionGUID: p/4//AqxRSukgfabYxZ8rw== X-CSE-MsgGUID: INFdYdLJTl6N4ybls9lJrw== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214446" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214446" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:54 -0700 X-CSE-ConnectionGUID: sCIa9UlHRCugN+fuxQzlXQ== X-CSE-MsgGUID: rAowFTfHREeEulha8LroDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696680" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:51 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 05/10] drm/xe/xe_late_bind_fw: Load late binding firmware Date: Wed, 25 Jun 2025 22:30:10 +0530 Message-Id: <20250625170015.33912-6-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Load late binding firmware v2: - s/EAGAIN/EBUSY/ - Flush worker in suspend and driver unload (Daniele) v3: - Use retry interval of 6s, in steps of 200ms, to allow other OS components release MEI CL handle (Sasha) v4: - return -ENODEV if component not added (Daniele) - parse and print status returned by csc - Use xe_pm_get_if_in_active (Daniele) Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 149 ++++++++++++++++++++- drivers/gpu/drm/xe/xe_late_bind_fw.h | 1 + drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 7 + 3 files changed, 156 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 32d1436e7191..52243063d98a 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -16,6 +16,20 @@ #include "xe_late_bind_fw.h" #include "xe_pcode.h" #include "xe_pcode_api.h" +#include "xe_pm.h" + +/* + * The component should load quite quickly in most cases, but it could take + * a bit. Using a very big timeout just to cover the worst case scenario + */ +#define LB_INIT_TIMEOUT_MS 20000 + +/* + * Retry interval set to 6 seconds, in steps of 200 ms, to allow time for + * other OS components to release the MEI CL handle + */ +#define LB_FW_LOAD_RETRY_MAXCOUNT 30 +#define LB_FW_LOAD_RETRY_PAUSE_MS 200 =20 static const u32 fw_id_to_type[] =3D { [XE_LB_FW_FAN_CONTROL] =3D CSC_LATE_BINDING_TYPE_FAN_CONTROL, @@ -31,6 +45,30 @@ late_bind_to_xe(struct xe_late_bind *late_bind) return container_of(late_bind, struct xe_device, late_bind); } =20 +static const char *xe_late_bind_parse_status(uint32_t status) +{ + switch (status) { + case CSC_LATE_BINDING_STATUS_SUCCESS: + return "success"; + case CSC_LATE_BINDING_STATUS_4ID_MISMATCH: + return "4Id Mismatch"; + case CSC_LATE_BINDING_STATUS_ARB_FAILURE: + return "ARB Failure"; + case CSC_LATE_BINDING_STATUS_GENERAL_ERROR: + return "General Error"; + case CSC_LATE_BINDING_STATUS_INVALID_PARAMS: + return "Invalid Params"; + case CSC_LATE_BINDING_STATUS_INVALID_SIGNATURE: + return "Invalid Signature"; + case CSC_LATE_BINDING_STATUS_INVALID_PAYLOAD: + return "Invalid Payload"; + case CSC_LATE_BINDING_STATUS_TIMEOUT: + return "Timeout"; + default: + return "Unknown error"; + } +} + static int xe_late_bind_fw_num_fans(struct xe_late_bind *late_bind) { struct xe_device *xe =3D late_bind_to_xe(late_bind); @@ -44,6 +82,93 @@ static int xe_late_bind_fw_num_fans(struct xe_late_bind = *late_bind) return 0; } =20 +static void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *l= ate_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct xe_late_bind_fw *lbfw; + int fw_id; + + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { + lbfw =3D &late_bind->late_bind_fw[fw_id]; + if (lbfw->valid && late_bind->wq) { + drm_dbg(&xe->drm, "Flush work: load %s firmware\n", + fw_id_to_name[lbfw->id]); + flush_work(&lbfw->work); + } + } +} + +static void xe_late_bind_work(struct work_struct *work) +{ + struct xe_late_bind_fw *lbfw =3D container_of(work, struct xe_late_bind_f= w, work); + struct xe_late_bind *late_bind =3D container_of(lbfw, struct xe_late_bind, + late_bind_fw[lbfw->id]); + struct xe_device *xe =3D late_bind_to_xe(late_bind); + int retry =3D LB_FW_LOAD_RETRY_MAXCOUNT; + int ret; + int slept; + + /* we can queue this before the component is bound */ + for (slept =3D 0; slept < LB_INIT_TIMEOUT_MS; slept +=3D 100) { + if (late_bind->component.ops) + break; + msleep(100); + } + + if (!xe_pm_runtime_get_if_active(xe)) + return; + + mutex_lock(&late_bind->mutex); + + if (!late_bind->component.ops) { + drm_err(&xe->drm, "Late bind component not bound\n"); + goto out; + } + + drm_dbg(&xe->drm, "Load %s firmware\n", fw_id_to_name[lbfw->id]); + + do { + ret =3D late_bind->component.ops->push_config(late_bind->component.mei_d= ev, + lbfw->type, lbfw->flags, + lbfw->payload, lbfw->payload_size); + if (!ret) + break; + msleep(LB_FW_LOAD_RETRY_PAUSE_MS); + } while (--retry && ret =3D=3D -EBUSY); + + if (!ret) { + drm_dbg(&xe->drm, "Load %s firmware successful\n", + fw_id_to_name[lbfw->id]); + goto out; + } + + if (ret > 0) + drm_err(&xe->drm, "Load %s firmware failed with err %d, %s\n", + fw_id_to_name[lbfw->id], ret, xe_late_bind_parse_status(ret)); + else + drm_err(&xe->drm, "Load %s firmware failed with err %d", + fw_id_to_name[lbfw->id], ret); +out: + mutex_unlock(&late_bind->mutex); + xe_pm_runtime_put(xe); +} + +int xe_late_bind_fw_load(struct xe_late_bind *late_bind) +{ + struct xe_late_bind_fw *lbfw; + int fw_id; + + if (!late_bind->component_added) + return -ENODEV; + + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { + lbfw =3D &late_bind->late_bind_fw[fw_id]; + if (lbfw->valid) + queue_work(late_bind->wq, &lbfw->work); + } + return 0; +} + static int __xe_late_bind_fw_init(struct xe_late_bind *late_bind, u32 fw_i= d) { struct xe_device *xe =3D late_bind_to_xe(late_bind); @@ -99,6 +224,7 @@ static int __xe_late_bind_fw_init(struct xe_late_bind *l= ate_bind, u32 fw_id) =20 memcpy(lb_fw->payload, fw->data, lb_fw->payload_size); release_firmware(fw); + INIT_WORK(&lb_fw->work, xe_late_bind_work); lb_fw->valid =3D true; =20 return 0; @@ -109,11 +235,16 @@ static int xe_late_bind_fw_init(struct xe_late_bind *= late_bind) int ret; int fw_id; =20 + late_bind->wq =3D alloc_ordered_workqueue("late-bind-ordered-wq", 0); + if (!late_bind->wq) + return -ENOMEM; + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { ret =3D __xe_late_bind_fw_init(late_bind, fw_id); if (ret) return ret; } + return 0; } =20 @@ -137,6 +268,8 @@ static void xe_late_bind_component_unbind(struct device= *xe_kdev, struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); struct xe_late_bind *late_bind =3D &xe->late_bind; =20 + xe_late_bind_wait_for_worker_completion(late_bind); + mutex_lock(&late_bind->mutex); late_bind->component.ops =3D NULL; mutex_unlock(&late_bind->mutex); @@ -152,7 +285,15 @@ static void xe_late_bind_remove(void *arg) struct xe_late_bind *late_bind =3D arg; struct xe_device *xe =3D late_bind_to_xe(late_bind); =20 + xe_late_bind_wait_for_worker_completion(late_bind); + + late_bind->component_added =3D false; + component_del(xe->drm.dev, &xe_late_bind_component_ops); + if (late_bind->wq) { + destroy_workqueue(late_bind->wq); + late_bind->wq =3D NULL; + } mutex_destroy(&late_bind->mutex); } =20 @@ -183,9 +324,15 @@ int xe_late_bind_init(struct xe_late_bind *late_bind) return err; } =20 + late_bind->component_added =3D true; + err =3D devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_b= ind); if (err) return err; =20 - return xe_late_bind_fw_init(late_bind); + err =3D xe_late_bind_fw_init(late_bind); + if (err) + return err; + + return xe_late_bind_fw_load(late_bind); } diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h index 4c73571c3e62..28d56ed2bfdc 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -11,5 +11,6 @@ struct xe_late_bind; =20 int xe_late_bind_init(struct xe_late_bind *late_bind); +int xe_late_bind_fw_load(struct xe_late_bind *late_bind); =20 #endif diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index 93abf4c51789..f119a75f4c9c 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -9,6 +9,7 @@ #include #include #include +#include =20 #define MAX_PAYLOAD_SIZE SZ_4K =20 @@ -38,6 +39,8 @@ struct xe_late_bind_fw { u8 *payload; /** @late_bind_fw.payload_size: late binding blob payload_size */ size_t payload_size; + /** @late_bind_fw.work: worker to upload latebind blob */ + struct work_struct work; }; =20 /** @@ -64,6 +67,10 @@ struct xe_late_bind { struct mutex mutex; /** @late_bind.late_bind_fw: late binding firmware array */ struct xe_late_bind_fw late_bind_fw[XE_LB_FW_MAX_ID]; + /** @late_bind.wq: workqueue to submit request to download late bind blob= */ + struct workqueue_struct *wq; + /** @late_bind.component_added: whether the component has been added */ + bool component_added; }; =20 #endif --=20 2.34.1 From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEE642EACFB for ; Wed, 25 Jun 2025 16:56:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870618; cv=none; b=FgZvpTRKqlv4CemKlZTWk+TvHtGosbJTqsYpKoLBlYKq4Rae55uRhoT0p5nizhKo/cDO0k/jgQrCfotw5sAFtmORXmTnYQTQ6wvhc8wZG5eOGVdjmaF4lzKKWnK5T4zBO11JOPsefePDu1T8dnTtNDU6B5sCqnM+Rndkh1rJEEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870618; c=relaxed/simple; bh=E72XAmwLEXP/cIfDQ5XSxKLgy7353qIEmfUuR7ydBVY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XXmY5bvkCDyobdfzsWyF2kTaUiB5B1skW6y/ftRYyTp9uq1sSWVBMNZoKOgz1VTSATnVeHvkw5KW/NfYhcytbk1DLCyE7AiBHJ5xBtlXi2dnnEruCSaNk5U7TK96Wby38/cnBbMHZ76LRpaq9+iwaq5Y/LvMhMp/VcI14QuW+GA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ewEYtxLU; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ewEYtxLU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870617; x=1782406617; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E72XAmwLEXP/cIfDQ5XSxKLgy7353qIEmfUuR7ydBVY=; b=ewEYtxLUFy2VK8NYZEAu2K7vr6o7uWUbqKHRYH8jPvfNuBEzQyxPVHmd tEHMFj7lvcV5CyDRcZZc4T1t/4brPlpGiGWY0AJqbx6FwXT/hsOFj+5r6 s58sH9P2vPVbQNAnffmoraZjvuq8t2KprdTrMNbKMwSW9CBDeKFUWqSd4 QgFsHbd8MuISR4Ylip2t6HlO7bNutzGyTkNXMNRYfU8vSWLqsJpKRHYzg /PuW4tfpE9lTgmHy0xAxrn7klrANIr+YSZGNWqwpO5aNnV1uVN2c/cipW bw085evX9gHs2rYjBh/jsTTb3l15o24Xl8/n2Q0B7c6UxUfORs/NMaDUa g==; X-CSE-ConnectionGUID: MSL2/gErTX+cBbA5FLS15w== X-CSE-MsgGUID: BbIyne4hRmuIRuN09tn5YA== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214453" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214453" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:56 -0700 X-CSE-ConnectionGUID: 3uBLudaDRKmk2vQH8jnnpw== X-CSE-MsgGUID: VC4Q+YAtSg+EZyqY7EcukA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696699" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:54 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 06/10] drm/xe/xe_late_bind_fw: Reload late binding fw in rpm resume Date: Wed, 25 Jun 2025 22:30:11 +0530 Message-Id: <20250625170015.33912-7-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reload late binding fw during runtime resume. v2: Flush worker during runtime suspend Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 2 +- drivers/gpu/drm/xe/xe_late_bind_fw.h | 1 + drivers/gpu/drm/xe/xe_pm.c | 6 ++++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 52243063d98a..737780336000 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -82,7 +82,7 @@ static int xe_late_bind_fw_num_fans(struct xe_late_bind *= late_bind) return 0; } =20 -static void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *l= ate_bind) +void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *late_bin= d) { struct xe_device *xe =3D late_bind_to_xe(late_bind); struct xe_late_bind_fw *lbfw; diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h index 28d56ed2bfdc..07e437390539 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -12,5 +12,6 @@ struct xe_late_bind; =20 int xe_late_bind_init(struct xe_late_bind *late_bind); int xe_late_bind_fw_load(struct xe_late_bind *late_bind); +void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *late_bin= d); =20 #endif diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index ff749edc005b..91923fd4af80 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -20,6 +20,7 @@ #include "xe_gt.h" #include "xe_guc.h" #include "xe_irq.h" +#include "xe_late_bind_fw.h" #include "xe_pcode.h" #include "xe_pxp.h" #include "xe_trace.h" @@ -460,6 +461,8 @@ int xe_pm_runtime_suspend(struct xe_device *xe) if (err) goto out; =20 + xe_late_bind_wait_for_worker_completion(&xe->late_bind); + /* * Applying lock for entire list op as xe_ttm_bo_destroy and xe_bo_move_n= otify * also checks and deletes bo entry from user fault list. @@ -550,6 +553,9 @@ int xe_pm_runtime_resume(struct xe_device *xe) =20 xe_pxp_pm_resume(xe->pxp); =20 + if (xe->d3cold.allowed) + xe_late_bind_fw_load(&xe->late_bind); + out: xe_rpm_lockmap_release(xe); xe_pm_write_callback_task(xe, NULL); --=20 2.34.1 From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72A952EACF4 for ; Wed, 25 Jun 2025 16:56:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870620; cv=none; b=VgI7Q1lTWgEIZzd42cqM6q0yZrUJaUPNCD7CxFmme+1b95yYJwnx456F96vobeQea2CZpcorVf9n5E7RrVzepUhTXGaWfcQSymQN1pfDA20eFVA/GlD90vrV1pGAlJg+x6b/nmZA3B+13kFVVNDhZtzyfJTeP0FZepvj0PsOBz8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870620; c=relaxed/simple; bh=KOQQsCoE0oqkeAm/Y0aoPQ+O5D3xfSmk4KxH6jeeGRY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BNAxUSyT2aixrpP4Ap2j3StmooqEkWkqkEbu1a89xQ+7ijWMydLiomLswSm7Yofpu54KjpfK/1DVktn6RCbutv95AhXddMcWig9Jd9rsGVMtCvLVztBTO3TWWvVmXSH96/l3KWiBc4bWzx0Xa8ZiHFhERX/rgkY3r/jAD7PShEY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lEE6cOH3; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lEE6cOH3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870619; x=1782406619; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KOQQsCoE0oqkeAm/Y0aoPQ+O5D3xfSmk4KxH6jeeGRY=; b=lEE6cOH3VtYlMZK8lCmPvrT2wxKKIOqnc1G0NKeKFBUCza8L8Dx2qop7 z2MfVs1JkMT8D6/ty5jFU0J9t/UeRwmZsCLlH4ZNiiO3vxPXiROJcSyee BnGBUQBZv6MlkIM+Qflq/CIplqxp7/dWV9THVB5dSJcDKKVaDy1e1SqYj be2LWvGQ5JdPDfrvWO7lQ48O+JSZfjfrsXg+pVjQ3ZyRqDgMu2LnocY8w L7BK3w/zLC5cg5hpboSkM3x8eq7PI1jsbywR5tfMMtpcC1VDliP7aoro1 oOpYpE89Ywae7aqhUJPP+Tr4vOoo2Mk8W96k9YvX//xRJGPCagqsc1LyJ g==; X-CSE-ConnectionGUID: 4/UH5f2gR9+lUg1uyrriQw== X-CSE-MsgGUID: PkoeotfeTsO1oEcurrplgg== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214457" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214457" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:59 -0700 X-CSE-ConnectionGUID: 6xHZ9QIXS+aLcdDHtaz0pg== X-CSE-MsgGUID: gHz9xzKtR1CzDvLpoKgVnQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696709" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:56 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 07/10] drm/xe/xe_late_bind_fw: Reload late binding fw during system resume Date: Wed, 25 Jun 2025 22:30:12 +0530 Message-Id: <20250625170015.33912-8-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reload late binding fw during resume from system suspend v2: - Unconditionally reload late binding fw (Rodrigo) - Flush worker during system suspend Cc: Rodrigo Vivi Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_pm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index 91923fd4af80..f49b7b6eab97 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -127,6 +127,8 @@ int xe_pm_suspend(struct xe_device *xe) if (err) goto err; =20 + xe_late_bind_wait_for_worker_completion(&xe->late_bind); + for_each_gt(gt, xe, id) xe_gt_suspend_prepare(gt); =20 @@ -205,6 +207,8 @@ int xe_pm_resume(struct xe_device *xe) =20 xe_pxp_pm_resume(xe->pxp); =20 + xe_late_bind_fw_load(&xe->late_bind); + drm_dbg(&xe->drm, "Device resumed\n"); return 0; err: --=20 2.34.1 From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EF1F2ECEA3 for ; Wed, 25 Jun 2025 16:57:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870623; cv=none; b=M7dEx6QAsqnjRQVGSTBDdjXA2zeCMhrsrMOPYN7TJXYHtD2BtV0gp8LUqlRuFzvKVMlNsJ0XBZ/ploruYR7QIWZyyfLgiYYphBNAJQI18ei4J/oR8ZyDmOI3wq1KRSUTygJoGewsmT871KpDRD+A6pwzIOAePlZkZ4dHnr+gSKA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870623; c=relaxed/simple; bh=9+b4uaQGDlFPrBTtx9EMuF/EDYS/T1DcqTeYAOsTim8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=s/PoHUDTLkDO4M212PJpqqu5KIbBbISXMkn5T934VUcM7exOcZ4NPzmm6pFdl7LBmW6AUuwk+w0D7QCZDEp1QWKw4ghDpSwiG5c6I6IaQlBUhfbek9QC0LivW96L7wG9G6Jnx887g2zZ52lrqviP4Az9GhDD7V0DCI5Wh/rpKZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VqiPu2N3; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VqiPu2N3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870622; x=1782406622; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9+b4uaQGDlFPrBTtx9EMuF/EDYS/T1DcqTeYAOsTim8=; b=VqiPu2N3IedG+/y6cn+QNnqciQuUv7L21O381KHe3T6rJnVLxdZQUj/2 tt+27UzI1nZ8ZBfEvZTNKuZUiDoymbxoZboh0eVoGdsCPCLkEW0CrCcv0 alskhg9JhA4/3kauwc8Uki3AzlLMdQ3/IgVPT2Km3M1jNYKIOC4nD/Shq s4ryj9cAU13cVMoeSBGe0sMCpNjwsfbXj4F/zjUv4zvyTL/ifU+6LJjsU zQ/g2rd9Kh1/elcFnY5ak8uRv5jAMNasyI10vlINl1+vuuUpeNjWaVRZy CVASD3LDLFIeLuKjRx3pkEYK9gyf1Lmw6BvEQikJAF4BfEwXvN+c89fSx w==; X-CSE-ConnectionGUID: 2osXp3lwRTG2TvB7HXjnmw== X-CSE-MsgGUID: QYOoWjxZTiG3Ukhy7rvIhQ== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214461" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214461" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:57:02 -0700 X-CSE-ConnectionGUID: Rw0h/HxYQNWN2N/OscurxQ== X-CSE-MsgGUID: qGI1XWVBT6OAGIZHJNVw2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696722" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:56:59 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 08/10] drm/xe/xe_late_bind_fw: Introduce debug fs node to disable late binding Date: Wed, 25 Jun 2025 22:30:13 +0530 Message-Id: <20250625170015.33912-9-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a debug filesystem node to disable late binding fw reload during the system or runtime resume. This is intended for situations where the late binding fw needs to be loaded from user mode, perticularly for validation purpose. Note that xe kmd doesn't participate in late binding flow from user space. Binary loaded from the userspace will be lost upon entering to D3 cold hence user space app need to handle this situation. v2: - s/(uval =3D=3D 1) ? true : false/!!uval/ (Daniele) v3: - Refine the commit message (Daniele) Acked-by: Rodrigo Vivi Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_debugfs.c | 41 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 3 ++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 2 ++ 3 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugf= s.c index d83cd6ed3fa8..d1f6f556efa2 100644 --- a/drivers/gpu/drm/xe/xe_debugfs.c +++ b/drivers/gpu/drm/xe/xe_debugfs.c @@ -226,6 +226,44 @@ static const struct file_operations atomic_svm_timesli= ce_ms_fops =3D { .write =3D atomic_svm_timeslice_ms_set, }; =20 +static ssize_t disable_late_binding_show(struct file *f, char __user *ubuf, + size_t size, loff_t *pos) +{ + struct xe_device *xe =3D file_inode(f)->i_private; + struct xe_late_bind *late_bind =3D &xe->late_bind; + char buf[32]; + int len; + + len =3D scnprintf(buf, sizeof(buf), "%d\n", late_bind->disable); + + return simple_read_from_buffer(ubuf, size, pos, buf, len); +} + +static ssize_t disable_late_binding_set(struct file *f, const char __user = *ubuf, + size_t size, loff_t *pos) +{ + struct xe_device *xe =3D file_inode(f)->i_private; + struct xe_late_bind *late_bind =3D &xe->late_bind; + u32 uval; + ssize_t ret; + + ret =3D kstrtouint_from_user(ubuf, size, sizeof(uval), &uval); + if (ret) + return ret; + + if (uval > 1) + return -EINVAL; + + late_bind->disable =3D !!uval; + return size; +} + +static const struct file_operations disable_late_binding_fops =3D { + .owner =3D THIS_MODULE, + .read =3D disable_late_binding_show, + .write =3D disable_late_binding_set, +}; + void xe_debugfs_register(struct xe_device *xe) { struct ttm_device *bdev =3D &xe->ttm; @@ -249,6 +287,9 @@ void xe_debugfs_register(struct xe_device *xe) debugfs_create_file("atomic_svm_timeslice_ms", 0600, root, xe, &atomic_svm_timeslice_ms_fops); =20 + debugfs_create_file("disable_late_binding", 0600, root, xe, + &disable_late_binding_fops); + for (mem_type =3D XE_PL_VRAM0; mem_type <=3D XE_PL_VRAM1; ++mem_type) { man =3D ttm_manager_type(bdev, mem_type); =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 737780336000..777f66692d7f 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -161,6 +161,9 @@ int xe_late_bind_fw_load(struct xe_late_bind *late_bind) if (!late_bind->component_added) return -ENODEV; =20 + if (late_bind->disable) + return 0; + for (fw_id =3D 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) { lbfw =3D &late_bind->late_bind_fw[fw_id]; if (lbfw->valid) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index f119a75f4c9c..16f2bd6bbdf1 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -71,6 +71,8 @@ struct xe_late_bind { struct workqueue_struct *wq; /** @late_bind.component_added: whether the component has been added */ bool component_added; + /** @late_bind.disable to block late binding reload during pm resume flow= */ + bool disable; }; =20 #endif --=20 2.34.1 From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5FF72ED84B for ; Wed, 25 Jun 2025 16:57:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870626; cv=none; b=S23X6s7gKfIZpPsO5PwQ5s+XuuQwXS/Ol35bKlwP0ONaN/8tx5cXCVzG5dfmzRr1w229TPMuJzXBRidDVlbe7K+TrAfhP1iO8uyIGDeaDAUvZdDZ+851I6IfcxuPevu+9EhXgRxYWmtJiOxgdYRnP0/DX5qGQmyE3Yfs2ks9RHQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870626; c=relaxed/simple; bh=a+F4jxb2dusRnbIqNfNGcCnZXqK4rpiF3HdhFrNqR5M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=t1B0j/JfDxmDuuOxG7MaKiK4nQ5N/V41gfvjkvb+GF6ugYL/HP6gkCeHTX6C1kVdRqSO+35+X5itH/TXV+inJekbUAc08vpr5ClzXpg9yg0n101ZsxqOLFJENgN3xLlfVAFAPjjRRzhDxXEjclmNvcN77crPghTYHNS65q2QxAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=foyELBaU; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="foyELBaU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870625; x=1782406625; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=a+F4jxb2dusRnbIqNfNGcCnZXqK4rpiF3HdhFrNqR5M=; b=foyELBaUDFSA37PKQlbqT0O3ehU989n8He5PkX//Rvp32/8MDuXPwjfm g3eTJvKMv1vNEIV5zLzW0YsjYSf5GLpPK6F70JlPrFHDcvVnq9i+vTNeN huLU1TgGLPKawB0S50/vMBuviZP7EHXu+BkT1ar3IoCKEpgX1c60mssJe gsvJyh2gKGY0TGjmVDZ+/YoT7KaK0oOvPQTUajHHcgemD7nugB+ZHSdzc GfHFCQmRAzxMku8LX3IzhsvEiMnhSU30ZoppyWUlnJSaL+Wjr9D/jIPaV xEczjQlWMFFc6HsIyJSSHBcWVSr0JeCk4c5doFycwDjBtACXW05OaGG4i A==; X-CSE-ConnectionGUID: vfO83CZGSJ6I1XxW/taWgA== X-CSE-MsgGUID: Pdd35P7ETauZ2UggMTZEGw== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214464" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214464" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:57:04 -0700 X-CSE-ConnectionGUID: keNnEAGvSMCURzU4Xg9rrw== X-CSE-MsgGUID: BgTuWuyRQBSOctvz6EqQVw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696733" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:57:02 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 09/10] drm/xe/xe_late_bind_fw: Extract and print version info Date: Wed, 25 Jun 2025 22:30:14 +0530 Message-Id: <20250625170015.33912-10-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract and print version info of the late binding binary. v2: Some refinements (Daniele) Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 124 +++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 3 + drivers/gpu/drm/xe/xe_uc_fw_abi.h | 66 +++++++++++ 3 files changed, 193 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 777f66692d7f..253908794d4a 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -45,6 +45,121 @@ late_bind_to_xe(struct xe_late_bind *late_bind) return container_of(late_bind, struct xe_device, late_bind); } =20 +static struct xe_device * +late_bind_fw_to_xe(struct xe_late_bind_fw *lb_fw) +{ + return container_of(lb_fw, struct xe_device, late_bind.late_bind_fw[lb_fw= ->id]); +} + +/* Refer to the "Late Bind based Firmware Layout" documentation entry for = details */ +static int parse_cpd_header(struct xe_late_bind_fw *lb_fw, + const void *data, size_t size, const char *manifest_entry) +{ + struct xe_device *xe =3D late_bind_fw_to_xe(lb_fw); + const struct gsc_cpd_header_v2 *header =3D data; + const struct gsc_manifest_header *manifest; + const struct gsc_cpd_entry *entry; + size_t min_size =3D sizeof(*header); + u32 offset; + int i; + + /* manifest_entry is mandatory */ + xe_assert(xe, manifest_entry); + + if (size < min_size || header->header_marker !=3D GSC_CPD_HEADER_MARKER) + return -ENOENT; + + if (header->header_length < sizeof(struct gsc_cpd_header_v2)) { + drm_err(&xe->drm, "%s late binding fw: Invalid CPD header length %u!\n", + fw_id_to_name[lb_fw->id], header->header_length); + return -EINVAL; + } + + min_size =3D header->header_length + sizeof(struct gsc_cpd_entry) * heade= r->num_of_entries; + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + /* Look for the manifest first */ + entry =3D (void *)header + header->header_length; + for (i =3D 0; i < header->num_of_entries; i++, entry++) + if (strcmp(entry->name, manifest_entry) =3D=3D 0) + offset =3D entry->offset & GSC_CPD_ENTRY_OFFSET_MASK; + + if (!offset) { + drm_err(&xe->drm, "%s late binding fw: Failed to find manifest_entry\n", + fw_id_to_name[lb_fw->id]); + return -ENODATA; + } + + min_size =3D offset + sizeof(struct gsc_manifest_header); + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + manifest =3D data + offset; + + lb_fw->version =3D manifest->fw_version; + + return 0; +} + +/* Refer to the "Late Bind based Firmware Layout" documentation entry for = details */ +static int parse_lb_layout(struct xe_late_bind_fw *lb_fw, + const void *data, size_t size, const char *fpt_entry) +{ + struct xe_device *xe =3D late_bind_fw_to_xe(lb_fw); + const struct csc_fpt_header *header =3D data; + const struct csc_fpt_entry *entry; + size_t min_size =3D sizeof(*header); + u32 offset; + int i; + + /* fpt_entry is mandatory */ + xe_assert(xe, fpt_entry); + + if (size < min_size || header->header_marker !=3D CSC_FPT_HEADER_MARKER) + return -ENOENT; + + if (header->header_length < sizeof(struct csc_fpt_header)) { + drm_err(&xe->drm, "%s late binding fw: Invalid FPT header length %u!\n", + fw_id_to_name[lb_fw->id], header->header_length); + return -EINVAL; + } + + min_size =3D header->header_length + sizeof(struct csc_fpt_entry) * heade= r->num_of_entries; + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + /* Look for the cpd header first */ + entry =3D (void *)header + header->header_length; + for (i =3D 0; i < header->num_of_entries; i++, entry++) + if (strcmp(entry->name, fpt_entry) =3D=3D 0) + offset =3D entry->offset; + + if (!offset) { + drm_err(&xe->drm, "%s late binding fw: Failed to find fpt_entry\n", + fw_id_to_name[lb_fw->id]); + return -ENODATA; + } + + min_size =3D offset + sizeof(struct gsc_cpd_header_v2); + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + return parse_cpd_header(lb_fw, data + offset, size - offset, "LTES.man"); +} + static const char *xe_late_bind_parse_status(uint32_t status) { switch (status) { @@ -217,6 +332,10 @@ static int __xe_late_bind_fw_init(struct xe_late_bind = *late_bind, u32 fw_id) return -ENODATA; } =20 + ret =3D parse_lb_layout(lb_fw, fw->data, fw->size, "LTES"); + if (ret) + return ret; + lb_fw->payload =3D drmm_kzalloc(&xe->drm, lb_fw->payload_size, GFP_KERNEL= ); if (!lb_fw->payload) { release_firmware(fw); @@ -225,6 +344,11 @@ static int __xe_late_bind_fw_init(struct xe_late_bind = *late_bind, u32 fw_id) =20 lb_fw->payload_size =3D fw->size; =20 + drm_info(&xe->drm, "Using %s firmware from %s version %u.%u.%u.%u\n", + fw_id_to_name[lb_fw->id], lb_fw->blob_path, + lb_fw->version.major, lb_fw->version.minor, + lb_fw->version.hotfix, lb_fw->version.build); + memcpy(lb_fw->payload, fw->data, lb_fw->payload_size); release_firmware(fw); INIT_WORK(&lb_fw->work, xe_late_bind_work); diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index 16f2bd6bbdf1..7f98a1380844 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -10,6 +10,7 @@ #include #include #include +#include "xe_uc_fw_abi.h" =20 #define MAX_PAYLOAD_SIZE SZ_4K =20 @@ -41,6 +42,8 @@ struct xe_late_bind_fw { size_t payload_size; /** @late_bind_fw.work: worker to upload latebind blob */ struct work_struct work; + /** @late_bind_fw.version: late binding blob manifest version */ + struct gsc_version version; }; =20 /** diff --git a/drivers/gpu/drm/xe/xe_uc_fw_abi.h b/drivers/gpu/drm/xe/xe_uc_f= w_abi.h index 87ade41209d0..78782d105fa9 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw_abi.h +++ b/drivers/gpu/drm/xe/xe_uc_fw_abi.h @@ -318,4 +318,70 @@ struct gsc_manifest_header { u32 exponent_size; /* in dwords */ } __packed; =20 +/** + * DOC: Late binding Firmware Layout + * + * The Late binding binary starts with FPT header, which contains locations + * of various partitions of the binary. Here we're interested in finding o= ut + * manifest version. To the manifest version, we need to locate CPD header + * one of the entry in CPD header points to manifest header. Manifest head= er + * contains the version. + * + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + * | FPT Header | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + * | FPT entries[] | + * | entry1 | + * | ... | + * | entryX | + * | "LTES" | + * | ... | + * | offset >-----------------------------|------o + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | CPD Header |<-----o + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + * | CPD entries[] | + * | entry1 | + * | ... | + * | entryX | + * | "LTES.man" | + * | ... | + * | offset >----------------------------|------o + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | Manifest Header |<-----o + * | ... | + * | FW version | + * | ... | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + */ + +/* FPT Headers */ +struct csc_fpt_header { + u32 header_marker; +#define CSC_FPT_HEADER_MARKER 0x54504624 + u32 num_of_entries; + u8 header_version; + u8 entry_version; + u8 header_length; /* in bytes */ + u8 flags; + u16 ticks_to_add; + u16 tokens_to_add; + u32 uma_size; + u32 crc32; + struct gsc_version fitc_version; +} __packed; + +struct csc_fpt_entry { + u8 name[4]; /* partition name */ + u32 reserved1; + u32 offset; /* offset from beginning of CSE region */ + u32 length; /* partition length in bytes */ + u32 reserved2[3]; + u32 partition_flags; +} __packed; + #endif --=20 2.34.1 From nobody Wed Oct 8 17:31:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 854402EE26A for ; Wed, 25 Jun 2025 16:57:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870628; cv=none; b=YC1J6NCcgfGVeCkmnpYcfFnBDvmKuKjiv2Jf9tYEvNToDr6JIvfkFdVneiOJuP7XU0BiVxyL+hRvQnIVqLg3gzBk7T78I8CTIiKZcAkEWNlod50ToJrqrFeQIC09ZXOhlZ+1H6Pk4S4nswJPbYjjPknAuuf36B721qeT8Y/22fU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750870628; c=relaxed/simple; bh=wBhqdHFT6q92MdaZKb3oeHHxeJu1lqs/E+7CU/KnemU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rpWaPlNQ2Vv0OB6fPdQQNkTKjX6AU8aWK7P9/+YG1kGtasAnmr5S3HRWWe/qmj+vUH9a+XaS6KlOjM28CKMULVCY6+BuC37GY+0bykXWWxYfnaDXOx++qjORb9H/IzCqL/Hczo0SFKCCVXboAak96Uxu+eyfsl3P3YiB63NsZLE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mNgLB8Ds; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mNgLB8Ds" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750870627; x=1782406627; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wBhqdHFT6q92MdaZKb3oeHHxeJu1lqs/E+7CU/KnemU=; b=mNgLB8Ds2bQQs4PRPvP/CvxKXLcsQqxIgP92RizEQYzIRMyYkTifpe5y gnUgf9FiZql14xEsgCaTePt4Xx1XYaJvzpZ9ULDA1fZdryp/QpnK7DacX o5o3vJzbY1Vy568WIoI63oQwhRyad/k3F818UJusDWtIV64fBuH0ovZz1 UbjT8Yv+Ftv5EgKIGxjvBOWmHn27aZCPeVlRZ+XDlxCD9USZQvVN0G08a /jFUZHSsHNfyzkXfg1lJoqCWKaeQpJiH13OPsq9M7/LtBWoEwIWD9FNUJ Mh4w9ebF9CMKjHyI+LLG8vYcOlNjjbNth6h9vrLlQZLT1GB81CrqWJcfn g==; X-CSE-ConnectionGUID: yDV8OeL1T5WQXEWXpKV1+A== X-CSE-MsgGUID: RoCu3jsiS0G+9lu/8A1aJQ== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="53214467" X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="53214467" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:57:07 -0700 X-CSE-ConnectionGUID: 3X4X4U68Ttq5Zj9Z5nIKSw== X-CSE-MsgGUID: TapVp8apSniM0HuyJr/5Cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,265,1744095600"; d="scan'208";a="151696740" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2025 09:57:04 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com Subject: [PATCH v4 10/10] drm/xe/xe_late_bind_fw: Select INTEL_MEI_LATE_BIND for CI Date: Wed, 25 Jun 2025 22:30:15 +0530 Message-Id: <20250625170015.33912-11-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625170015.33912-1-badal.nilawar@intel.com> References: <20250625170015.33912-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Do not review Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig index 30ed74ad29ab..b161e1156c73 100644 --- a/drivers/gpu/drm/xe/Kconfig +++ b/drivers/gpu/drm/xe/Kconfig @@ -44,6 +44,7 @@ config DRM_XE select WANT_DEV_COREDUMP select AUXILIARY_BUS select HMM_MIRROR + select INTEL_MEI_LATE_BIND help Driver for Intel Xe2 series GPUs and later. Experimental support for Xe series is also available. --=20 2.34.1