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Wed, 25 Jun 2025 07:17:18 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:c47e:d783:f875:2c7c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4538235a85bsm21609425e9.23.2025.06.25.07.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 07:17:16 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/3] clk: renesas: r9a09g077-cpg: Add PLL2 and SDHI clock support Date: Wed, 25 Jun 2025 15:17:04 +0100 Message-ID: <20250625141705.151383-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250625141705.151383-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250625141705.151383-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for PLL2 to the R9A09G077 (RZ/T2H) clock definitions and register it as the source for the high-speed SDHI clock (SDHI_CLKHS) operating at 800MHz. Also add fixed-factor clock PCLKAM derived from CLK_PLL4D1, and define module clocks for SDHI0 and SDHI1, both of which use PCLKAM as their clock source. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g077-cpg.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index baf917ff4beb..93862d84f95f 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -67,7 +67,7 @@ enum rzt2h_clk_types { =20 enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK =3D R9A09G077_CLK_PCLKL, + LAST_DT_CORE_CLK =3D R9A09G077_SDHI_CLKHS, =20 /* External Input Clocks */ CLK_EXTAL, @@ -76,9 +76,11 @@ enum clk_ids { CLK_LOCO, CLK_PLL0, CLK_PLL1, + CLK_PLL2, CLK_PLL4, CLK_SEL_CLK_PLL0, CLK_SEL_CLK_PLL1, + CLK_SEL_CLK_PLL2, CLK_SEL_CLK_PLL4, CLK_PLL4D1, CLK_SCI0ASYNC, @@ -105,6 +107,7 @@ static const struct clk_div_table dtable_24_25_30_32[] = =3D { =20 static const char * const sel_clk_pll0[] =3D { ".loco", ".pll0" }; static const char * const sel_clk_pll1[] =3D { ".loco", ".pll1" }; +static const char * const sel_clk_pll2[] =3D { ".loco", ".pll2" }; static const char * const sel_clk_pll4[] =3D { ".loco", ".pll4" }; =20 static const struct cpg_core_clk r9a09g077_core_clks[] __initconst =3D { @@ -115,12 +118,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[= ] __initconst =3D { DEF_RATE(".loco", CLK_LOCO, 1000 * 1000), DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 1, 48), DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 1, 32), DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96), =20 DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL, sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY), DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL, sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY), + DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL, + sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY), DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL, sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY), =20 @@ -142,10 +148,14 @@ static const struct cpg_core_clk r9a09g077_core_clks[= ] __initconst =3D { DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1), DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1), DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1), + DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1), + DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1), }; =20 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst =3D { DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC), + DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM), + DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM), }; =20 static struct clk * __init --=20 2.49.0