From nobody Wed Oct 8 17:34:02 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F16E264FB3; Wed, 25 Jun 2025 13:17:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857425; cv=none; b=mL5MO1Z7MuMpMZaAIW/Pq2Jdiqjl3D3ZSGHVnTjIFLbkXBXYIf0/E7XiVz9NFiFTLXxxwpmPFXqonwnohMMdf5ueh0+63dWWoa1G9Dg92ei11GoHlzwWsY1LZn3YBOB0RnwXcE7gMXa40DH8BrQ8TJzE5ggEQIgNP+25Nz04oCk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857425; c=relaxed/simple; bh=rY5b8vRqdXfrxDOAn0nZ9LkgMlPuDFO9Y76rv/I7xqs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qDCEe7g+YQA8s0UaFoK2uTMivNIzN+pYoU9uKlBBMo4yJRziGyeFCRdBemh7KW2ZS/12uqXzK7w9bEG/yMz9Se9NNnUUty6By9tGrT1AA7EHp6i/+PPKmTpmyQ8y9Vo8LokXXnfVpFODvy/niYVo01LDBK3Vp4PxasV1680HuZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tZFq04FJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tZFq04FJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DBDD9C4CEF0; Wed, 25 Jun 2025 13:17:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857425; bh=rY5b8vRqdXfrxDOAn0nZ9LkgMlPuDFO9Y76rv/I7xqs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tZFq04FJczg0EJNQiggiT9bTqrGhHGfEryGsPeCBi4zbJnm9eHI+gjO4qQzu4MJgu j0ZzvH1Dg1GMBraQAtBe/EjWQg6RamqjKKaz6SgQfbvyHxJKurD0Ac0q/KSjaRcdON TNWBCs7dOb5BBdiTEz6Re1hxpuRe0bNd4E0aezKDvmSDWdjzmUs6P24EImmwRMGkyv u6RvSd/8etVRpK0eoxi+t4YCaeXN+pxYkuvLMVfbLgOmnfFzXowaWAZdo8d0alJuaH ukskJTj6qxHRhe1pqbXL9TNasHg9Rak9Euc8f/cUZrw/dlFsBhNm2M5nb+23y7yMUz rQrRU5muXWGkA== Received: by wens.tw (Postfix, from userid 1000) id 587075FAC5; Wed, 25 Jun 2025 21:17:02 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara , Conor Dooley Subject: [PATCH v2 1/5] dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board Date: Wed, 25 Jun 2025 21:16:48 +0800 Message-Id: <20250625131652.1667345-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250625131652.1667345-1-wens@kernel.org> References: <20250625131652.1667345-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The OrangePi 4A is a typical Raspberry Pi model B sized development board from Xunlong designed around an Allwinner T527 SoC. Add its compatible name to the list of valid ones. Reviewed-by: Andre Przywara Acked-by: Conor Dooley Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentati= on/devicetree/bindings/arm/sunxi.yaml index 7807ea613258..c41d0a0b89e6 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -996,6 +996,11 @@ properties: - const: xunlong,orangepi-3 - const: allwinner,sun50i-h6 =20 + - description: Xunlong OrangePi 4A + items: + - const: xunlong,orangepi-4a + - const: allwinner,sun55i-t527 + - description: Xunlong OrangePi Lite items: - const: xunlong,orangepi-lite --=20 2.39.5 From nobody Wed Oct 8 17:34:02 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06E7C25FA31; Wed, 25 Jun 2025 13:17:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857425; cv=none; b=jPl/YZ3moIzfpj6jkLziXQh2Q1z2rWAWzMIk8AuhC/We/4lrhRsjbnoBOy1BSu+f1EGUrbFOqsD3XnApJ7ph6NwHjECEyB1p4RkBQiFKmA0su3JbT57K3R42CfEc7mITeueAxQoaI82XxPwXiQT4LaxrvCBMWXMBffTVu0XuUs4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857425; c=relaxed/simple; bh=bRr/5nBVNTrO8h20FoPhHm0wRk96HyeoMwIQD4LmilM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=C8/5NEg5RqpM6NnA8ZgZEjAU8iKP77OdrA1Slm5qgRS5fanrAfYnrff7DbTTr5FBzcKSaSUfG02iEWgKaOh3n94+K+2DGEEUXuEeHXKm6VQqVj8XPhmnKJIv7/NKBWOr5+acPk8airOZZP1832AGwLq9vLUs0zjHeEvI4VNGfwM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=k++/2pzA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k++/2pzA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B81D9C4AF09; Wed, 25 Jun 2025 13:17:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857424; bh=bRr/5nBVNTrO8h20FoPhHm0wRk96HyeoMwIQD4LmilM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k++/2pzAGuY4XdUVV8YAqUHG2uxVs4d9ZCHK82L+bB0W50e04qc6lcpiQfnVenQNh yckW3BuZy9cXoG18Db6m5qQAB925pd+zfbEHFuu35UwK3929/pKQBDGmZRRgbWp2zN Wk8Ixx6u1BlyQMqKvSk296ltnMOFho3SIgAdKPge34Rpd+zckdRd7tsWqBcHQip5QA W21UkbwKpOc56N3/4x6EZEMkTnxwP67HjmSk/tXm6xK41WL+q1mRhA95T3nckRZVdS IkA3AlYHb/ujGaWRCYRq4QUT+u2Mj+VQYhCFpSQlX0k61vGKevF6dFtNgmsW1kztFL riqE1hn3lu6iw== Received: by wens.tw (Postfix, from userid 1000) id 5DFE05FF19; Wed, 25 Jun 2025 21:17:02 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH v2 2/5] arm64: dts: allwinner: a523: Move mmc nodes to correct position Date: Wed, 25 Jun 2025 21:16:49 +0800 Message-Id: <20250625131652.1667345-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250625131652.1667345-1-wens@kernel.org> References: <20250625131652.1667345-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai When the mmc nodes were added to the dtsi file, they were inserted in the incorrect position. Move them to the correct place. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 126 +++++++++--------- 1 file changed, 63 insertions(+), 63 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 8b7cbc2e78f5..458d7ecedacd 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -181,69 +181,6 @@ ccu: clock-controller@2001000 { #reset-cells =3D <1>; }; =20 - mmc0: mmc@4020000 { - compatible =3D "allwinner,sun55i-a523-mmc", - "allwinner,sun20i-d1-mmc"; - reg =3D <0x04020000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names =3D "ahb", "mmc"; - resets =3D <&ccu RST_BUS_MMC0>; - reset-names =3D "ahb"; - interrupts =3D ; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mmc0_pins>; - status =3D "disabled"; - - max-frequency =3D <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - mmc1: mmc@4021000 { - compatible =3D "allwinner,sun55i-a523-mmc", - "allwinner,sun20i-d1-mmc"; - reg =3D <0x04021000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names =3D "ahb", "mmc"; - resets =3D <&ccu RST_BUS_MMC1>; - reset-names =3D "ahb"; - interrupts =3D ; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mmc1_pins>; - status =3D "disabled"; - - max-frequency =3D <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - mmc2: mmc@4022000 { - compatible =3D "allwinner,sun55i-a523-mmc", - "allwinner,sun20i-d1-mmc"; - reg =3D <0x04022000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names =3D "ahb", "mmc"; - resets =3D <&ccu RST_BUS_MMC2>; - reset-names =3D "ahb"; - interrupts =3D ; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mmc2_pins>; - status =3D "disabled"; - - max-frequency =3D <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - wdt: watchdog@2050000 { compatible =3D "allwinner,sun55i-a523-wdt"; reg =3D <0x2050000 0x20>; @@ -449,6 +386,69 @@ its: msi-controller@3440000 { }; }; =20 + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg =3D <0x04020000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins>; + status =3D "disabled"; + + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg =3D <0x04021000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; 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charset="utf-8" From: Chen-Yu Tsai Nodes are supposed to be sorted by address, or if no addresses apply, by node name. The rgmii0 pins are out of order, possibly due to multiple patches adding pin mux settings conflicting. Move the rgmii0 pins to the correct location. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 458d7ecedacd..30613a0b1124 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -126,16 +126,6 @@ pio: pinctrl@2000000 { interrupt-controller; #interrupt-cells =3D <3>; =20 - rgmii0_pins: rgmii0-pins { - pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", - "PH5", "PH6", "PH7", "PH9", "PH10", - "PH14", "PH15", "PH16", "PH17", "PH18"; - allwinner,pinmux =3D <5>; - function =3D "emac0"; - drive-strength =3D <40>; - bias-disable; - }; - mmc0_pins: mmc0-pins { pins =3D "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,pinmux =3D <2>; @@ -163,6 +153,16 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; =20 + rgmii0_pins: rgmii0-pins { + pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH9", "PH10", + "PH14", "PH15", "PH16", "PH17", "PH18"; + allwinner,pinmux =3D <5>; + function =3D "emac0"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; --=20 2.39.5 From nobody Wed Oct 8 17:34:02 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04F8925F784; Wed, 25 Jun 2025 13:17:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857425; cv=none; b=JLoqY8emzParYivl8nyf3LuLIdxl5IGI56ck6i1gKhB160pDE66tTQRMOSIk5zpbagy5P09mKwDRH45mGkwaqGJIbizHEqxuwGQpaZcZJnm9j200T1qhN/HIn43yeaDH2/BMnn43KZXAcvJRTjqzVsRGweZizyk3nFfnhvRuud0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857425; c=relaxed/simple; bh=2wjz3+JKr8b/GuKvZURR2QiYdmWce02dMigkYvBt0Gk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AQL0MoZNDaKPRQvjIb6JJemGmqA6ZZVLTzYahmhHdwVrmJtrGQ0T7G42/BotF/m3J0f1SdifHEgHDMgSA8KbKGk90/DcqJ1lzso6GOOlxLefxiDLm9kiBuzCn5rwywpnIkgYtKzbjOCaRLFdQWcqijdhYY4Sl1W90/EG+Tvo8MI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F3AopbvJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F3AopbvJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B4105C4CEEE; Wed, 25 Jun 2025 13:17:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857424; bh=2wjz3+JKr8b/GuKvZURR2QiYdmWce02dMigkYvBt0Gk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F3AopbvJ164+Etui5cLAx3/wbfJEr+coRlX2u6OyEm1akxuq0i/AL7fUXVMBTjiLv LLjT9xl8src5NZV1o1yIMp4eh/9b3evLl2JUGSyNIWStmk/jPDDgT3Dz9XQTQJJgPt zN0zX6f4dp+DGSrZ6Dun2F8eNQAiu0fkFrAN4H0HR0BhP4BjUACuf3pgjS1fzcvORZ eM/2PRlGQaASki9zmJmbSRbsO4qU8zRsyX38v9xy7KruT8eZtgAdiMnkbTdZQTtHba ZvCo1AFMvM3IoKuTr1AdyHdp2Mpw0cF9hym7nj2PrZZZOmsP7J0hhvgTijm9Cy2OIe hm1ciZ94ZlrVQ== Received: by wens.tw (Postfix, from userid 1000) id 794825FF4F; Wed, 25 Jun 2025 21:17:02 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH v2 4/5] arm64: dts: allwinner: a523: Add UART1 pins Date: Wed, 25 Jun 2025 21:16:51 +0800 Message-Id: <20250625131652.1667345-5-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250625131652.1667345-1-wens@kernel.org> References: <20250625131652.1667345-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai UART1 is normally used to connect to the Bluetooth side of a Broadcom WiFi+BT combo chip. The connection uses 4 pins. Add pinmux nodes for UART1, one for the RX/TX pins, and one for the RTS/CTS pins. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 30613a0b1124..6f62201fd739 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -168,6 +168,20 @@ uart0_pb_pins: uart0-pb-pins { allwinner,pinmux =3D <2>; function =3D "uart0"; }; + + /omit-if-no-ref/ + uart1_pins: uart1-pins { + pins =3D "PG6", "PG7"; + function =3D "uart1"; + allwinner,pinmux =3D <2>; + }; + + /omit-if-no-ref/ + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins =3D "PG8", "PG9"; + function =3D "uart1"; + allwinner,pinmux =3D <2>; + }; }; =20 ccu: clock-controller@2001000 { --=20 2.39.5 From nobody Wed Oct 8 17:34:02 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DDCF26B745; Wed, 25 Jun 2025 13:17:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857427; cv=none; b=a3wZqj63H8MdXKSz8yabEd8qwctdnShJhIyIbX14pNSdAyQUyVjaoM264wZgm8UXGIv0bVfMcq1HfCDhTuxKpMgf3YtkHYc9rL4Ygpf//UmilAA5o8cqtPbZ3MvLAfrGJoja32GHBtzP18SZc3XvMNeFathrBQ27R6qUwh2hGLQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857427; c=relaxed/simple; bh=GQCtV65tnQSYaczAMpaz5abbjbW1c9WMqIxzwn0KYr4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GXuvr9mXk+HEGjRI3v0z27qyD0doh5GGD1qT1C0lcVHebtn8fQsVa7jaRMotvLipMNAP8pjM3jpHZ+6LkPnfJppToGfmDT4uQInGTIvlQHdcZiPynm+HvTlX4hYt8mp6qjwgvDCljex93z6VIbmrGcuY8ZH3hNdsCL5kj6tV7uA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pBJwVyJ5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pBJwVyJ5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F877C4CEEA; Wed, 25 Jun 2025 13:17:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857427; bh=GQCtV65tnQSYaczAMpaz5abbjbW1c9WMqIxzwn0KYr4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pBJwVyJ5ILFW2wIUW1Ms5dl8Af3Ir1xWOfDgTS97UtVEZT3uC6vo4AAOEnXpBwruQ EujFxoRE3LsYWvuK0DlP48m/pPWi4aiK6dgydPzfKPejs59D1L83a17xWV3LK19a/P cNVyAtD6qB82QYig3G5MDo6w7YAiTO2CWJ9f93czKZT13rnJRvxiQnvWxmYioMJNRT ueO2fP6aE1PsMqssJUNf6j3H7si+yFx21J0jCxBrp4hoIuBc0yjbTrLMNy/MPtBnVW Y8/WauWdiA3USwBRp/NqX2fGAymGfEmIG6RWL9EpM+Iqn6bK25Uv4s6hOo3gZPhtbc 0CUqYN7zfSEcg== Received: by wens.tw (Postfix, from userid 1000) id 7F9B85FFBC; Wed, 25 Jun 2025 21:17:02 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH v2 5/5] arm64: dts: allwinner: t527: Add OrangePi 4A board Date: Wed, 25 Jun 2025 21:16:52 +0800 Message-Id: <20250625131652.1667345-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250625131652.1667345-1-wens@kernel.org> References: <20250625131652.1667345-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The OrangePi 4A is a typical Raspberry Pi model B sized development board from Xunlong designed around an Allwinner T527 SoC. The board has the following features: - Allwinner T527 SoC - AXP717B + AXP323 PMICs - Up to 4GB LPDDR4 DRAM - micro SD slot - optional eMMC module - M.2 slot for PCIe 2.0 x1 - 16 MB SPI-NOR flash - 4x USB 2.0 type-A ports (one can be used in gadget mode) - 1x Gigabit ethernet w/ Motorcomm PHY (through yet to be supported GMAC200) - 3.5mm audio jack via internal audio codec - HDMI 2.0 output - eDP, MIPI CSI (2-lane and 4-lane) and MIPI DSI (4-lane) connectors - USB type-C port purely for power - AP6256 (Broadcom BCM4345) WiFi 5.0 + BT 5.0 - unsoldered headers for ADC and an additional USB 2.0 host port - 40-pin GPIO header Add a device tree for it, enabling all peripherals currently supported. Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Fixed regulator names for bldo3 and bldo4 - Dropped labels for aldo1, bldo3, and bldo4, which are not really used - Added voltage constraints to aldo2, based on specifications from schematic - Appended "-usb-0v9" to cpusldo's regulator name - Added comments to explain how axp323 aldo1 and dldo1 are tied together arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 383 ++++++++++++++++++ 2 files changed, 384 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.d= ts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 773cc02a13d0..780aeba0f3a4 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -57,3 +57,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx= -sp.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-a527-cubie-a5e.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-h728-x96qpro+.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-avaota-a1.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-orangepi-4a.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts new file mode 100644 index 000000000000..ff2fd8e71e03 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include +#include + +/ { + model =3D "OrangePi 4A"; + compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "ext_osc32k"; + }; + + leds { + compatible =3D "gpio-leds"; + + /* PWM capable pin, but PWM isn't supported yet. */ + led { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + }; + }; + + wifi_pwrseq: pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&r_pio 1 1 GPIO_ACTIVE_LOW>; /* PM1 */ + clocks =3D <&rtc CLK_OSC32K_FANOUT>; + clock-names =3D "ext_clock"; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "otg-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + enable-active-high; + }; + + reg_pcie_vcc3v3: regulator-pcie-vcc3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-pcie-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; + + reg_usb_vbus: regulator-usb-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 12 GPIO_ACTIVE_HIGH>; /* PL12 */ + enable-active-high; + }; + + reg_vcc5v: regulator-vcc5v { + /* board wide 5V supply from USB type-C port */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + vmmc-supply =3D <®_cldo3>; + cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_dldo1_323>; + vqmmc-supply =3D <®_bldo1>; + status =3D "okay"; + + brcmf: wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + interrupt-parent =3D <&r_pio>; + interrupts =3D <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ + interrupt-names =3D "host-wake"; + }; +}; + +&mmc2 { + bus-width =3D <8>; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <®_cldo3>; + vqmmc-supply =3D <®_cldo1>; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pb-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply =3D <®_cldo1>; + vcc-pd-supply =3D <®_cldo3>; + vcc-pe-supply =3D <®_aldo2>; + vcc-pf-supply =3D <®_cldo3>; /* VCC-IO for 3.3v; VCC-MCSI for 1.8v */ + vcc-pg-supply =3D <®_bldo1>; + vcc-ph-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply =3D <®_cldo3>; + vcc-pj-supply =3D <®_cldo1>; + vcc-pk-supply =3D <®_cldo1>; +}; + +&r_i2c0 { + status =3D "okay"; + + axp717: pmic@35 { + compatible =3D "x-powers,axp717"; + reg =3D <0x35>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&nmi_intc 0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + vin4-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <920000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1160000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vcc-dram"; + }; + + reg_dcdc4: dcdc4 { + /* feeds 3.3V pin on GPIO header */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vdd-io"; + }; + + aldo1 { + /* not actually connected */ + regulator-name =3D "avdd-csi"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pe"; + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-pl-usb"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pg-wifi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pm-lpddr"; + }; + + bldo3 { + /* not actually connected */ + regulator-name =3D "afvcc-csi"; + }; + + bldo4 { + /* not actually connected */ + regulator-name =3D "dvdd-csi"; + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-cvp-pc-lvds-mcsi-pk-efuse-pcie-edp-1v8"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-csi"; + }; + + reg_cldo3: cldo3 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-io-mmc-nand-pd-pi-usb"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-3v3-phy1-lcd"; + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible =3D "x-powers,axp323"; + reg =3D <0x36>; + #interrupt-cells =3D <1>; + interrupt-controller; + status =3D "okay"; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + + regulators { + reg_aldo1_323: aldo1 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-wifi"; + }; + + reg_dldo1_323: dldo1 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-wifi2"; + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1150000>; + regulator-name =3D "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* Some RISC-V management core related voltage */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply =3D <®_aldo3>; + */ + vcc-pm-supply =3D <®_bldo2>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pb_pins>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm4345c5"; + clocks =3D <&rtc CLK_OSC32K_FANOUT>; + clock-names =3D "lpo"; + vbat-supply =3D <®_aldo1_323>; + vddio-supply =3D <®_bldo1>; + device-wakeup-gpios =3D <&r_pio 1 3 GPIO_ACTIVE_HIGH>; /* PM3 */ + host-wakeup-gpios =3D <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ + shutdown-gpios =3D <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ + }; +}; + +&usb_otg { + /* + * The OTG controller is connected to one of the type-A ports. + * There is a regulator, controlled by a GPIO, to provide VBUS power + * to the port, and a VBUSDET GPIO, to detect externally provided + * power. But without ID or CC pins there is no real way to do a + * runtime role detection. + */ + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usbphy { + usb0_vbus-supply =3D <®_otg_vbus>; + usb0_vbus_det-gpios =3D <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + usb1_vbus-supply =3D <®_usb_vbus>; + status =3D "okay"; +}; --=20 2.39.5