From nobody Wed Oct 8 20:17:02 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3071425EF82 for ; Wed, 25 Jun 2025 11:35:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750851301; cv=none; b=EQy3kALdmZYu8YYCm/I43ZRUoujhtSvMdlellxlbwgipM+bvUHeOcUoIoKQb0F+Olpw7E4+aLB8lr3G+r1ThJ7rNpzPymTpY9kH/ealWnYo4ao8mXozpjhSHNKjr1sDMnov7jCsOHTs/RWWOMb2Q23exoBgkL4GqjjfWVTAJ1Ag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750851301; c=relaxed/simple; bh=7g2ZgDyqdK+/bHCMw8fbIJLN1rbyvElwZKb0WnbvDbg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gH2YJ4AYLpX2LsanFRDl8Kb5zHGFNeyGI29S3MajMVpcCzDnnicyr3CHljPThUlUmhftXvs8vwPrgjvv2lLjBZAKe3hGwFpJaywLFcxhNDJGDoLRL5xnNJKESm/IvEsVEQMiwe+kg9lpii9I3OS7K1IPwgLhS4Up214n0HKONL8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F8D120E3; Wed, 25 Jun 2025 04:34:41 -0700 (PDT) Received: from mazurka.cambridge.arm.com (mazurka.cambridge.arm.com [10.2.80.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B490D3F58B; Wed, 25 Jun 2025 04:34:55 -0700 (PDT) From: =?UTF-8?q?Miko=C5=82aj=20Lenczewski?= To: ryan.roberts@arm.com, yang@os.amperecomputing.com, catalin.marinas@arm.com, will@kernel.org, jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, james.morse@arm.com, broonie@kernel.org, ardb@kernel.org, baohua@kernel.org, suzuki.poulose@arm.com, david@redhat.com, jgg@ziepe.ca, nicolinc@nvidia.com, jsnitsel@redhat.com, mshavit@google.com, kevin.tian@intel.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev Cc: =?UTF-8?q?Miko=C5=82aj=20Lenczewski?= Subject: [PATCH v8 3/4] iommu/arm: Add BBM Level 2 smmu feature Date: Wed, 25 Jun 2025 11:34:34 +0000 Message-ID: <20250625113435.26849-4-miko.lenczewski@arm.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250625113435.26849-1-miko.lenczewski@arm.com> References: <20250625113435.26849-1-miko.lenczewski@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable For supporting BBM Level 2 for userspace mappings, we want to ensure that the smmu also supports its own version of BBM Level 2. Luckily, the smmu spec (IHI 0070G 3.21.1.3) is stricter than the aarch64 spec (DDI 0487K.a D8.16.2), so already guarantees that no aborts are raised when BBM level 2 is claimed. Add the feature and testing for it under arm_smmu_sva_supported(). Signed-off-by: Miko=C5=82aj Lenczewski Reviewed-by: Catalin Marinas Reviewed-by: Robin Murphy Reviewed-by: Ryan Roberts --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 3 +++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 0601dece0a0d..59a480974d80 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -220,6 +220,9 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smm= u) feat_mask |=3D ARM_SMMU_FEAT_VAX; } =20 + if (system_supports_bbml2_noabort()) + feat_mask |=3D ARM_SMMU_FEAT_BBML2; + if ((smmu->features & feat_mask) !=3D feat_mask) return false; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 10cc6dc26b7b..39e933086f8f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4457,6 +4457,9 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_d= evice *smmu) if (FIELD_GET(IDR3_FWB, reg)) smmu->features |=3D ARM_SMMU_FEAT_S2FWB; =20 + if (FIELD_GET(IDR3_BBM, reg) =3D=3D 2) + smmu->features |=3D ARM_SMMU_FEAT_BBML2; + /* IDR5 */ reg =3D readl_relaxed(smmu->base + ARM_SMMU_IDR5); =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ea41d790463e..a33bf520ba97 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -60,6 +60,7 @@ struct arm_smmu_device; #define ARM_SMMU_IDR3 0xc #define IDR3_FWB (1 << 8) #define IDR3_RIL (1 << 10) +#define IDR3_BBM GENMASK(12, 11) =20 #define ARM_SMMU_IDR5 0x14 #define IDR5_STALL_MAX GENMASK(31, 16) @@ -755,6 +756,7 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_HA (1 << 21) #define ARM_SMMU_FEAT_HD (1 << 22) #define ARM_SMMU_FEAT_S2FWB (1 << 23) +#define ARM_SMMU_FEAT_BBML2 (1 << 24) u32 features; =20 #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) --=20 2.49.0