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charset="utf-8" From: Lad Prabhakar In preparation for adding more validation checks, move the `$ref` for 'i2c-controller.yaml' to the end of the file. Also, relocate the conditional check for 'resets' into the 'allOf' block. Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v3->v4: - No changes. v2->v3: - No changes. v1->v2: - Added Acked-by and Reviewed-by tags. --- .../devicetree/bindings/i2c/renesas,riic.yaml | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Docu= mentation/devicetree/bindings/i2c/renesas,riic.yaml index cc39511a49d6..bfcc400655dc 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -10,9 +10,6 @@ maintainers: - Chris Brandt - Wolfram Sang =20 -allOf: - - $ref: /schemas/i2c/i2c-controller.yaml# - properties: compatible: oneOf: @@ -84,18 +81,21 @@ required: - '#address-cells' - '#size-cells' =20 -if: - properties: - compatible: - contains: - enum: - - renesas,riic-r9a07g043 - - renesas,riic-r9a07g044 - - renesas,riic-r9a07g054 - - renesas,riic-r9a09g057 -then: - required: - - resets +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,riic-r9a07g043 + - renesas,riic-r9a07g044 + - renesas,riic-r9a07g054 + - renesas,riic-r9a09g057 + then: + required: + - resets =20 unevaluatedProperties: false =20 --=20 2.49.0 From nobody Wed Oct 8 18:16:57 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09A622D878E; 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Wed, 25 Jun 2025 03:45:36 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:c47e:d783:f875:2c7c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4538233c1easm16036175e9.3.2025.06.25.03.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 03:45:35 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Chris Brandt , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Wolfram Sang , Andy Shevchenko Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , Conor Dooley Subject: [PATCH v4 2/5] dt-bindings: i2c: renesas,riic: Document RZ/T2H and RZ/N2H support Date: Wed, 25 Jun 2025 11:45:23 +0100 Message-ID: <20250625104526.101004-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250625104526.101004-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250625104526.101004-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Document support for the I2C Bus Interface (RIIC) found on the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The RIIC IP on these parts is similar to that on RZ/V2H(P) but supports only four interrupts (including a combined error/event), lacks FM+ mode, and does not require reset. Introduce a new compatible string `renesas,riic-r9a09g077` for RZ/T2H and use it as a fallback for RZ/N2H. Unlike earlier SoCs that use eight distinct interrupts, the RZ/T2H uses only four. Update the binding schema to reflect this interrupt layout and skip the `resets` property check, as it is not required on these SoCs. Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- v3->v4: - Squashed documenting RZ/N2H into same patch - Updated commit messages - Collected Reviewed-by tag from Geert - Restored Ack and Reviews v2->v3: - Replaced Transmit Error -> `Transfer Error` - Fixed the order of interrupts in the DT binding documentation to match the HW manual. v1-> v2: - Listed the interrupts in the order as mentioned in the HW manual. - Renamed the interrupt names to match the HW manual. - Added Acked-by and Reviewed-by tags. --- .../devicetree/bindings/i2c/renesas,riic.yaml | 75 ++++++++++++++----- 1 file changed, 56 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Docu= mentation/devicetree/bindings/i2c/renesas,riic.yaml index bfcc400655dc..6876eade431b 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -29,32 +29,50 @@ properties: - renesas,riic-r9a09g056 # RZ/V2N - const: renesas,riic-r9a09g057 # RZ/V2H(P) =20 - - const: renesas,riic-r9a09g057 # RZ/V2H(P) + - enum: + - renesas,riic-r9a09g057 # RZ/V2H(P) + - renesas,riic-r9a09g077 # RZ/T2H + + - items: + - const: renesas,riic-r9a09g087 # RZ/N2H + - const: renesas,riic-r9a09g077 # RZ/T2H =20 reg: maxItems: 1 =20 interrupts: - items: - - description: Transmit End Interrupt - - description: Receive Data Full Interrupt - - description: Transmit Data Empty Interrupt - - description: Stop Condition Detection Interrupt - - description: Start Condition Detection Interrupt - - description: NACK Reception Interrupt - - description: Arbitration-Lost Interrupt - - description: Timeout Interrupt + oneOf: + - items: + - description: Transmit End Interrupt + - description: Receive Data Full Interrupt + - description: Transmit Data Empty Interrupt + - description: Stop Condition Detection Interrupt + - description: Start Condition Detection Interrupt + - description: NACK Reception Interrupt + - description: Arbitration-Lost Interrupt + - description: Timeout Interrupt + - items: + - description: Transfer Error Or Event Generation + - description: Receive Data Full Interrupt + - description: Transmit Data Empty Interrupt + - description: Transmit End Interrupt =20 interrupt-names: - items: - - const: tei - - const: ri - - const: ti - - const: spi - - const: sti - - const: naki - - const: ali - - const: tmoi + oneOf: + - items: + - const: tei + - const: ri + - const: ti + - const: spi + - const: sti + - const: naki + - const: ali + - const: tmoi + - items: + - const: eei + - const: rxi + - const: txi + - const: tei =20 clock-frequency: description: @@ -84,6 +102,25 @@ required: allOf: - $ref: /schemas/i2c/i2c-controller.yaml# =20 + - if: + properties: + compatible: + contains: + const: renesas,riic-r9a09g077 + then: + properties: + interrupts: + maxItems: 4 + interrupt-names: + maxItems: 4 + resets: false + else: + properties: + interrupts: + minItems: 8 + interrupt-names: + minItems: 8 + - if: properties: compatible: --=20 2.49.0 From nobody Wed Oct 8 18:16:57 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 804642D9ECB; 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charset="utf-8" From: Lad Prabhakar In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs, which feature a combined error interrupt instead of individual error interrupts per condition, update the driver to support configurable IRQ layouts via OF data. Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to allow future SoCs to provide a custom IRQ layout. This patch is a non-functional change for existing SoCs and maintains compatibility with the current `riic_irqs` array. Signed-off-by: Lad Prabhakar Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang # on RZ/A1 Reviewed-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven Reviewed-by: Andy Shevchenko --- v3->v4: - No changes. v2->v3: - No changes. v1->v2: - Added Acked-by and Reviewed-by tags. --- drivers/i2c/busses/i2c-riic.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 23375f7fe3ad..ecd1c78eecfd 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -102,6 +102,8 @@ enum riic_reg_list { =20 struct riic_of_data { const u8 *regs; + const struct riic_irq_desc *irqs; + u8 num_irqs; bool fast_mode_plus; }; =20 @@ -520,21 +522,23 @@ static int riic_i2c_probe(struct platform_device *pde= v) return dev_err_probe(dev, PTR_ERR(riic->rstc), "failed to acquire deasserted reset\n"); =20 - for (i =3D 0; i < ARRAY_SIZE(riic_irqs); i++) { + riic->info =3D of_device_get_match_data(dev); + + for (i =3D 0; i < riic->info->num_irqs; i++) { + const struct riic_irq_desc *irq_desc; int irq; =20 - irq =3D platform_get_irq(pdev, riic_irqs[i].res_num); + irq_desc =3D &riic->info->irqs[i]; + irq =3D platform_get_irq(pdev, irq_desc->res_num); if (irq < 0) return irq; =20 - ret =3D devm_request_irq(dev, irq, riic_irqs[i].isr, - 0, riic_irqs[i].name, riic); + ret =3D devm_request_irq(dev, irq, irq_desc->isr, 0, irq_desc->name, rii= c); if (ret) return dev_err_probe(dev, ret, "failed to request irq %s\n", - riic_irqs[i].name); + irq_desc->name); } =20 - riic->info =3D of_device_get_match_data(dev); =20 adap =3D &riic->adapter; i2c_set_adapdata(adap, riic); @@ -606,11 +610,15 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] =3D { =20 static const struct riic_of_data riic_rz_a_info =3D { .regs =3D riic_rz_a_regs, + .irqs =3D riic_irqs, + .num_irqs =3D ARRAY_SIZE(riic_irqs), .fast_mode_plus =3D true, }; =20 static const struct riic_of_data riic_rz_a1h_info =3D { .regs =3D riic_rz_a_regs, + .irqs =3D riic_irqs, + .num_irqs =3D ARRAY_SIZE(riic_irqs), }; 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charset="utf-8" From: Lad Prabhakar Reorder the entry in `riic_i2c_dt_ids` to place the generic compatible string `renesas,riic-rz` at the end of the array, following the convention used in other Renesas drivers. Also, drop the unnecessary comma after the sentinel entry, as it is not needed. Signed-off-by: Lad Prabhakar Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang # on RZ/A1 Reviewed-by: Geert Uytterhoeven Reviewed-by: Andy Shevchenko --- v3->v4: - No changes. v2->v3: - No changes. v1->v2: - Initialized the members of `riic_of_data` in the order they are declared in the struct. - Added Reviewed-by and Tested-by tags. --- drivers/i2c/busses/i2c-riic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index ecd1c78eecfd..d0b975e45595 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -693,10 +693,10 @@ static const struct dev_pm_ops riic_i2c_pm_ops =3D { }; =20 static const struct of_device_id riic_i2c_dt_ids[] =3D { - { .compatible =3D "renesas,riic-rz", .data =3D &riic_rz_a_info }, { .compatible =3D "renesas,riic-r7s72100", .data =3D &riic_rz_a1h_info, = }, { .compatible =3D "renesas,riic-r9a09g057", .data =3D &riic_rz_v2h_info }, - { /* Sentinel */ }, + { .compatible =3D "renesas,riic-rz", .data =3D &riic_rz_a_info }, + { /* Sentinel */ } }; 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charset="utf-8" From: Lad Prabhakar Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a different interrupt layout for the RIIC controller. Unlike other SoCs with individual error interrupts, RZ/T2H uses a combined error interrupt (EEI). Introduce a new IRQ descriptor table for RZ/T2H, along with a custom ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared interrupt. Signed-off-by: Lad Prabhakar Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang # on RZ/A1 Reviewed-by: Geert Uytterhoeven Reviewed-by: Andy Shevchenko --- v3->v4: - No changes. v2->v3: - No changes. v1->v2: - Updated the riic_rzt2h_irqs array to match the order of interrupts as mentioned in the DT binding. - Updated the interrupt names in the riic_rzt2h_irqs array to match the HW manual. - Added Tested-by and Reviewed-by tags. --- drivers/i2c/busses/i2c-riic.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index d0b975e45595..9c164a4b9bb9 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -79,6 +79,7 @@ #define ICIER_SPIE BIT(3) =20 #define ICSR2_NACKF BIT(4) +#define ICSR2_STOP BIT(3) =20 #define ICBR_RESERVED GENMASK(7, 5) /* Should be 1 on writes */ =20 @@ -326,6 +327,19 @@ static irqreturn_t riic_stop_isr(int irq, void *data) return IRQ_HANDLED; } =20 +static irqreturn_t riic_eei_isr(int irq, void *data) +{ + u8 icsr2 =3D riic_readb(data, RIIC_ICSR2); + + if (icsr2 & ICSR2_NACKF) + return riic_tend_isr(irq, data); + + if (icsr2 & ICSR2_STOP) + return riic_stop_isr(irq, data); + + return IRQ_NONE; +} + static u32 riic_func(struct i2c_adapter *adap) { return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; @@ -497,6 +511,13 @@ static const struct riic_irq_desc riic_irqs[] =3D { { .res_num =3D 5, .isr =3D riic_tend_isr, .name =3D "riic-nack" }, }; =20 +static const struct riic_irq_desc riic_rzt2h_irqs[] =3D { + { .res_num =3D 0, .isr =3D riic_eei_isr, .name =3D "riic-eei" }, + { .res_num =3D 1, .isr =3D riic_rdrf_isr, .name =3D "riic-rxi" }, + { .res_num =3D 2, .isr =3D riic_tdre_isr, .name =3D "riic-txi" }, + { .res_num =3D 3, .isr =3D riic_tend_isr, .name =3D "riic-tei" }, +}; + static int riic_i2c_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -643,6 +664,12 @@ static const struct riic_of_data riic_rz_v2h_info =3D { .fast_mode_plus =3D true, }; =20 +static const struct riic_of_data riic_rz_t2h_info =3D { + .regs =3D riic_rz_v2h_regs, + .irqs =3D riic_rzt2h_irqs, + .num_irqs =3D ARRAY_SIZE(riic_rzt2h_irqs), +}; + static int riic_i2c_suspend(struct device *dev) { struct riic_dev *riic =3D dev_get_drvdata(dev); @@ -695,6 +722,7 @@ static const struct dev_pm_ops riic_i2c_pm_ops =3D { static const struct of_device_id riic_i2c_dt_ids[] =3D { { .compatible =3D "renesas,riic-r7s72100", .data =3D &riic_rz_a1h_info, = }, { .compatible =3D "renesas,riic-r9a09g057", .data =3D &riic_rz_v2h_info }, + { .compatible =3D "renesas,riic-r9a09g077", .data =3D &riic_rz_t2h_info }, { .compatible =3D "renesas,riic-rz", .data =3D &riic_rz_a_info }, { /* Sentinel */ } }; --=20 2.49.0