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Wed, 25 Jun 2025 02:21:29 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 25 Jun 2025 02:21:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 25 Jun 2025 02:21:28 -0700 Received: from test-OptiPlex-Tower-Plus-7010.marvell.com (unknown [10.29.37.157]) by maili.marvell.com (Postfix) with ESMTP id 0B1B63F705E; Wed, 25 Jun 2025 02:21:16 -0700 (PDT) From: Hariprasad Kelam To: , CC: , , , , , , , , , , , , Subject: [net-next 1/3] Octeontx-pf: Update SGMII mode mapping Date: Wed, 25 Jun 2025 14:51:05 +0530 Message-ID: <20250625092107.9746-2-hkelam@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625092107.9746-1-hkelam@marvell.com> References: <20250625092107.9746-1-hkelam@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI1MDA2OSBTYWx0ZWRfX4vFFUsws+BMa LZlnC0hWZmsq6+DiiNE3A95ESH5Bps4FQQng74ZN8SCKLSpFNvqjUlqLduPCPaDhuS21+A2zaax R0flaf3nFwezGBPDbabVvHezMt3HHjg30Z1gFNX1sX+AmdcCXuYrY/X218jFOlftrqxbTIQ88IU 5QK8WMeb7DP+8EYZ5AOl9DbsNpimPhhFGLdYPGb+qC5EpDzaW9L3oaCgIOTB3Mmymh7syL4s7TN QSwIzovPMb7Uf4kCVBhFl+oep2OkEeIKZ5liypqWe5r63JLh3udrhFNTeZkVcmhSeR4yd/dYQCK zfeW0iAdAFYXJWniNMiC440OaDZjwCkNSK9FXNOVEqCWSV/ALGXQjCuqSaqs3sg3uTWwEIHjWL+ fvwmIn3TgdDmGo1mqpXVUxus7HI5p5fLK0c05hqDJM4M7/xB25envvRLWqkV6sryMLRdLAa8 X-Authority-Analysis: v=2.4 cv=EoTSrTcA c=1 sm=1 tr=0 ts=685bbf99 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=6IFa9wvqVegA:10 a=M5GUcnROAAAA:8 a=IFoFaaN2sayDEy6T10wA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: 5Y7uyyMq7W2jdBH2Cn0CSU8u8WdhbeTL X-Proofpoint-GUID: 5Y7uyyMq7W2jdBH2Cn0CSU8u8WdhbeTL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-25_02,2025-06-23_07,2025-03-28_01 Content-Type: text/plain; charset="utf-8" Current implementation maps ethtool link modes 10baseT/100baseT/1000baseT to single firmware mode SGMII. This create a problem for end users who want to advertise only one speed among them. This patch addresses the issue by mapping each ethtool link mode to a corresponding firmware mode also updates new modes supported by firmware. Signed-off-by: Hariprasad Kelam --- .../net/ethernet/marvell/octeontx2/af/cgx.c | 8 ++--- .../ethernet/marvell/octeontx2/af/cgx_fw_if.h | 26 ++++++++++++++- .../marvell/octeontx2/nic/otx2_ethtool.c | 32 +++++++++---------- 3 files changed, 44 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/= ethernet/marvell/octeontx2/af/cgx.c index 971993586fb4..ac30b6dcb5e5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c @@ -1200,16 +1200,16 @@ static void otx2_map_ethtool_link_modes(u64 bitmask, { switch (bitmask) { case ETHTOOL_LINK_MODE_10baseT_Half_BIT: - set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII)); + set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT)); break; case ETHTOOL_LINK_MODE_10baseT_Full_BIT: - set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII)); + set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT)); break; case ETHTOOL_LINK_MODE_100baseT_Half_BIT: - set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII)); + set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT)); break; case ETHTOOL_LINK_MODE_100baseT_Full_BIT: - set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII)); + set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT)); break; case ETHTOOL_LINK_MODE_1000baseT_Half_BIT: set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII)); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/driver= s/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h index d4a27c882a5b..da21a6f847cf 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h @@ -95,7 +95,31 @@ enum CGX_MODE_ { CGX_MODE_100G_C2M, CGX_MODE_100G_CR4, CGX_MODE_100G_KR4, - CGX_MODE_MAX /* =3D 29 */ + CGX_MODE_LAUI_2_C2C_BIT, + CGX_MODE_LAUI_2_C2M_BIT, + CGX_MODE_50GBASE_CR2_C_BIT, + CGX_MODE_50GBASE_KR2_C_BIT, /* =3D 30 */ + CGX_MODE_100GAUI_2_C2C_BIT, + CGX_MODE_100GAUI_2_C2M_BIT, + CGX_MODE_100GBASE_CR2_BIT, + CGX_MODE_100GBASE_KR2_BIT, + CGX_MODE_SFI_1G_BIT, + CGX_MODE_25GBASE_CR_C_BIT, + CGX_MODE_25GBASE_KR_C_BIT, + CGX_MODE_SGMII_10M_BIT, + CGX_MODE_SGMII_100M_BIT, /* =3D 39 */ + CGX_MODE_2500_BASEX_BIT =3D 42, /* Mode group 1 */ + CGX_MODE_5000_BASEX_BIT, + CGX_MODE_O_USGMII_BIT, + CGX_MODE_Q_USGMII_BIT, + CGX_MODE_2_5G_USXGMII_BIT, + CGX_MODE_5G_USXGMII_BIT, + CGX_MODE_10G_SXGMII_BIT, + CGX_MODE_10G_DXGMII_BIT, + CGX_MODE_10G_QXGMII_BIT, + CGX_MODE_TP_BIT, + CGX_MODE_FIBER_BIT, + CGX_MODE_MAX /* =3D 53 */ }; /* REQUEST ID types. Input to firmware */ enum cgx_cmd_id { diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c index 9b7f847b9c22..ae1cdd51b9fb 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c @@ -15,6 +15,7 @@ =20 #include "otx2_common.h" #include "otx2_ptp.h" +#include =20 #define DRV_NAME "rvu-nicpf" #define DRV_VF_NAME "rvu-nicvf" @@ -1126,17 +1127,9 @@ static void otx2_get_link_mode_info(u64 link_mode_bm= ap, *link_ksettings) { __ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_link_modes) =3D { 0, }; - const int otx2_sgmii_features[6] =3D { - ETHTOOL_LINK_MODE_10baseT_Half_BIT, - ETHTOOL_LINK_MODE_10baseT_Full_BIT, - ETHTOOL_LINK_MODE_100baseT_Half_BIT, - ETHTOOL_LINK_MODE_100baseT_Full_BIT, - ETHTOOL_LINK_MODE_1000baseT_Half_BIT, - ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - }; /* CGX link modes to Ethtool link mode mapping */ - const int cgx_link_mode[27] =3D { - 0, /* SGMII Mode */ + const int cgx_link_mode[CGX_MODE_MAX] =3D { + 0, /* SGMII 1000baseT */ ETHTOOL_LINK_MODE_1000baseX_Full_BIT, ETHTOOL_LINK_MODE_10000baseT_Full_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, @@ -1166,14 +1159,19 @@ static void otx2_get_link_mode_info(u64 link_mode_b= map, }; u8 bit; =20 - for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, 27) { - /* SGMII mode is set */ - if (bit =3D=3D 0) - linkmode_set_bit_array(otx2_sgmii_features, - ARRAY_SIZE(otx2_sgmii_features), - otx2_link_modes); - else + for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, ARRAY_SIZE(cgx_li= nk_mode)) { + if (bit =3D=3D CGX_MODE_SGMII_10M_BIT) { + linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, otx2_link_modes); + linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, otx2_link_modes); + } else if (bit =3D=3D CGX_MODE_SGMII_100M_BIT) { + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, otx2_link_modes); + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, otx2_link_modes); + } else if (bit =3D=3D CGX_MODE_SGMII) { + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, otx2_link_modes); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, otx2_link_modes); + } else { linkmode_set_bit(cgx_link_mode[bit], otx2_link_modes); + } } =20 if (req_mode =3D=3D OTX2_MODE_ADVERTISED) --=20 2.34.1