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Wed, 25 Jun 2025 02:21:29 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 25 Jun 2025 02:21:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 25 Jun 2025 02:21:28 -0700 Received: from test-OptiPlex-Tower-Plus-7010.marvell.com (unknown [10.29.37.157]) by maili.marvell.com (Postfix) with ESMTP id 0B1B63F705E; Wed, 25 Jun 2025 02:21:16 -0700 (PDT) From: Hariprasad Kelam To: , CC: , , , , , , , , , , , , Subject: [net-next 1/3] Octeontx-pf: Update SGMII mode mapping Date: Wed, 25 Jun 2025 14:51:05 +0530 Message-ID: <20250625092107.9746-2-hkelam@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250625092107.9746-1-hkelam@marvell.com> References: <20250625092107.9746-1-hkelam@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI1MDA2OSBTYWx0ZWRfX4vFFUsws+BMa LZlnC0hWZmsq6+DiiNE3A95ESH5Bps4FQQng74ZN8SCKLSpFNvqjUlqLduPCPaDhuS21+A2zaax R0flaf3nFwezGBPDbabVvHezMt3HHjg30Z1gFNX1sX+AmdcCXuYrY/X218jFOlftrqxbTIQ88IU 5QK8WMeb7DP+8EYZ5AOl9DbsNpimPhhFGLdYPGb+qC5EpDzaW9L3oaCgIOTB3Mmymh7syL4s7TN QSwIzovPMb7Uf4kCVBhFl+oep2OkEeIKZ5liypqWe5r63JLh3udrhFNTeZkVcmhSeR4yd/dYQCK zfeW0iAdAFYXJWniNMiC440OaDZjwCkNSK9FXNOVEqCWSV/ALGXQjCuqSaqs3sg3uTWwEIHjWL+ fvwmIn3TgdDmGo1mqpXVUxus7HI5p5fLK0c05hqDJM4M7/xB25envvRLWqkV6sryMLRdLAa8 X-Authority-Analysis: v=2.4 cv=EoTSrTcA c=1 sm=1 tr=0 ts=685bbf99 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=6IFa9wvqVegA:10 a=M5GUcnROAAAA:8 a=IFoFaaN2sayDEy6T10wA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: 5Y7uyyMq7W2jdBH2Cn0CSU8u8WdhbeTL X-Proofpoint-GUID: 5Y7uyyMq7W2jdBH2Cn0CSU8u8WdhbeTL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-25_02,2025-06-23_07,2025-03-28_01 Content-Type: text/plain; charset="utf-8" Current implementation maps ethtool link modes 10baseT/100baseT/1000baseT to single firmware mode SGMII. This create a problem for end users who want to advertise only one speed among them. This patch addresses the issue by mapping each ethtool link mode to a corresponding firmware mode also updates new modes supported by firmware. Signed-off-by: Hariprasad Kelam --- .../net/ethernet/marvell/octeontx2/af/cgx.c | 8 ++--- .../ethernet/marvell/octeontx2/af/cgx_fw_if.h | 26 ++++++++++++++- .../marvell/octeontx2/nic/otx2_ethtool.c | 32 +++++++++---------- 3 files changed, 44 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/= ethernet/marvell/octeontx2/af/cgx.c index 971993586fb4..ac30b6dcb5e5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c @@ -1200,16 +1200,16 @@ static void otx2_map_ethtool_link_modes(u64 bitmask, { switch (bitmask) { case ETHTOOL_LINK_MODE_10baseT_Half_BIT: - set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII)); + set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT)); break; case ETHTOOL_LINK_MODE_10baseT_Full_BIT: - set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII)); + set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII_10M_BIT)); break; case ETHTOOL_LINK_MODE_100baseT_Half_BIT: - set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII)); + set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT)); break; case ETHTOOL_LINK_MODE_100baseT_Full_BIT: - set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII)); + set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII_100M_BIT)); break; case ETHTOOL_LINK_MODE_1000baseT_Half_BIT: set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII)); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/driver= s/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h index d4a27c882a5b..da21a6f847cf 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h @@ -95,7 +95,31 @@ enum CGX_MODE_ { CGX_MODE_100G_C2M, CGX_MODE_100G_CR4, CGX_MODE_100G_KR4, - CGX_MODE_MAX /* =3D 29 */ + CGX_MODE_LAUI_2_C2C_BIT, + CGX_MODE_LAUI_2_C2M_BIT, + CGX_MODE_50GBASE_CR2_C_BIT, + CGX_MODE_50GBASE_KR2_C_BIT, /* =3D 30 */ + CGX_MODE_100GAUI_2_C2C_BIT, + CGX_MODE_100GAUI_2_C2M_BIT, + CGX_MODE_100GBASE_CR2_BIT, + CGX_MODE_100GBASE_KR2_BIT, + CGX_MODE_SFI_1G_BIT, + CGX_MODE_25GBASE_CR_C_BIT, + CGX_MODE_25GBASE_KR_C_BIT, + CGX_MODE_SGMII_10M_BIT, + CGX_MODE_SGMII_100M_BIT, /* =3D 39 */ + CGX_MODE_2500_BASEX_BIT =3D 42, /* Mode group 1 */ + CGX_MODE_5000_BASEX_BIT, + CGX_MODE_O_USGMII_BIT, + CGX_MODE_Q_USGMII_BIT, + CGX_MODE_2_5G_USXGMII_BIT, + CGX_MODE_5G_USXGMII_BIT, + CGX_MODE_10G_SXGMII_BIT, + CGX_MODE_10G_DXGMII_BIT, + CGX_MODE_10G_QXGMII_BIT, + CGX_MODE_TP_BIT, + CGX_MODE_FIBER_BIT, + CGX_MODE_MAX /* =3D 53 */ }; /* REQUEST ID types. Input to firmware */ enum cgx_cmd_id { diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c index 9b7f847b9c22..ae1cdd51b9fb 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c @@ -15,6 +15,7 @@ =20 #include "otx2_common.h" #include "otx2_ptp.h" +#include =20 #define DRV_NAME "rvu-nicpf" #define DRV_VF_NAME "rvu-nicvf" @@ -1126,17 +1127,9 @@ static void otx2_get_link_mode_info(u64 link_mode_bm= ap, *link_ksettings) { __ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_link_modes) =3D { 0, }; - const int otx2_sgmii_features[6] =3D { - ETHTOOL_LINK_MODE_10baseT_Half_BIT, - ETHTOOL_LINK_MODE_10baseT_Full_BIT, - ETHTOOL_LINK_MODE_100baseT_Half_BIT, - ETHTOOL_LINK_MODE_100baseT_Full_BIT, - ETHTOOL_LINK_MODE_1000baseT_Half_BIT, - ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - }; /* CGX link modes to Ethtool link mode mapping */ - const int cgx_link_mode[27] =3D { - 0, /* SGMII Mode */ + const int cgx_link_mode[CGX_MODE_MAX] =3D { + 0, /* SGMII 1000baseT */ ETHTOOL_LINK_MODE_1000baseX_Full_BIT, ETHTOOL_LINK_MODE_10000baseT_Full_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, @@ -1166,14 +1159,19 @@ static void otx2_get_link_mode_info(u64 link_mode_b= map, }; u8 bit; =20 - for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, 27) { - /* SGMII mode is set */ - if (bit =3D=3D 0) - linkmode_set_bit_array(otx2_sgmii_features, - ARRAY_SIZE(otx2_sgmii_features), - otx2_link_modes); - else + for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, ARRAY_SIZE(cgx_li= nk_mode)) { + if (bit =3D=3D CGX_MODE_SGMII_10M_BIT) { + linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, otx2_link_modes); + linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, otx2_link_modes); + } else if (bit =3D=3D CGX_MODE_SGMII_100M_BIT) { + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, otx2_link_modes); + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, otx2_link_modes); + } else if (bit =3D=3D CGX_MODE_SGMII) { + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, otx2_link_modes); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, otx2_link_modes); + } else { linkmode_set_bit(cgx_link_mode[bit], otx2_link_modes); + } } =20 if (req_mode =3D=3D OTX2_MODE_ADVERTISED) --=20 2.34.1 From nobody Wed Oct 8 19:15:18 2025 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDC0429E105; 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charset="utf-8" Kernel and firmware communicates via scratch register which is 64 bit in size. [MODE_ID PORT AUTONEG DUPLEX SPEED CMD_ID OWNERSHIP ] 63-22 21-14 13 12 11-8 7-2 1-0 The existing MODE_ID bitmap can only support up to 42 modes. To resolve the issue, the unused port field is modified as below uint64_t reserved2:6; uint64_t mode_group_idx:2; 'mode_group_idx' categorize the mode ID range to accommodate more modes. To specify mode ID range of 0 - 41, this field will be 0. To specify mode ID range of 42 - 83, this field will be 1. mode ID will be still mentioned as 1 << (0 - 41). But the mode_group_idx decides the actual mode range Signed-off-by: Hariprasad Kelam --- drivers/net/ethernet/marvell/octeontx2/af/cgx.c | 17 +++++++++++++++-- .../ethernet/marvell/octeontx2/af/cgx_fw_if.h | 7 ++++++- .../net/ethernet/marvell/octeontx2/af/mbox.h | 2 +- 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/= ethernet/marvell/octeontx2/af/cgx.c index ac30b6dcb5e5..5c2435f39308 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c @@ -1182,6 +1182,9 @@ static int cgx_link_usertable_index_map(int speed) static void set_mod_args(struct cgx_set_link_mode_args *args, u32 speed, u8 duplex, u8 autoneg, u64 mode) { + int mode_baseidx; + u8 cgx_mode; + /* Fill default values incase of user did not pass * valid parameters */ @@ -1191,8 +1194,18 @@ static void set_mod_args(struct cgx_set_link_mode_ar= gs *args, args->speed =3D speed; if (args->an =3D=3D AUTONEG_UNKNOWN) args->an =3D autoneg; + + /* Derive mode_base_idx and mode fields based + * on cgx_mode value + */ + cgx_mode =3D find_first_bit((unsigned long *)&mode, + CGX_MODE_MAX); args->mode =3D mode; - args->ports =3D 0; + mode_baseidx =3D cgx_mode - 41; + if (mode_baseidx > 0) { + args->mode_baseidx =3D 1; + args->mode =3D BIT_ULL(mode_baseidx); + } } =20 static void otx2_map_ethtool_link_modes(u64 bitmask, @@ -1499,7 +1512,7 @@ int cgx_set_link_mode(void *cgxd, struct cgx_set_link= _mode_args args, cgx_link_usertable_index_map(args.speed), req); req =3D FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req); req =3D FIELD_SET(CMDMODECHANGE_AN, args.an, req); - req =3D FIELD_SET(CMDMODECHANGE_PORT, args.ports, req); + req =3D FIELD_SET(CMDMODECHANGE_MODE_BASEIDX, args.mode_baseidx, req); req =3D FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req); =20 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/driver= s/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h index da21a6f847cf..39352d451cc3 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h @@ -282,7 +282,12 @@ struct cgx_lnk_sts { #define CMDMODECHANGE_SPEED GENMASK_ULL(11, 8) #define CMDMODECHANGE_DUPLEX GENMASK_ULL(12, 12) #define CMDMODECHANGE_AN GENMASK_ULL(13, 13) -#define CMDMODECHANGE_PORT GENMASK_ULL(21, 14) +/* this field categorize the mode ID(FLAGS) range to accommodate + * more modes. + * To specify mode ID range of 0 - 41, this field will be 0. + * To specify mode ID range of 42 - 83, this field will be 1. + */ +#define CMDMODECHANGE_MODE_BASEIDX GENMASK_ULL(21, 20) #define CMDMODECHANGE_FLAGS GENMASK_ULL(63, 22) =20 /* LINK_BRING_UP command timeout */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index b3562d658d45..2fc6b0ba7494 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -675,7 +675,7 @@ struct cgx_set_link_mode_args { u32 speed; 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charset="utf-8" Current implementation considers only first advertise mode and passes the same to firmware to process. This patch extends code such that user can advertise multiple modes on the given interface. Below are high level changes: 1. Remove unnecessary speed/duplex/autoneg validation as its already verified as part of "set_link_ksettings" 2. Since scratch csr framework designed to support single mode at a time, use "shared firmware data" for multi mode support. Signed-off-by: Hariprasad Kelam --- .../net/ethernet/marvell/octeontx2/af/cgx.c | 32 +++++++++++-------- .../net/ethernet/marvell/octeontx2/af/cgx.h | 1 + .../net/ethernet/marvell/octeontx2/af/mbox.h | 7 ++-- .../ethernet/marvell/octeontx2/af/rvu_cgx.c | 9 +++++- .../marvell/octeontx2/nic/otx2_ethtool.c | 30 ++++++++--------- 5 files changed, 48 insertions(+), 31 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/= ethernet/marvell/octeontx2/af/cgx.c index 5c2435f39308..846ee2b9edf1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c @@ -1185,15 +1185,10 @@ static void set_mod_args(struct cgx_set_link_mode_a= rgs *args, int mode_baseidx; u8 cgx_mode; =20 - /* Fill default values incase of user did not pass - * valid parameters - */ - if (args->duplex =3D=3D DUPLEX_UNKNOWN) - args->duplex =3D duplex; - if (args->speed =3D=3D SPEED_UNKNOWN) - args->speed =3D speed; - if (args->an =3D=3D AUTONEG_UNKNOWN) - args->an =3D autoneg; + if (args->multimode) { + args->mode |=3D mode; + return; + } =20 /* Derive mode_base_idx and mode fields based * on cgx_mode value @@ -1494,18 +1489,29 @@ int cgx_get_fwdata_base(u64 *base) } =20 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, + struct cgx_lmac_fwdata_s *linkmodes, int cgx_id, int lmac_id) { struct cgx *cgx =3D cgxd; u64 req =3D 0, resp; + u8 bit; =20 if (!cgx) return -ENODEV; =20 - if (args.mode) - otx2_map_ethtool_link_modes(args.mode, &args); - if (!args.speed && args.duplex && !args.an) - return -EINVAL; + for_each_set_bit(bit, args.advertising, + __ETHTOOL_LINK_MODE_MASK_NBITS) + otx2_map_ethtool_link_modes(bit, &args); + + if (args.multimode) { + if (linkmodes->advertised_link_modes_own !=3D CGX_CMD_OWN_NS) + return -EBUSY; + + linkmodes->advertised_link_modes =3D args.mode; + /* Update ownership */ + linkmodes->advertised_link_modes_own =3D CGX_CMD_OWN_FIRMWARE; + args.mode =3D GENMASK_ULL(41, 0); + } =20 req =3D FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req); req =3D FIELD_SET(CMDMODECHANGE_SPEED, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/= ethernet/marvell/octeontx2/af/cgx.h index 1cf12e5c7da8..950231e7ea71 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h @@ -171,6 +171,7 @@ int cgx_set_fec(u64 fec, int cgx_id, int lmac_id); int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *r= sp); int cgx_get_phy_fec_stats(void *cgxd, int lmac_id); int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, + struct cgx_lmac_fwdata_s *linkmodes, int cgx_id, int lmac_id); u64 cgx_features_get(void *cgxd); struct mac_ops *get_mac_ops(void *cgxd); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 2fc6b0ba7494..0bc0dc79868b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -10,6 +10,7 @@ =20 #include #include +#include =20 #include "rvu_struct.h" #include "common.h" @@ -658,7 +659,8 @@ struct cgx_lmac_fwdata_s { u64 supported_link_modes; /* only applicable if AN is supported */ u64 advertised_fec; - u64 advertised_link_modes; + u64 advertised_link_modes_own:1; /* CGX_CMD_OWN */ + u64 advertised_link_modes:63; /* Only applicable if SFP/QSFP slot is present */ struct sfp_eeprom_s sfp_eeprom; struct phy_s phy; @@ -676,11 +678,12 @@ struct cgx_set_link_mode_args { u8 duplex; u8 an; u8 mode_baseidx; + u8 multimode; u64 mode; + __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); }; =20 struct cgx_set_link_mode_req { -#define AUTONEG_UNKNOWN 0xff struct mbox_msghdr hdr; struct cgx_set_link_mode_args args; }; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_cgx.c index b79db887ab9b..890a1a5df2de 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c @@ -1223,6 +1223,7 @@ int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rv= u, struct cgx_set_link_mode_rsp *rsp) { int pf =3D rvu_get_pf(rvu->pdev, req->hdr.pcifunc); + struct cgx_lmac_fwdata_s *linkmodes; u8 cgx_idx, lmac; void *cgxd; =20 @@ -1231,7 +1232,13 @@ int rvu_mbox_handler_cgx_set_link_mode(struct rvu *r= vu, =20 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); cgxd =3D rvu_cgx_pdata(cgx_idx, rvu); - rsp->status =3D cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac); + if (rvu->hw->lmac_per_cgx =3D=3D CGX_LMACS_USX) + linkmodes =3D &rvu->fwdata->cgx_fw_data_usx[cgx_idx][lmac]; + else + linkmodes =3D &rvu->fwdata->cgx_fw_data[cgx_idx][lmac]; + + rsp->status =3D cgx_set_link_mode(cgxd, req->args, linkmodes, + cgx_idx, lmac); return 0; } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c index ae1cdd51b9fb..20de517dfb09 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c @@ -1212,23 +1212,10 @@ static int otx2_get_link_ksettings(struct net_devic= e *netdev, return 0; } =20 -static void otx2_get_advertised_mode(const struct ethtool_link_ksettings *= cmd, - u64 *mode) -{ - u32 bit_pos; - - /* Firmware does not support requesting multiple advertised modes - * return first set bit - */ - bit_pos =3D find_first_bit(cmd->link_modes.advertising, - __ETHTOOL_LINK_MODE_MASK_NBITS); - if (bit_pos !=3D __ETHTOOL_LINK_MODE_MASK_NBITS) - *mode =3D bit_pos; -} - static int otx2_set_link_ksettings(struct net_device *netdev, const struct ethtool_link_ksettings *cmd) { + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) =3D { 0, }; struct otx2_nic *pf =3D netdev_priv(netdev); struct ethtool_link_ksettings cur_ks; struct cgx_set_link_mode_req *req; @@ -1265,7 +1252,20 @@ static int otx2_set_link_ksettings(struct net_device= *netdev, */ req->args.duplex =3D cmd->base.duplex ^ 0x1; req->args.an =3D cmd->base.autoneg; - otx2_get_advertised_mode(cmd, &req->args.mode); + /* Mask unsupported modes and send message to AF */ + linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mask); + linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mask); + linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mask); + + linkmode_copy(req->args.advertising, + cmd->link_modes.advertising); + linkmode_andnot(req->args.advertising, + req->args.advertising, mask); + + /* inform AF that we need parse this differently */ + if (bitmap_weight(req->args.advertising, + __ETHTOOL_LINK_MODE_MASK_NBITS) >=3D 2) + req->args.multimode =3D true; =20 err =3D otx2_sync_mbox_msg(&pf->mbox); end: --=20 2.34.1