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charset="utf-8" Add PCIe lane equalization preset properties with all values set to 5 for 8.0 GT/s and 16.0 GT/s data rates to enhance link stability. Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Signed-off-by: Ziyue Zhang Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 45f536633f64..16caf1da0708 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7159,6 +7159,9 @@ pcie0: pcie@1c00000 { phys =3D <&pcie0_phy>; phy-names =3D "pciephy"; =20 + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; + status =3D "disabled"; =20 pcieport0: pcie@0 { @@ -7317,6 +7320,9 @@ pcie1: pcie@1c10000 { phys =3D <&pcie1_phy>; phy-names =3D "pciephy"; =20 + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; + status =3D "disabled"; =20 pcie@0 { --=20 2.34.1