From nobody Wed Oct 8 19:15:36 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D6BE264623; Wed, 25 Jun 2025 13:10:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857042; cv=none; b=LoyeBLcXuEpRsgnGqHRsqqw4NcuSDEoAJCqOXs1eQ5OxLpW8DwnCllAccMDSCwW/qRAgWY12jMj0RJ5PtaasymVLxIqWoOZoxkO3xNHJvG8efMHXgU+JvdbaE5eH5An6lnBi5vPcHqsPyMvQyR2cgS3wOABS/LkM6WRNzYc972U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857042; c=relaxed/simple; bh=sRK+Q+xLpf+MdIO7vezUMhN2g5ZN7lwn51lKN+M6MS8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eDFOwZ8pmX+BIbm7fXoamT61Zis3AFYFYdOMsOlHr3tsstMUGggxoyrHuDmMT2pcESNxJkc93yZi79h2sjsuaIHWI2NqoSTw2z1uNhVs/PvwAa+Jl3XQfoIxo+nxBI7E7ruAdbBAPPFZeg56UzpzFJmPoOrJJVGEPeapPbbu4TU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JIAa+TU+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JIAa+TU+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9C0E6C4CEEF; Wed, 25 Jun 2025 13:10:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857041; bh=sRK+Q+xLpf+MdIO7vezUMhN2g5ZN7lwn51lKN+M6MS8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JIAa+TU+sIRwjqRyMhjtTunPx7nYozpLByafudgmcQ2z86YAFZnuVBRwBkvKUFFHa nWjQRMiBNiIy6Z6jBcWTfj8KA470lcnA++PTyehxr875MD3WAOnw3jqfTzJuCIqfyk j+U8TPNBLXrOuas9XS0nQcbJXGX++jPLlGPHfQ3GG9vljGBOtpBBAE2F98ynnc9T9m 1FvyYL8vBglbndyReSnS9CrBQlfvww86rUXcB0YgAKeMDgJrnkbxCKVybHHtt4ZHVx LRdwKADkrEqISfBXb+SRprpX0J3Imu5qmfqKfGirxrNbcTBZ4Dp7NR5gdhCcnKGNXP 8YINJZ236BXCQ== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:13 +0200 Subject: [PATCH v5 05/14] drm/msm/a6xx: Resolve the meaning of AMSBC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-5-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=3390; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=trNEux0uXrdD3pVfEZz/8zHX0JaBDg1rN6itkv7P7tM=; b=5ZdNyRiBsK2wwu/uJQ0hT8IyEg6eKPXodHlSNORTjlqWElWXS8ueDdR1En3mMvRvC34eqUyPM fINBoXH7plHDMLak0fF629pCyeMQ+j3N4VL0iz7JPhmFOgY7RJg7krR X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The bit must be set to 1 if the UBWC encoder version is >=3D 3.0, drop it as a separate field. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 6588a47ea0f0635aaf3944215fa31befb63f4f57..d14c84a0a4b14bf7f77375e619a= c6892374bb3c1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -635,21 +635,16 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) =20 if (adreno_is_a621(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; } =20 if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 16; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.rgb565_predicator =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } =20 - if (adreno_is_a640_family(gpu)) - gpu->ubwc_config.amsbc =3D 1; - if (adreno_is_a680(gpu)) gpu->ubwc_config.macrotile_mode =3D 1; =20 @@ -660,7 +655,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit =3D 16; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.rgb565_predicator =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; @@ -668,7 +662,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) =20 if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.rgb565_predicator =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; @@ -677,7 +670,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) =20 if (adreno_is_7c3(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 14; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } @@ -693,6 +685,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + const struct qcom_ubwc_cfg_data *cfg =3D adreno_gpu->common_ubwc_cfg; /* * We subtract 13 from the highest bank bit (13 is the minimum value * allowed by hw) and write the lowest two bits of the remaining value @@ -700,6 +693,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) */ BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; + bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; u32 hbb_hi =3D hbb >> 2; u32 hbb_lo =3D hbb & 3; u32 ubwc_mode =3D adreno_gpu->ubwc_config.ubwc_swizzle & 1; @@ -708,7 +702,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | adreno_gpu->ubwc_config.rgb565_predicator << 11 | - hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 | + hbb_hi << 10 | amsbc << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); =20 --=20 2.50.0