From nobody Wed Oct 8 19:15:36 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9927265CBE; Wed, 25 Jun 2025 13:10:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857038; cv=none; b=rYKu24As8Lq/fGK9SqP64whm9t/yb9JbYTrZxbKUNi22Wb58wsE/WupmQdLTjeVh4ArIUTPvusms7HuMyrOQ2i0v+HlKWc51sV9FNGxMI6NWBGVIwj51SvYaAbgALPKhedf7Xj/UDyJ+oamKtseE4dHOnhpBq9KcbXg3Z89iaV8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857038; c=relaxed/simple; bh=Cg+8DupBWLyeRJpjZIdQOmGK3HcqSLv3ER/VUAwzlDQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u1/T9N4vy6LDqHi6gnjtyEjbDqslOGiQgEJJsLBPQ9skVdQ8rU8zHj5zc8pgv27nV79q7vux6lGJXlaJW5ceU7o6wUbg0UpC/KuY8pglkzKJQ+RgE4i2VqZhnnhvuXBxFPHa4WA0ApQVK2laPqtUw3+UgAHp2p+WgLA1oxDBoG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pUV8YFKq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pUV8YFKq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57BE1C4CEEE; Wed, 25 Jun 2025 13:10:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857037; bh=Cg+8DupBWLyeRJpjZIdQOmGK3HcqSLv3ER/VUAwzlDQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pUV8YFKqtb6nFtbvpGyPm1OY9FOhOFsCtbNwOm6qEXjR3nc5+4PSGQn9h+GcP8FKk 9c7MHMDrByJ53Vk1yokb4VcORLW+g3S4rw9Ta/EVHWSRG+NkNOBegAeB+MbafZKbOs USTLI+n6l+dhJfX/DCCG2PMEXEvsO69WNRz+g1jnYPqz7Pm6qsFjfvxdj/X1cZ5c3F W75m7lOCD1Tq3Syo3RzdI/4U4anOo7Pm8/FsfhqnMl6EvsGw+vxDLlfGey5XbX3y4W UbzSmh2+q3TmL8lByEQ3Mv8k1rCijZfxQPoLfjTp7f9wxeXVDPaxBSENN1oWH3oCCH M342FIcjXgSMQ== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:12 +0200 Subject: [PATCH v5 04/14] drm/msm/a6xx: Get a handle to the common UBWC config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-4-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=2724; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=3iWBKvs5q5N+qB3FfdC53TcHieKOPEBmf5TENWZJ3pY=; b=aEhYqGuJzlkspWzkso0gsKCoGxzrFGbO+4ef+yrDEDxpDFqgd+n4fZ9xk3ejSEn1GXJyDBser LV5PU8PGCVaDh0s13kMjZgdnMcIJGb4O47rjcpmpYlFKqvkDov6/iI7 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Start the great despaghettification by getting a pointer to the common UBWC configuration, which houses e.g. UBWC versions that we need to make decisions. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 491fde0083a202bec7c6b3bca88d0e5a717a6560..6588a47ea0f0635aaf3944215fa= 31befb63f4f57 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -603,8 +603,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs= [i]); } =20 -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) { + /* Inherit the common config and make some necessary fixups */ + gpu->common_ubwc_cfg =3D qcom_ubwc_config_get_data(); + if (IS_ERR(gpu->common_ubwc_cfg)) + return PTR_ERR(gpu->common_ubwc_cfg); + gpu->ubwc_config.rgb565_predicator =3D 0; gpu->ubwc_config.uavflagprd_inv =3D 0; gpu->ubwc_config.min_acc_len =3D 0; @@ -681,6 +686,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gp= u) gpu->ubwc_config.highest_bank_bit =3D 14; gpu->ubwc_config.min_acc_len =3D 1; } + + return 0; } =20 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) @@ -2564,7 +2571,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a6xx_fault_handler); =20 - a6xx_calc_ubwc_config(adreno_gpu); + ret =3D a6xx_calc_ubwc_config(adreno_gpu); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + /* Set up the preemption specific bits and pieces for each ringbuffer */ a6xx_preempt_init(gpu); =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index bc063594a359ee6b796381c5fd2c30e2aa12a26d..a2a211cac147cb5bc5befdcab07= 559b778adc2bb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -12,6 +12,8 @@ #include #include =20 +#include + #include "msm_gpu.h" =20 #include "adreno_common.xml.h" @@ -243,6 +245,7 @@ struct adreno_gpu { */ u32 macrotile_mode; } ubwc_config; + const struct qcom_ubwc_cfg_data *common_ubwc_cfg; =20 /* * Register offsets are different between some GPUs. --=20 2.50.0