From nobody Wed Oct 8 19:15:36 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B79C263899; Wed, 25 Jun 2025 13:11:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857080; cv=none; b=b0eThnQiPWYn1C/kUMbHFCT5NbkD7P9ru6iVybylR0bqk1HT4QdSXuRT0wju1n81UQ8ahRCNN/m1zRmofB3CfsAfUitW1jzUksnQ/ybuGqLT69H+jXpjfGEAyxCkJpuUtk9N7jIEqS2ePgv8MxorrD9wQQHXe075bTqLN2/0RlA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857080; c=relaxed/simple; bh=MkfZzfoVVNA3pxZuMdbFXVp7BKdKAuZdCsoqILxRvRQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qf28Z5VB5SgCfSyZc35i0aEEwh1jNsBcVsaJg6Wzk/MzPMlfU8rVNYRXkfKXaxkogqel4hYnG6qOZzeRugOqtqrbjCBeehmWUmeevv51t9vYK4bLdffzqrA/ofvrk8w5XaXZa+9+Lv4TU+lSp/pJk4Wws2LmCj0x8HR7rKP4uds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ruqvgjdB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ruqvgjdB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 81CE5C4CEEA; Wed, 25 Jun 2025 13:11:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857080; bh=MkfZzfoVVNA3pxZuMdbFXVp7BKdKAuZdCsoqILxRvRQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ruqvgjdBnqjzAwiksbIIjr7WLNzs0VwEjeUSSyTkcc+5z0EmmxbxbeX8pEsHRMh2a 3Xa7rEBHaGGlaxSFkxWVU6b4OvaUI3BsI9cEh1KHHKxa1w1ScGyPTqzM1qWQ41HbRm VvIlHWt+bvSQE/+WIHGX/U+7/m499veFYErH3Vvso0O0Vlpf0kL+z8HntGQn6n/QOa ICq0V+IUQ0HSHhLp1dS8xiunq09PGyPSY3Tt/QmpFEIRoQgvPSRL/dbdqBAd2L/eLn rjMQ13AQG/+wDr+qFNCU4D5788ap/AePqLhXnitZEq0ny7QNwojMWobSPCLnxmRmS3 2Icvo/6rMHO3A== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:21 +0200 Subject: [PATCH v5 13/14] soc: qcom: ubwc: Fill in UBWC swizzle cfg for platforms that lack one Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-13-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=2912; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=BYjEaeP46UE0oO20FwMEmnGxDtZiOlg0yWNCSte8Gao=; b=CkayZoiAePy0yJDF0unY93ZXDyCSxISrgOG2Kj0wWQkP3zr6T2/4Y+sZP80SyxtX+7TYxHjQ4 aWKedzK/nP5BFNnakHyH8WJGvuPOap9xekZ3/QaNC//cpHkOxmMuXUj X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The UBWC 1.0 case is easy - it must be all 3 enabled. UBWC2.0 and 3.x require that level1 is removed, follow suit. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/ubwc_config.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 7fb18ab067e60a8443d73d31886acc344c11d3b1..dd616342acbe67a76257bbe8b71= 9cc5d18a85f9f 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -15,12 +15,18 @@ static const struct qcom_ubwc_cfg_data msm8937_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_1_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data msm8998_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_1_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 @@ -70,6 +76,8 @@ static const struct qcom_ubwc_cfg_data sc7280_data =3D { static const struct qcom_ubwc_cfg_data sc8180x_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 16, .macrotile_mode =3D true, }; @@ -87,12 +95,16 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = =3D { static const struct qcom_ubwc_cfg_data sdm670_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sdm845_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 @@ -118,6 +130,8 @@ static const struct qcom_ubwc_cfg_data sm6125_data =3D { static const struct qcom_ubwc_cfg_data sm6150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 @@ -133,12 +147,16 @@ static const struct qcom_ubwc_cfg_data sm6350_data = =3D { static const struct qcom_ubwc_cfg_data sm7150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sm8150_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 --=20 2.50.0