From nobody Wed Oct 8 19:15:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EF32263889; Wed, 25 Jun 2025 13:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857075; cv=none; b=V+M5F5tXlT9nPcw0f7/LLdUk4i3RWExxhqgIpRkm5WPFTf+lExTEcTUdynw8/YPo+FjqzI2Eajbm1gLJVUGHIQe4iw6YZMoiOydWy3PlZcu0+9oTYjWLYfNLTjBkkj61xo3FyKxhnIvQ0pXoLbMya+0rDRAMzfsyFYtzb2Ym+KU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857075; c=relaxed/simple; bh=HXejwBHjVhIVdEfA05YFBWpoT919/Xwuxzfki73h1Uc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mIpiC3jMrnnYraIwygF4pIMnbmD5U9YUPn2Fe8Gif4KRBXJqCjwXosxscelc81kezrhKTyazMXNTYNtENxx5zoMkhDPMmD/cVV8sQKyuSN/yCc4LmyPOVQ3TJ45ZKCLw6uMk6xnqbNbV/ACWw9X1Y4JmFTD3oJy/WvpB6E6Oj6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LvMJEDuH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LvMJEDuH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 950D6C4CEEE; Wed, 25 Jun 2025 13:11:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857075; bh=HXejwBHjVhIVdEfA05YFBWpoT919/Xwuxzfki73h1Uc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LvMJEDuHpfIast1vN40E7OCVGuwQjWUGagA77M8Y0Cb1/4sZA3Wb/8j8uTU70s7DP fOPicZgx/IfyrHwAK+mwJy7IroaMo5MD+c0FNEPekdrT6vQZoDAabF3jHqPWJQpZWX Vz8CQlI1rhIKy/ix2QlEgH0sPgGCKBdCrtSA8OjQoRKIP0tAvMNUJTZF1DAER1+sqA fr/NN30g7LGViRZHHb4hFJky6VBz0e2Zjd+wbks++jvAtXsfKvmXYRkcrOtZCU/Beh qu1qjiOTztv5DZE6Dhb6Q3SYq5Qv/VGJHiU0ojNC/nxMiLJeJ1jzEoiCY4wccFKzCX qKbTo9E9qZ9bA== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:20 +0200 Subject: [PATCH v5 12/14] soc: qcom: ubwc: Add #defines for UBWC swizzle bits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-12-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=7400; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=r+76uZPGShAF8TMlEDHNZOPYCTMe3A9KqrCqkJ5zMjY=; b=fiA7G5Qf4HN8+WerGFgF2yBjbtlzRWScsJfGR3I1qCTyJwNPDDJP+/vsoBgAOvc3pcYLSYgGB 39E0xdFtqguCVHlqzpkr6JvWtmCGKILIiljjtJxE4slgEaXnB+CUff/ X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Make the values a bit more meaningful. This commit is intentionally cross-subsystem to ease review, as the patchset is intended to be merged together, with a maintainer consensus. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/soc/qcom/ubwc_config.c | 37 +++++++++++++++++++++++--------= ---- include/linux/soc/qcom/ubwc.h | 8 ++++---- 3 files changed, 30 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e16ad298ba1c11ed5b4c70487bc09e23b2ed5cce..6612030621b1b16c8662d39453b= 609c9c9ff982f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -679,7 +679,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; bool rgb565_predicator =3D cfg->ubwc_enc_version >=3D UBWC_4_0; - u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & BIT(1)); + u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LV= L2); bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; bool min_acc_len_64b =3D false; diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 49ec20901f607b77fb297764b97d75c0537b1db2..7fb18ab067e60a8443d73d31886= acc344c11d3b1 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -32,7 +32,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data =3D { static const struct qcom_ubwc_cfg_data sa8775p_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 4, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, @@ -41,7 +41,8 @@ static const struct qcom_ubwc_cfg_data sa8775p_data =3D { static const struct qcom_ubwc_cfg_data sar2130p_data =3D { .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, @@ -50,7 +51,8 @@ static const struct qcom_ubwc_cfg_data sar2130p_data =3D { static const struct qcom_ubwc_cfg_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -58,7 +60,8 @@ static const struct qcom_ubwc_cfg_data sc7180_data =3D { static const struct qcom_ubwc_cfg_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, .macrotile_mode =3D true, @@ -74,7 +77,8 @@ static const struct qcom_ubwc_cfg_data sc8180x_data =3D { static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 16, .macrotile_mode =3D true, @@ -95,7 +99,9 @@ static const struct qcom_ubwc_cfg_data sdm845_data =3D { static const struct qcom_ubwc_cfg_data sm6115_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 7, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -103,7 +109,9 @@ static const struct qcom_ubwc_cfg_data sm6115_data =3D { static const struct qcom_ubwc_cfg_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_3_0, - .ubwc_swizzle =3D 7, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 @@ -116,7 +124,8 @@ static const struct qcom_ubwc_cfg_data sm6150_data =3D { static const struct qcom_ubwc_cfg_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -136,7 +145,8 @@ static const struct qcom_ubwc_cfg_data sm8150_data =3D { static const struct qcom_ubwc_cfg_data sm8250_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -146,7 +156,8 @@ static const struct qcom_ubwc_cfg_data sm8250_data =3D { static const struct qcom_ubwc_cfg_data sm8350_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -156,7 +167,8 @@ static const struct qcom_ubwc_cfg_data sm8350_data =3D { static const struct qcom_ubwc_cfg_data sm8550_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -176,7 +188,8 @@ static const struct qcom_ubwc_cfg_data sm8750_data =3D { static const struct qcom_ubwc_cfg_data x1e80100_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index 5dc41aafa0afe1fe7f66ae6f8815989663ced780..e6b13980e58d1d120c84acbb90d= b52c007242387 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -21,11 +21,11 @@ struct qcom_ubwc_cfg_data { * UBWC 1.0 always enables all three levels. * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. * UBWC 4.0 adds the optional ability to disable levels 2 & 3. - * - * This is a bitmask where BIT(0) enables level 1, BIT(1) - * controls level 2, and BIT(2) enables level 3. */ u32 ubwc_swizzle; +#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) +#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) +#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) =20 /** * @highest_bank_bit: Highest Bank Bit @@ -66,7 +66,7 @@ static inline bool qcom_ubwc_get_ubwc_mode(const struct q= com_ubwc_cfg_data *cfg) { bool ret =3D cfg->ubwc_enc_version =3D=3D UBWC_1_0; =20 - if (ret && !(cfg->ubwc_swizzle & BIT(0))) + if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1)) pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0= \n"); =20 return ret; --=20 2.50.0