From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 239BF262FDD; Wed, 25 Jun 2025 13:10:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857024; cv=none; b=ORHsaZg4mtYmOiLWFiuy8KoCW3dto8jFtNxbkzlHKfYMl21O8h4gpLOgV8ZACn8U3MFeAU74HiSCwAh6d1r++LMpdwxlQLyQ6KQoAY3g64OSiyy45BeHcyTcYNF8uoTloRbOwchcxAkn11XuKqNkcxVxBcOrO6EJP/s49b/b/WA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857024; c=relaxed/simple; bh=U7rh4Js0zFDR1FYan5mcVUPgdUXX8fWot6B1TjZ9pkU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nl0e6e2DDckDGj0Iwmn1FdbtLEoCgKopOn5Di9q5Udh7pFBAj9Ua1GZ8LDMY27RfOUGwJDbW0KIBxdsMdeQmcekRJ4RgEdySRts+jVpTsApaeJ+abhBcvPXM4ZCCQj4NfWrgdzV5hVDzxFTmHzv31PhcipjDoYDpp36QU0w0yl0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jQH+yt96; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jQH+yt96" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E1489C4CEEE; Wed, 25 Jun 2025 13:10:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857023; bh=U7rh4Js0zFDR1FYan5mcVUPgdUXX8fWot6B1TjZ9pkU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jQH+yt96dUidGFacro86CK4VLyD0mZIJxxC77RlR/EiNc1oHUQcFI+NxC87OiHDcy 0tSLqERhM7w13stV2E58KjXD3T4dbQaxsK3YmVvH2EzaNha/gfDeJNy7X806psQxnD jJfNL8GoNxWUOicSF3YlocfmPteebdm37QFXZCqevxpGCYmoheRL3Iuu6fns4Q93jw t0W3Qi8m5G/Rse6TzpAzzQ7Z7J82HTGQgnvSRdtJLLXsmjW8boWcFsJdj/IHCAikgh ecLyliLU3SPPVmZmcoU1JIjKxQY1OjHB0gA4aKJH8xpSCbFUcOnbMUvVAjYVyjIsU7 gDZOrKDGAZ4ew== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:09 +0200 Subject: [PATCH v5 01/14] soc: qcom: Add UBWC config provider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-1-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=11796; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=3XvaHcsWY/JLjyLUb0KCPBzQ28Hx+QQGadIBNbz9rQg=; b=lSldZ2FKTz0K3eUxa5wV+jFMOqTmzLVdO7NX2v2s19AQyowLf7jEbtvo7DzCcB6QXiraFxeI7 inzNpk7C+FbDnk373Me5NIrVlT1IUNHE+b9MTZL5n+w7zoOPzUqajEK X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Add a file that will serve as a single source of truth for UBWC configuration data for various multimedia blocks. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/Kconfig | 8 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/ubwc_config.c | 247 +++++++++++++++++++++++++++++++++++++= ++++ include/linux/soc/qcom/ubwc.h | 65 +++++++++++ 4 files changed, 321 insertions(+) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 58e63cf0036ba8554e4082da5184a620ca807a9e..2caadbbcf8307ff94f5afbdd148= 1e5e5e291749f 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -296,3 +296,11 @@ config QCOM_PBS PBS trigger event to the PBS RAM. =20 endmenu + +config QCOM_UBWC_CONFIG + tristate + help + Most Qualcomm SoCs feature a number of Universal Bandwidth Compression + (UBWC) engines across various IP blocks, which need to be initialized + with coherent configuration data. This module functions as a single + source of truth for that information. diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index acbca2ab5cc2a9ab3dce1ff38efd048ba2fab31e..b7f1d2a5736748b8772c090fd24= 462fa91f321c6 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_QCOM_ICC_BWMON) +=3D icc-bwmon.o qcom_ice-objs +=3D ice.o obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) +=3D qcom_ice.o obj-$(CONFIG_QCOM_PBS) +=3D qcom-pbs.o +obj-$(CONFIG_QCOM_UBWC_CONFIG) +=3D ubwc_config.o diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c new file mode 100644 index 0000000000000000000000000000000000000000..ef2dfaa6730f7f5cb08bac3cff6= 486e5f3f99570 --- /dev/null +++ b/drivers/soc/qcom/ubwc_config.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include + +static const struct qcom_ubwc_cfg_data msm8937_data =3D { + .ubwc_enc_version =3D UBWC_1_0, + .ubwc_dec_version =3D UBWC_1_0, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data msm8998_data =3D { + .ubwc_enc_version =3D UBWC_1_0, + .ubwc_dec_version =3D UBWC_1_0, + .highest_bank_bit =3D 15, +}; + +static const struct qcom_ubwc_cfg_data qcm2290_data =3D { + /* no UBWC */ + .highest_bank_bit =3D 15, +}; + +static const struct qcom_ubwc_cfg_data sa8775p_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 4, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 13, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sar2130p_data =3D { + .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ + .ubwc_dec_version =3D UBWC_4_3, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 13, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sc7180_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sc7280_data =3D { + .ubwc_enc_version =3D UBWC_3_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 14, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sc8180x_data =3D { + .ubwc_enc_version =3D UBWC_3_0, + .ubwc_dec_version =3D UBWC_3_0, + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sdm670_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sdm845_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .highest_bank_bit =3D 15, +}; + +static const struct qcom_ubwc_cfg_data sm6115_data =3D { + .ubwc_enc_version =3D UBWC_1_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 7, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm6125_data =3D { + .ubwc_enc_version =3D UBWC_1_0, + .ubwc_dec_version =3D UBWC_3_0, + .ubwc_swizzle =3D 1, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm6150_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm6350_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm7150_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .highest_bank_bit =3D 14, +}; + +static const struct qcom_ubwc_cfg_data sm8150_data =3D { + .ubwc_enc_version =3D UBWC_3_0, + .ubwc_dec_version =3D UBWC_3_0, + .highest_bank_bit =3D 15, +}; + +static const struct qcom_ubwc_cfg_data sm8250_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sm8350_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sm8550_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_3, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data sm8750_data =3D { + .ubwc_enc_version =3D UBWC_5_0, + .ubwc_dec_version =3D UBWC_5_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct qcom_ubwc_cfg_data x1e80100_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_3, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + +static const struct of_device_id qcom_ubwc_configs[] __maybe_unused =3D { + { .compatible =3D "qcom,apq8096", .data =3D &msm8998_data }, + { .compatible =3D "qcom,msm8917", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8937", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8953", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8956", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8976", .data =3D &msm8937_data }, + { .compatible =3D "qcom,msm8996", .data =3D &msm8998_data }, + { .compatible =3D "qcom,msm8998", .data =3D &msm8998_data }, + { .compatible =3D "qcom,qcm2290", .data =3D &qcm2290_data, }, + { .compatible =3D "qcom,qcm6490", .data =3D &sc7280_data, }, + { .compatible =3D "qcom,sa8155p", .data =3D &sm8150_data, }, + { .compatible =3D "qcom,sa8540p", .data =3D &sc8280xp_data, }, + { .compatible =3D "qcom,sa8775p", .data =3D &sa8775p_data, }, + { .compatible =3D "qcom,sar2130p", .data =3D &sar2130p_data }, + { .compatible =3D "qcom,sc7180", .data =3D &sc7180_data }, + { .compatible =3D "qcom,sc7280", .data =3D &sc7280_data, }, + { .compatible =3D "qcom,sc8180x", .data =3D &sc8180x_data, }, + { .compatible =3D "qcom,sc8280xp", .data =3D &sc8280xp_data, }, + { .compatible =3D "qcom,sdm630", .data =3D &msm8937_data }, + { .compatible =3D "qcom,sdm636", .data =3D &msm8937_data }, + { .compatible =3D "qcom,sdm660", .data =3D &msm8937_data }, + { .compatible =3D "qcom,sdm670", .data =3D &sdm670_data, }, + { .compatible =3D "qcom,sdm845", .data =3D &sdm845_data, }, + { .compatible =3D "qcom,sm4250", .data =3D &sm6115_data, }, + { .compatible =3D "qcom,sm6115", .data =3D &sm6115_data, }, + { .compatible =3D "qcom,sm6125", .data =3D &sm6125_data, }, + { .compatible =3D "qcom,sm6150", .data =3D &sm6150_data, }, + { .compatible =3D "qcom,sm6350", .data =3D &sm6350_data, }, + { .compatible =3D "qcom,sm6375", .data =3D &sm6350_data, }, + { .compatible =3D "qcom,sm7125", .data =3D &sc7180_data }, + { .compatible =3D "qcom,sm7150", .data =3D &sm7150_data, }, + { .compatible =3D "qcom,sm8150", .data =3D &sm8150_data, }, + { .compatible =3D "qcom,sm8250", .data =3D &sm8250_data, }, + { .compatible =3D "qcom,sm8350", .data =3D &sm8350_data, }, + { .compatible =3D "qcom,sm8450", .data =3D &sm8350_data, }, + { .compatible =3D "qcom,sm8550", .data =3D &sm8550_data, }, + { .compatible =3D "qcom,sm8650", .data =3D &sm8550_data, }, + { .compatible =3D "qcom,sm8750", .data =3D &sm8750_data, }, + { .compatible =3D "qcom,x1e80100", .data =3D &x1e80100_data, }, + { .compatible =3D "qcom,x1p42100", .data =3D &x1e80100_data, }, + { } +}; + +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void) +{ + const struct of_device_id *match; + struct device_node *root; + + root =3D of_find_node_by_path("/"); + if (!root) + return ERR_PTR(-ENODEV); + + match =3D of_match_node(qcom_ubwc_configs, root); + of_node_put(root); + if (!match) { + pr_err("Couldn't find UBWC config data for this platform!\n"); + return ERR_PTR(-EINVAL); + } + + return match->data; +} diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h new file mode 100644 index 0000000000000000000000000000000000000000..b92fc402638bae85e4e9da2552b= e56ac9ea9b448 --- /dev/null +++ b/include/linux/soc/qcom/ubwc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __QCOM_UBWC_H__ +#define __QCOM_UBWC_H__ + +#include +#include + +struct qcom_ubwc_cfg_data { + u32 ubwc_enc_version; + /* Can be read from MDSS_BASE + 0x58 */ + u32 ubwc_dec_version; + + /** + * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling. + * + * UBWC 1.0 always enables all three levels. + * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. + * UBWC 4.0 adds the optional ability to disable levels 2 & 3. + * + * This is a bitmask where BIT(0) enables level 1, BIT(1) + * controls level 2, and BIT(2) enables level 3. + */ + u32 ubwc_swizzle; + + /** + * @highest_bank_bit: Highest Bank Bit + * + * The Highest Bank Bit value represents the bit of the highest + * DDR bank. This should ideally use DRAM type detection. + */ + int highest_bank_bit; + bool ubwc_bank_spread; + + /** + * @macrotile_mode: Macrotile Mode + * + * Whether to use 4-channel macrotiling mode or the newer + * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is + * 4-channel and 1 is 8-channel. + */ + bool macrotile_mode; +}; + +#define UBWC_1_0 0x10000000 +#define UBWC_2_0 0x20000000 +#define UBWC_3_0 0x30000000 +#define UBWC_4_0 0x40000000 +#define UBWC_4_3 0x40030000 +#define UBWC_5_0 0x50000000 + +#ifdef CONFIG_QCOM_UBWC_CONFIG +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void); +#else +static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(v= oid) +{ + return ERR_PTR(-EOPNOTSUPP); +} +#endif + +#endif /* __QCOM_UBWC_H__ */ --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6896A263F28; Wed, 25 Jun 2025 13:10:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857028; cv=none; b=AC/j8uujKtniHTCI85nnEO4MhAw+qDKBBe4MdG5ZU2gAGL44QHFbRoeTM0HE4ZbzkUdeXj6nOB8ATsZsVZe2QPLFo10ItoyZCFWpGyabw7YonedSOvBxVYAbMg7J07Qui20dAV+JNenPHSLQoRvrsQlvqV8ixs1owALwSCrIUIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857028; c=relaxed/simple; bh=bFXCEdgVhfDMEoqkGoje5SoT0Fo4NnjqAhltzIwdUUA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mZzLB4BNe1zDWeYjeHIlihiC5iMxFaef58I2RaKKJowZgFxkm3si9diSc/COamz2wmxHZrMXvxPHWwVQoRv2LHK1QTNpySqxjeJGRPIFpjX9N5901XpDx8xrapRXKZDF1W3chd/Pzxuy16iGR5kA8VxL6a3r/vvbpvGWGwiOHds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TFGFEVs1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TFGFEVs1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 686D2C4CEEA; Wed, 25 Jun 2025 13:10:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857028; bh=bFXCEdgVhfDMEoqkGoje5SoT0Fo4NnjqAhltzIwdUUA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TFGFEVs1itA8cp1o1GEbTnFCKfPv0xd+tYKJ5h86MYTxGlyUyN4Idtwk+T3bVHyFU nEU2lfDuUU4+sdETou3Vq0KGq95MRocUHXuAMebWtfhKY8CpjBaE1WsOnR46akJund M3PanMkdY04vMDRSkA4YFwSFIvXK5+y/xF5TjCoEpz/NTihEBnBxgK+j/BlcYlfBVy KCnY4x6VIUcF0wc7wqvrPuMYsPdkRRvz3paxaa3mojSd0dVgr6SEQvi58a9hpWD1o9 4cdtxfqlqVPlbapJHb6SsQIjL6hPeMaEicWiHDYGE36r2d6/ZSZwjxFI15ySTJk+rp /y9B+GQBZddfg== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:10 +0200 Subject: [PATCH v5 02/14] drm/msm: Offset MDSS HBB value by 13 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-2-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=7622; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=T2FBWroU738HI/Pia2RKVHq+4tLpLcX1tOA/9NV0Bxg=; b=30+gbFk908d/HvMplBO4zGFPIgkGxPk+6x6LkyzVwaqJI/EtPWIEP4LLiLqnh4D8yVecIZOzy ZDulj8KOxDYCUiRnxehvrVB7bo5SbbtLsa6YVuo1QqctfgzaxX2m+Ku X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The Adreno part of the driver exposes this value to userspace, and the SMEM data source also presents a x+13 value. Keep things coherent and make the value uniform across them. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 52 +++++++++++++++++++++-----------------= ---- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 422da5ebf802676afbfc5f242a5a84e6d488dda1..597c8e64985316763d7ced763c4= c6fdb5da9fb90 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -167,7 +167,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 if (data->ubwc_bank_spread) value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; @@ -182,7 +182,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 if (data->macrotile_mode) value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; @@ -200,7 +200,7 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 if (data->ubwc_bank_spread) value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; @@ -277,9 +277,9 @@ static const struct msm_mdss_data *msm_mdss_generate_md= p5_mdss_data(struct msm_m =20 if (hw_rev =3D=3D MDSS_HW_MSM8996 || hw_rev =3D=3D MDSS_HW_MSM8998) - data->highest_bank_bit =3D 2; + data->highest_bank_bit =3D 15; else - data->highest_bank_bit =3D 1; + data->highest_bank_bit =3D 14; =20 return data; } @@ -593,13 +593,13 @@ static void mdss_remove(struct platform_device *pdev) static const struct msm_mdss_data msm8998_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_1_0, - .highest_bank_bit =3D 2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data qcm2290_data =3D { /* no UBWC */ - .highest_bank_bit =3D 0x2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 @@ -608,7 +608,7 @@ static const struct msm_mdss_data sa8775p_data =3D { .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 4, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0, + .highest_bank_bit =3D 13, .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; @@ -618,7 +618,7 @@ static const struct msm_mdss_data sar2130p_data =3D { .ubwc_dec_version =3D UBWC_4_3, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0, + .highest_bank_bit =3D 13, .macrotile_mode =3D 1, .reg_bus_bw =3D 74000, }; @@ -628,7 +628,7 @@ static const struct msm_mdss_data sc7180_data =3D { .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0x1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 @@ -637,7 +637,7 @@ static const struct msm_mdss_data sc7280_data =3D { .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; @@ -645,7 +645,7 @@ static const struct msm_mdss_data sc7280_data =3D { static const struct msm_mdss_data sc8180x_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; @@ -655,7 +655,7 @@ static const struct msm_mdss_data sc8280xp_data =3D { .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; @@ -663,14 +663,14 @@ static const struct msm_mdss_data sc8280xp_data =3D { static const struct msm_mdss_data sdm670_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data sdm845_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 @@ -679,21 +679,21 @@ static const struct msm_mdss_data sm6350_data =3D { .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data sm7150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 static const struct msm_mdss_data sm8150_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 2, + .highest_bank_bit =3D 15, .reg_bus_bw =3D 76800, }; =20 @@ -702,7 +702,7 @@ static const struct msm_mdss_data sm6115_data =3D { .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 7, .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 0x1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 @@ -710,13 +710,13 @@ static const struct msm_mdss_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_3_0, .ubwc_swizzle =3D 1, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, }; =20 static const struct msm_mdss_data sm6150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 1, + .highest_bank_bit =3D 14, .reg_bus_bw =3D 76800, }; =20 @@ -726,7 +726,7 @@ static const struct msm_mdss_data sm8250_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; @@ -737,7 +737,7 @@ static const struct msm_mdss_data sm8350_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; @@ -748,7 +748,7 @@ static const struct msm_mdss_data sm8550_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 57000, }; @@ -759,7 +759,7 @@ static const struct msm_mdss_data sm8750_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, .reg_bus_bw =3D 57000, }; @@ -770,7 +770,7 @@ static const struct msm_mdss_data x1e80100_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 3, + .highest_bank_bit =3D 16, .macrotile_mode =3D true, /* TODO: Add reg_bus_bw with real value */ }; --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 581782641CC; Wed, 25 Jun 2025 13:10:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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Wed, 25 Jun 2025 13:10:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857032; bh=4rfc0hzad1XXSZ+PRmF5xBVXCwNOCKR+tydVyq9LxR0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PI3V8/wZtsJf0EA3gO8jENF0ddn3Sj8/K+pmMD0uHfyU8F+LnKAL1e0gt1R1PPsAO +qEtbrvxGDF3EZKg+Hg4n8TEQh+lMf2j+ea9WD507e6jScK0zwcfOMH1mGItM2OnoS 6uaxl1rDJQplolSiXZ6sWgSPkF/uVzW6Pk1hIm0oZ3xWandVQSRT9xKqHHvRATMbQ6 bQ4MW8pRs/Ue5D2VlMNIt0gd+I32Jkhf07d3RvsMrRBYTk6KCPTavJpwjxls4SOvfM pmUi2QExZ+owvvnMd3KW3JSJpLoq6A1FJtXb2CEsN7DA25oOGfEovjsL845XoejsCF 4+YpDIFPdLSYg== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:11 +0200 Subject: [PATCH v5 03/14] drm/msm: Use the central UBWC config database Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-3-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=22665; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=hpRHCKsHwApH8Qb6bl0zoHsIj72FPFlp+XpZ2Fb+v9Y=; b=xd6v/7c+LUt30AY1HsHsorFG+Y0Q7puVI7mmrmxs2HXhmsyRw3tUGf9fryL6zOpUH+QG+WQpx PzR8+FtQKBlDCTdTORG65ASvMLD+u1qsFq4oXMPjLy0DY4Nj9BK8Xf5 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio As discussed a lot in the past, the UBWC config must be coherent across a number of IP blocks (currently display and GPU, but it also may/will concern camera/video as the drivers evolve). So far, we've been trying to keep the values reasonable in each of the two drivers separately, but it really make sense to do so centrally, especially given certain fields (e.g. HBB) may need to be gathered dynamically. To reduce room for error, move to fetching the config from a central source, so that the data programmed into the hardware is consistent across all multimedia blocks that request it. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +- drivers/gpu/drm/msm/msm_mdss.c | 338 +++++-------------------= ---- drivers/gpu/drm/msm/msm_mdss.h | 29 --- 10 files changed, 73 insertions(+), 321 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 7f127e2ae44292f8f5c7ff6a9251c3d7ec8c9f58..aa317677b6a8960406635fda058= a6b7d76256a51 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -30,6 +30,7 @@ config DRM_MSM select SHMEM select TMPFS select QCOM_SCM + select QCOM_UBWC_CONFIG select WANT_DEV_COREDUMP select SND_SOC_HDMI_CODEC if SND_SOC select SYNC_FILE diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 7dfd0e0a779535e1f6b003f48188bc90d29d6853..6f1fc790ad6d815ed8a2c9936a4= 0d6e6a0b413a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -10,11 +10,11 @@ #include "dpu_hw_sspp.h" #include "dpu_kms.h" =20 -#include "msm_mdss.h" - #include #include =20 +#include + #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 =20 /* SSPP registers */ @@ -684,7 +684,7 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pi= pe, struct dpu_kms *kms, struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, const struct dpu_sspp_cfg *cfg, void __iomem *addr, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, const struct dpu_mdss_version *mdss_rev) { struct dpu_hw_sspp *hw_pipe; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index ed90e78d178a497ae7e2dc12b09a37c8a3f79621..bdac5c04bf7901b864d5999fb39= 5aa5c90de82f5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops { struct dpu_hw_sspp { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; - const struct msm_mdss_data *ubwc; + const struct qcom_ubwc_cfg_data *ubwc; =20 /* Pipe */ enum dpu_sspp idx; @@ -325,7 +325,7 @@ struct dpu_kms; struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, const struct dpu_sspp_cfg *cfg, void __iomem *addr, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, const struct dpu_mdss_version *mdss_rev); =20 int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms = *kms, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index df9d6a509bcd453978bc2491795a6ef87cc95638..226da68d9a9b26f798b8e6795f2= 994e971b80505 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -20,9 +20,10 @@ #include #include =20 +#include + #include "msm_drv.h" #include "msm_mmu.h" -#include "msm_mdss.h" #include "msm_gem.h" #include "disp/msm_disp_snapshot.h" =20 @@ -1189,10 +1190,10 @@ static int dpu_kms_hw_init(struct msm_kms *kms) goto err_pm_put; } =20 - dpu_kms->mdss =3D msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent); + dpu_kms->mdss =3D qcom_ubwc_config_get_data(); if (IS_ERR(dpu_kms->mdss)) { rc =3D PTR_ERR(dpu_kms->mdss); - DPU_ERROR("failed to get MDSS data: %d\n", rc); + DPU_ERROR("failed to get UBWC config data: %d\n", rc); goto err_pm_put; } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.h index a57ec2ec106083e8f93578e4307e8b13ae549c08..993cf512f8c509ac4e28a60a1a3= 1b262f4a54f98 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -60,7 +60,7 @@ struct dpu_kms { struct msm_kms base; struct drm_device *dev; const struct dpu_mdss_cfg *catalog; - const struct msm_mdss_data *mdss; + const struct qcom_ubwc_cfg_data *mdss; =20 /* io/register spaces: */ void __iomem *mmio, *vbif[VBIF_MAX]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 421138bc3cb779c45fcfd5319056f0d31c862452..ba5a46c5c1b501d22c6b28dd82a= c761c26d08541 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -17,8 +17,9 @@ #include #include =20 +#include + #include "msm_drv.h" -#include "msm_mdss.h" #include "dpu_kms.h" #include "dpu_hw_sspp.h" #include "dpu_hw_util.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index a2219c4f55a45db894ff18c1fd0a810c1a3cf811..25382120cb1a4f2b68b0c657337= 1f75fb8d489ea 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -40,7 +40,7 @@ static inline bool reserved_by_other(uint32_t *res_map, i= nt idx, int dpu_rm_init(struct drm_device *dev, struct dpu_rm *rm, const struct dpu_mdss_cfg *cat, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, void __iomem *mmio) { int rc, i; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.h index aa62966056d489d9c94c61f24051a2f3e7b7ed89..ccd64404f12d3ca3956c8e6df7d= 1ffddd4f20642 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -69,7 +69,7 @@ struct msm_display_topology { int dpu_rm_init(struct drm_device *dev, struct dpu_rm *rm, const struct dpu_mdss_cfg *cat, - const struct msm_mdss_data *mdss_data, + const struct qcom_ubwc_cfg_data *mdss_data, void __iomem *mmio); =20 int dpu_rm_reserve(struct dpu_rm *rm, diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 597c8e64985316763d7ced763c4c6fdb5da9fb90..1f5fe7811e016909282087176a4= 2a2349b21c9c4 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -16,14 +16,17 @@ #include #include =20 -#include "msm_mdss.h" +#include + #include "msm_kms.h" =20 #include =20 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ =20 -#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */ +struct msm_mdss_data { + u32 reg_bus_bw; +}; =20 struct msm_mdss { struct device *dev; @@ -36,7 +39,8 @@ struct msm_mdss { unsigned long enabled_mask; struct irq_domain *domain; } irq_controller; - const struct msm_mdss_data *mdss_data; + const struct qcom_ubwc_cfg_data *mdss_data; + u32 reg_bus_bw; struct icc_path *mdp_path[2]; u32 num_mdp_paths; struct icc_path *reg_bus_path; @@ -165,7 +169,7 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *ms= m_mdss) =20 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 @@ -180,7 +184,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss = *msm_mdss) =20 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 @@ -198,7 +202,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss = *msm_mdss) =20 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); =20 @@ -224,7 +228,7 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss = *msm_mdss) =20 static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss) { - const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + const struct qcom_ubwc_cfg_data *data =3D msm_mdss->mdss_data; u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); =20 @@ -240,69 +244,6 @@ static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss= *msm_mdss) writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); } =20 -#define MDSS_HW_MAJ_MIN \ - (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK) - -#define MDSS_HW_MSM8996 0x1007 -#define MDSS_HW_MSM8937 0x100e -#define MDSS_HW_MSM8953 0x1010 -#define MDSS_HW_MSM8998 0x3000 -#define MDSS_HW_SDM660 0x3002 -#define MDSS_HW_SDM630 0x3003 - -/* - * MDP5 platforms use generic qcom,mdp5 compat string, so we have to gener= ate this data - */ -static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct= msm_mdss *mdss) -{ - struct msm_mdss_data *data; - u32 hw_rev; - - data =3D devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL); - if (!data) - return NULL; - - hw_rev =3D readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION); - hw_rev =3D FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev); - - if (hw_rev =3D=3D MDSS_HW_MSM8996 || - hw_rev =3D=3D MDSS_HW_MSM8937 || - hw_rev =3D=3D MDSS_HW_MSM8953 || - hw_rev =3D=3D MDSS_HW_MSM8998 || - hw_rev =3D=3D MDSS_HW_SDM660 || - hw_rev =3D=3D MDSS_HW_SDM630) { - data->ubwc_dec_version =3D UBWC_1_0; - data->ubwc_enc_version =3D UBWC_1_0; - } - - if (hw_rev =3D=3D MDSS_HW_MSM8996 || - hw_rev =3D=3D MDSS_HW_MSM8998) - data->highest_bank_bit =3D 15; - else - data->highest_bank_bit =3D 14; - - return data; -} - -const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) -{ - struct msm_mdss *mdss; - - if (!dev) - return ERR_PTR(-EINVAL); - - mdss =3D dev_get_drvdata(dev); - - /* - * We could not do it at the probe time, since hw revision register was - * not readable. Fill data structure now for the MDP5 platforms. - */ - if (!mdss->mdss_data && mdss->is_mdp5) - mdss->mdss_data =3D msm_mdss_generate_mdp5_mdss_data(mdss); - - return mdss->mdss_data; -} - static int msm_mdss_enable(struct msm_mdss *msm_mdss) { int ret, i; @@ -315,12 +256,8 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) for (i =3D 0; i < msm_mdss->num_mdp_paths; i++) icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); =20 - if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw) - icc_set_bw(msm_mdss->reg_bus_path, 0, - msm_mdss->mdss_data->reg_bus_bw); - else - icc_set_bw(msm_mdss->reg_bus_path, 0, - DEFAULT_REG_BW); + icc_set_bw(msm_mdss->reg_bus_path, 0, + msm_mdss->reg_bus_bw); =20 ret =3D clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -459,6 +396,7 @@ static int mdp5_mdss_parse_clock(struct platform_device= *pdev, struct clk_bulk_d =20 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool i= s_mdp5) { + const struct msm_mdss_data *mdss_data; struct msm_mdss *msm_mdss; int ret; int irq; @@ -471,7 +409,15 @@ static struct msm_mdss *msm_mdss_init(struct platform_= device *pdev, bool is_mdp5 if (!msm_mdss) return ERR_PTR(-ENOMEM); =20 - msm_mdss->mdss_data =3D of_device_get_match_data(&pdev->dev); + msm_mdss->mdss_data =3D qcom_ubwc_config_get_data(); + if (IS_ERR(msm_mdss->mdss_data)) + return ERR_CAST(msm_mdss->mdss_data); + + mdss_data =3D of_device_get_match_data(&pdev->dev); + if (!mdss_data) + return ERR_PTR(-EINVAL); + + msm_mdss->reg_bus_bw =3D mdss_data->reg_bus_bw; =20 msm_mdss->mmio =3D devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? = "mdss_phys" : "mdss"); if (IS_ERR(msm_mdss->mmio)) @@ -590,217 +536,49 @@ static void mdss_remove(struct platform_device *pdev) msm_mdss_destroy(mdss); } =20 -static const struct msm_mdss_data msm8998_data =3D { - .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_1_0, - .highest_bank_bit =3D 15, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data qcm2290_data =3D { - /* no UBWC */ - .highest_bank_bit =3D 15, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sa8775p_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 4, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 13, - .macrotile_mode =3D true, - .reg_bus_bw =3D 74000, -}; - -static const struct msm_mdss_data sar2130p_data =3D { - .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ - .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 13, - .macrotile_mode =3D 1, - .reg_bus_bw =3D 74000, -}; - -static const struct msm_mdss_data sc7180_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sc7280_data =3D { - .ubwc_enc_version =3D UBWC_3_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 14, - .macrotile_mode =3D true, - .reg_bus_bw =3D 74000, -}; - -static const struct msm_mdss_data sc8180x_data =3D { - .ubwc_enc_version =3D UBWC_3_0, - .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sc8280xp_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sdm670_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sdm845_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 15, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm6350_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm7150_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm8150_data =3D { - .ubwc_enc_version =3D UBWC_3_0, - .ubwc_dec_version =3D UBWC_3_0, - .highest_bank_bit =3D 15, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm6115_data =3D { - .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 7, - .ubwc_bank_spread =3D true, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm6125_data =3D { - .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_3_0, - .ubwc_swizzle =3D 1, - .highest_bank_bit =3D 14, -}; - -static const struct msm_mdss_data sm6150_data =3D { - .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, - .highest_bank_bit =3D 14, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm8250_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 76800, -}; - -static const struct msm_mdss_data sm8350_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 74000, -}; - -static const struct msm_mdss_data sm8550_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, +static const struct msm_mdss_data data_57k =3D { .reg_bus_bw =3D 57000, }; =20 -static const struct msm_mdss_data sm8750_data =3D { - .ubwc_enc_version =3D UBWC_5_0, - .ubwc_dec_version =3D UBWC_5_0, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - .reg_bus_bw =3D 57000, +static const struct msm_mdss_data data_74k =3D { + .reg_bus_bw =3D 74000, }; =20 -static const struct msm_mdss_data x1e80100_data =3D { - .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, - .ubwc_bank_spread =3D true, - /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ - .highest_bank_bit =3D 16, - .macrotile_mode =3D true, - /* TODO: Add reg_bus_bw with real value */ +static const struct msm_mdss_data data_76k8 =3D { + .reg_bus_bw =3D 76800, +}; + +static const struct msm_mdss_data data_153k6 =3D { + .reg_bus_bw =3D 153600, }; =20 static const struct of_device_id mdss_dt_match[] =3D { - { .compatible =3D "qcom,mdss" }, - { .compatible =3D "qcom,msm8998-mdss", .data =3D &msm8998_data }, - { .compatible =3D "qcom,qcm2290-mdss", .data =3D &qcm2290_data }, - { .compatible =3D "qcom,sa8775p-mdss", .data =3D &sa8775p_data }, - { .compatible =3D "qcom,sar2130p-mdss", .data =3D &sar2130p_data }, - { .compatible =3D "qcom,sdm670-mdss", .data =3D &sdm670_data }, - { .compatible =3D "qcom,sdm845-mdss", .data =3D &sdm845_data }, - { .compatible =3D "qcom,sc7180-mdss", .data =3D &sc7180_data }, - { .compatible =3D "qcom,sc7280-mdss", .data =3D &sc7280_data }, - { .compatible =3D "qcom,sc8180x-mdss", .data =3D &sc8180x_data }, - { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &sc8280xp_data }, - { .compatible =3D "qcom,sm6115-mdss", .data =3D &sm6115_data }, - { .compatible =3D "qcom,sm6125-mdss", .data =3D &sm6125_data }, - { .compatible =3D "qcom,sm6150-mdss", .data =3D &sm6150_data }, - { .compatible =3D "qcom,sm6350-mdss", .data =3D &sm6350_data }, - { .compatible =3D "qcom,sm6375-mdss", .data =3D &sm6350_data }, - { .compatible =3D "qcom,sm7150-mdss", .data =3D &sm7150_data }, - { .compatible =3D "qcom,sm8150-mdss", .data =3D &sm8150_data }, - { .compatible =3D "qcom,sm8250-mdss", .data =3D &sm8250_data }, - { .compatible =3D "qcom,sm8350-mdss", .data =3D &sm8350_data }, - { .compatible =3D "qcom,sm8450-mdss", .data =3D &sm8350_data }, - { .compatible =3D "qcom,sm8550-mdss", .data =3D &sm8550_data }, - { .compatible =3D "qcom,sm8650-mdss", .data =3D &sm8550_data}, - { .compatible =3D "qcom,sm8750-mdss", .data =3D &sm8750_data}, - { .compatible =3D "qcom,x1e80100-mdss", .data =3D &x1e80100_data}, + { .compatible =3D "qcom,mdss", .data =3D &data_153k6 }, + { .compatible =3D "qcom,msm8998-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,qcm2290-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sa8775p-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sar2130p-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sdm670-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sdm845-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sc7180-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sc7280-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sc8180x-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sc8280xp-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6115-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6125-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6150-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6350-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm6375-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm7150-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm8150-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm8250-mdss", .data =3D &data_76k8 }, + { .compatible =3D "qcom,sm8350-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sm8450-mdss", .data =3D &data_74k }, + { .compatible =3D "qcom,sm8550-mdss", .data =3D &data_57k }, + { .compatible =3D "qcom,sm8650-mdss", .data =3D &data_57k }, + { .compatible =3D "qcom,sm8750-mdss", .data =3D &data_57k }, + /* TODO: x1e8: Add reg_bus_bw with real value */ + { .compatible =3D "qcom,x1e80100-mdss", .data =3D &data_153k6 }, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h deleted file mode 100644 index dd0160c6ba1a297cea5b87cd8b03895b2aa08213..000000000000000000000000000= 0000000000000 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018, The Linux Foundation - */ - -#ifndef __MSM_MDSS_H__ -#define __MSM_MDSS_H__ - -struct msm_mdss_data { - u32 ubwc_enc_version; - /* can be read from register 0x58 */ - u32 ubwc_dec_version; - u32 ubwc_swizzle; - u32 highest_bank_bit; - bool ubwc_bank_spread; - bool macrotile_mode; - u32 reg_bus_bw; -}; - -#define UBWC_1_0 0x10000000 -#define UBWC_2_0 0x20000000 -#define UBWC_3_0 0x30000000 -#define UBWC_4_0 0x40000000 -#define UBWC_4_3 0x40030000 -#define UBWC_5_0 0x50000000 - -const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev); - -#endif /* __MSM_MDSS_H__ */ --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9927265CBE; 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a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Start the great despaghettification by getting a pointer to the common UBWC configuration, which houses e.g. UBWC versions that we need to make decisions. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 491fde0083a202bec7c6b3bca88d0e5a717a6560..6588a47ea0f0635aaf3944215fa= 31befb63f4f57 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -603,8 +603,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs= [i]); } =20 -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) { + /* Inherit the common config and make some necessary fixups */ + gpu->common_ubwc_cfg =3D qcom_ubwc_config_get_data(); + if (IS_ERR(gpu->common_ubwc_cfg)) + return PTR_ERR(gpu->common_ubwc_cfg); + gpu->ubwc_config.rgb565_predicator =3D 0; gpu->ubwc_config.uavflagprd_inv =3D 0; gpu->ubwc_config.min_acc_len =3D 0; @@ -681,6 +686,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gp= u) gpu->ubwc_config.highest_bank_bit =3D 14; gpu->ubwc_config.min_acc_len =3D 1; } + + return 0; } =20 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) @@ -2564,7 +2571,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a6xx_fault_handler); =20 - a6xx_calc_ubwc_config(adreno_gpu); + ret =3D a6xx_calc_ubwc_config(adreno_gpu); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + /* Set up the preemption specific bits and pieces for each ringbuffer */ a6xx_preempt_init(gpu); =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index bc063594a359ee6b796381c5fd2c30e2aa12a26d..a2a211cac147cb5bc5befdcab07= 559b778adc2bb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -12,6 +12,8 @@ #include #include =20 +#include + #include "msm_gpu.h" =20 #include "adreno_common.xml.h" @@ -243,6 +245,7 @@ struct adreno_gpu { */ u32 macrotile_mode; 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a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The bit must be set to 1 if the UBWC encoder version is >=3D 3.0, drop it as a separate field. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 6588a47ea0f0635aaf3944215fa31befb63f4f57..d14c84a0a4b14bf7f77375e619a= c6892374bb3c1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -635,21 +635,16 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) =20 if (adreno_is_a621(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; } =20 if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 16; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.rgb565_predicator =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } =20 - if (adreno_is_a640_family(gpu)) - gpu->ubwc_config.amsbc =3D 1; - if (adreno_is_a680(gpu)) gpu->ubwc_config.macrotile_mode =3D 1; =20 @@ -660,7 +655,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit =3D 16; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.rgb565_predicator =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; @@ -668,7 +662,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) =20 if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.rgb565_predicator =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; @@ -677,7 +670,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) =20 if (adreno_is_7c3(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 14; - gpu->ubwc_config.amsbc =3D 1; gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } @@ -693,6 +685,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + const struct qcom_ubwc_cfg_data *cfg =3D adreno_gpu->common_ubwc_cfg; /* * We subtract 13 from the highest bank bit (13 is the minimum value * allowed by hw) and write the lowest two bits of the remaining value @@ -700,6 +693,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) */ BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; + bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; u32 hbb_hi =3D hbb >> 2; u32 hbb_lo =3D hbb & 3; u32 ubwc_mode =3D adreno_gpu->ubwc_config.ubwc_swizzle & 1; @@ -708,7 +702,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | adreno_gpu->ubwc_config.rgb565_predicator << 11 | - hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 | + hbb_hi << 10 | amsbc << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); =20 --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DFC0264623; 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a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Instead of setting it on a gpu-per-gpu basis, converge it to the intended "is A650 family or A7xx". Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index d14c84a0a4b14bf7f77375e619ac6892374bb3c1..3d9c98e56d92ed43cf6e702fbd2= b5cbd3293ac5a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -611,7 +611,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) return PTR_ERR(gpu->common_ubwc_cfg); =20 gpu->ubwc_config.rgb565_predicator =3D 0; - gpu->ubwc_config.uavflagprd_inv =3D 0; gpu->ubwc_config.min_acc_len =3D 0; gpu->ubwc_config.ubwc_swizzle =3D 0x6; gpu->ubwc_config.macrotile_mode =3D 0; @@ -633,15 +632,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) if (adreno_is_a619_holi(gpu)) gpu->ubwc_config.highest_bank_bit =3D 13; =20 - if (adreno_is_a621(gpu)) { + if (adreno_is_a621(gpu)) gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.uavflagprd_inv =3D 2; - } =20 if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 16; gpu->ubwc_config.rgb565_predicator =3D 1; - gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } =20 @@ -656,21 +652,18 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit =3D 16; gpu->ubwc_config.rgb565_predicator =3D 1; - gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } =20 if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 13; gpu->ubwc_config.rgb565_predicator =3D 1; - gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; gpu->ubwc_config.ubwc_swizzle =3D 0x4; } =20 if (adreno_is_7c3(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 14; - gpu->ubwc_config.uavflagprd_inv =3D 2; gpu->ubwc_config.macrotile_mode =3D 1; } =20 @@ -694,11 +687,15 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; + u8 uavflagprd_inv =3D 0; u32 hbb_hi =3D hbb >> 2; u32 hbb_lo =3D hbb & 3; u32 ubwc_mode =3D adreno_gpu->ubwc_config.ubwc_swizzle & 1; u32 level2_swizzling_dis =3D !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); =20 + if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) + uavflagprd_inv =3D 2; + gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | adreno_gpu->ubwc_config.rgb565_predicator << 11 | @@ -713,7 +710,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) =20 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, level2_swizzling_dis << 12 | hbb_hi << 10 | - adreno_gpu->ubwc_config.uavflagprd_inv << 4 | + uavflagprd_inv << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); =20 --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8BC625D53E; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zggbwkhl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9DE60C4CEEA; Wed, 25 Jun 2025 13:10:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857050; bh=4+f7GA/otNyWhQwFzv3cN+bRXvAY+QsCJlqjXa4WCbQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Zggbwkhl/imWx1II153ZRhSuyRKcNYTOUYKDyZ89WIP/rDVulNHf3oUs3OJ5IfI8g QPkRedXzK6JnoIzuGfJAs0DMeozBZdMpTLa/itFkX7TonHS39cR7pc8gypj/Z588Dy abgD8ubRSGGgQr6acWXJpfwxSx9TZhye2dNttKpBF2iQC1ARVP90/YtFpH1gmWz2OK ZpNwVnzaLU20uw6u7I7ZwKGHDSWI2rV7E9qBDsCMHSu63T2O+FqohnOTE3/rjCLs9o UdRvkkEgdN6IPQHD5lAUv0Bc6gAYj/8IxFUquAWVeyWnFDghkL2ZgCyhaQf3AbQPpa X0eobgrixNDJw== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:15 +0200 Subject: [PATCH v5 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-7-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=2107; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=gbQdqtBOeisek0R+EbShz3Z9yw3aoUL/2+EsNsZHbj0=; b=/+o6wlnyMk5hrp+/vadcqkO8sHq+NbuPMHdUmYnHhEk3cMwl55Puusn+FBrovmHN0hUq/JAdy njmm6QCaOECDslOrFNm77gsXgieQEjbtBSxI9zb3WcfiCKaJfPsI0pk X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio This bit is set iff the UBWC version is 1.0. That notably does not include QCM2290's "no UBWC". This commit is intentionally cross-subsystem to ease review, as the patchset is intended to be merged together, with a maintainer consensus. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- include/linux/soc/qcom/ubwc.h | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 3d9c98e56d92ed43cf6e702fbd2b5cbd3293ac5a..3d345844337608086ffec1998b4= 7b315ada68a97 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -686,11 +686,11 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) */ BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; + bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; u8 uavflagprd_inv =3D 0; u32 hbb_hi =3D hbb >> 2; u32 hbb_lo =3D hbb & 3; - u32 ubwc_mode =3D adreno_gpu->ubwc_config.ubwc_swizzle & 1; u32 level2_swizzling_dis =3D !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); =20 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index b92fc402638bae85e4e9da2552be56ac9ea9b448..5dc41aafa0afe1fe7f66ae6f881= 5989663ced780 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -62,4 +62,14 @@ static inline const struct qcom_ubwc_cfg_data *qcom_ubwc= _config_get_data(void) } #endif =20 +static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data= *cfg) +{ + bool ret =3D cfg->ubwc_enc_version =3D=3D UBWC_1_0; + + if (ret && !(cfg->ubwc_swizzle & BIT(0))) + pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0= \n"); + + return ret; +} + #endif /* __QCOM_UBWC_H__ */ --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECD4A2620CF; Wed, 25 Jun 2025 13:10:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857056; cv=none; b=pN3pdjSCJXDFlpwpmPOPF87JI/uGqJu4wRlhHeC36IBVr+I5EHEaxbLxSva1nb5cOyXmgTVTQ2wi6Qxpww9ugzwtfZ9EPwdqhRMvLBNjcorWZObnAXusfUZJmGlDY/1QhIsnv2ptN2CJMyzr4+LDfU8BbLfKT4Xyp7JhnXn8Qk4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857056; c=relaxed/simple; bh=GH/kR3kom1SR2DzZhLQydzQqd3+Oq3MgLgPaayrkqBA=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-8-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=1212; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=j6D8eqPjFQVMYlE8pITPkljcLo0t+bJ0APdpU9FQnCs=; b=GrLRZDYs1oQtLzYIS9KzLvNYfA8Qr92qXDwq/nGQP7MoF71QKyN+f9wdjS5ujWq2Qq/Vxwjix wYSlIawBsIxDVtrYiHNZOAaUA/Npe9gC+GKbrm2hWzDfLf0yNw7cpS+ X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio ubwc_swizzle is a bitmask. Check for a bit to make it more obvious. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 3d345844337608086ffec1998b47b315ada68a97..78782f94ee678e13baa6eb1a009= a412e13557d59 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -686,12 +686,12 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) */ BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; + u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & BIT(1)); bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; u8 uavflagprd_inv =3D 0; u32 hbb_hi =3D hbb >> 2; u32 hbb_lo =3D hbb & 3; - u32 level2_swizzling_dis =3D !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); =20 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) uavflagprd_inv =3D 2; --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B98A2609F7; Wed, 25 Jun 2025 13:11:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857061; cv=none; b=fCUs1Ild2inzHKbM+qVdLnhhABZ2h8M0Q0SfC+0ItILt9MrvbP0oocXcEK0wPHzisiUEIyNMmrpxJCcfZnNg9zNyhzEVrFdox67+eO/UKGYeu7JUl4g88Zt0FTNibV0UgB/JudSFPfUPN1ddBCg0p1xQdIYwFFaqZAxGy1gGHzs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857061; c=relaxed/simple; bh=Jzp4H5XI2mNdXY7mf+xttkOOu68Xs66xVgu2w4KaY6c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dWKh2lExq4hiFwCBIaL8UKvUcLC1H8TRiKiA+eXKktNIsp0VliLwExzbQYVhdHHYyd7KKYx3bHLzHglbLqm7qGhyDmCapWMeh8zWwbmx780pMwFhezq/ljY6XbpHRI8nleKiwoipURSzfYWBgbrx/ylnM5frF+YNAb3os1Wmg94= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LTiWWK6y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LTiWWK6y" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 75EBEC4CEEA; Wed, 25 Jun 2025 13:10:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857061; bh=Jzp4H5XI2mNdXY7mf+xttkOOu68Xs66xVgu2w4KaY6c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LTiWWK6y8gbaXagk6u8Unpy/hH9iI8XRKZBMJKcMBcp2IBPYvJxudKZFbF2JxTouL P9m7T7A06zBbot5VGNWVyl1wl/rax21phiWt0/T8V5O46wnDrkb41TbRLLjPx5Gteo Gubl6mBwBeey3B4n/oyuNDXX7Dzq3XHapCmsJWtI9wDhs4aVUHqG/O0wzxDqYi7PmT qJYGtxBUMVM6snRY5EVIZT/hREcuQxZHZZjj9l+Lh0jiZguJ/awofBB6URn3eBSKzk eW8V16MTfKMyAa1e5eSonuqNHT+UhUDsxtAaKuO6JcPJHN1Klm9HWEGWAVsJHfomSC v/7id41v4sB1w== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:17 +0200 Subject: [PATCH v5 09/14] drm/msm/a6xx: Resolve the meaning of rgb565_predicator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-9-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=2509; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=XfAVKpXihNq5QYjqmv6bbx9jLqRnqYwolc2Cu9hDUvU=; b=cZf5zaKtql+E6lptsfMHrBRSoGTZvXv25nzP5qh+HyvX4tmWL1iBmkq6ZEHWeSYv7gMXEZ3Jz SYWgEeFqZtwAoZwr5rni4HVrmObHx3LoZPUhL3/Wr1aktafVXjqyDtu X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio It's supposed to be on when the UBWC encoder version is >=3D 4.0. Drop the per-GPU assignments. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 78782f94ee678e13baa6eb1a009a412e13557d59..53493f68ead2113143dab594bfe= df492014d5aaa 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -610,7 +610,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) if (IS_ERR(gpu->common_ubwc_cfg)) return PTR_ERR(gpu->common_ubwc_cfg); =20 - gpu->ubwc_config.rgb565_predicator =3D 0; gpu->ubwc_config.min_acc_len =3D 0; gpu->ubwc_config.ubwc_swizzle =3D 0x6; gpu->ubwc_config.macrotile_mode =3D 0; @@ -637,7 +636,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) =20 if (adreno_is_a623(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 16; - gpu->ubwc_config.rgb565_predicator =3D 1; gpu->ubwc_config.macrotile_mode =3D 1; } =20 @@ -651,13 +649,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) adreno_is_a740_family(gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ gpu->ubwc_config.highest_bank_bit =3D 16; - gpu->ubwc_config.rgb565_predicator =3D 1; gpu->ubwc_config.macrotile_mode =3D 1; } =20 if (adreno_is_a663(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.rgb565_predicator =3D 1; gpu->ubwc_config.macrotile_mode =3D 1; gpu->ubwc_config.ubwc_swizzle =3D 0x4; } @@ -686,6 +682,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) */ BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; + bool rgb565_predicator =3D cfg->ubwc_enc_version >=3D UBWC_4_0; u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & BIT(1)); bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; @@ -698,7 +695,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) =20 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | - adreno_gpu->ubwc_config.rgb565_predicator << 11 | + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | adreno_gpu->ubwc_config.min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); 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a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio It's only necessary for some lower end parts. Also rename it to min_acc_len_64b to denote that if set, the minimum access length is 64 bits, 32b otherwise. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 53493f68ead2113143dab594bfedf492014d5aaa..e16ad298ba1c11ed5b4c70487bc= 09e23b2ed5cce 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -610,14 +610,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) if (IS_ERR(gpu->common_ubwc_cfg)) return PTR_ERR(gpu->common_ubwc_cfg); =20 - gpu->ubwc_config.min_acc_len =3D 0; gpu->ubwc_config.ubwc_swizzle =3D 0x6; gpu->ubwc_config.macrotile_mode =3D 0; gpu->ubwc_config.highest_bank_bit =3D 15; =20 if (adreno_is_a610(gpu)) { gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.min_acc_len =3D 1; gpu->ubwc_config.ubwc_swizzle =3D 0x7; } =20 @@ -663,10 +661,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gp= u) gpu->ubwc_config.macrotile_mode =3D 1; } =20 - if (adreno_is_a702(gpu)) { + if (adreno_is_a702(gpu)) gpu->ubwc_config.highest_bank_bit =3D 14; - gpu->ubwc_config.min_acc_len =3D 1; - } =20 return 0; } @@ -686,6 +682,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & BIT(1)); bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; + bool min_acc_len_64b =3D false; u8 uavflagprd_inv =3D 0; u32 hbb_hi =3D hbb >> 2; u32 hbb_lo =3D hbb & 3; @@ -693,22 +690,25 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) uavflagprd_inv =3D 2; =20 + if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) + min_acc_len_64b =3D true; + gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, level2_swizzling_dis << 12 | rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); =20 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, level2_swizzling_dis << 6 | hbb_hi << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); =20 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, level2_swizzling_dis << 12 | hbb_hi << 10 | uavflagprd_inv << 4 | - adreno_gpu->ubwc_config.min_acc_len << 3 | + min_acc_len_64b << 3 | hbb_lo << 1 | ubwc_mode); =20 if (adreno_is_a7xx(adreno_gpu)) @@ -716,7 +716,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) FIELD_PREP(GENMASK(8, 5), hbb_lo)); =20 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, - adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); + min_acc_len_64b << 23 | hbb_lo << 21); =20 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, adreno_gpu->ubwc_config.macrotile_mode); --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E442262FDE; Wed, 25 Jun 2025 13:11:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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Wed, 25 Jun 2025 13:11:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857070; bh=5kd46EYzLSIP7jQo4nPGykrQoZ5gksu592EDZaqeOcE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tcoi9vqZ71DsEC7MtmEMv0kufQW4aGgdq1gGExDixPAemvBvIcUH1Z9nHPV7Zk5RR +Ri23cL0jv1l6eZ9hjq8VLLgQh5F3z/eUBgYP+Z3FxBv+ouabfOenA7PPQq+YqTeuo FV5DuYGKrGVFzoAQ5258yeVhzDhvoO3MHa6Sf/teRjlK734v0JgnDPRWVX0DW4o8MD EaLy+ZxgGPPN0rPe/Gek6vU3SUFv4Ph5wU6XnvDxAGFvGh30BH4ADMGxFdgka5Hnc8 DPBKCQEDUfc82TYlrSKPbSBwk8MeWc0MRoV87JFqIfraXVvq8pDwOKPCgYpQQAdk+J ljf+o/6jiDKmQ== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:19 +0200 Subject: [PATCH v5 11/14] soc: qcom: ubwc: Fix SM6125's ubwc_swizzle value Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-11-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=1051; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=boHkhEcS8ujsO8eosjmO/xq6FDYpSswaBWnJ0yziTTc=; b=CzQ//fue3SaXzkihq3Hg7cLtcchvyzO9heR+nRPgSf4915aF09zCmmnZiFPlW7Hx/V2XmkQVu qPhj8GQkJ5zAFuOTrOmCqLue6zycPK9syGflyzggBoJfFlaQnqeCZ8R X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The value of 7 (a.k.a. GENMASK(2, 0), a.k.a. disabling levels 1-3 of swizzling) is what we want on this platform (and others with a UBWC 1.0 encoder). Fix it to make mesa happy (the hardware doesn't care about the 2 higher bits, as they weren't consumed on this platform). Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/ubwc_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index ef2dfaa6730f7f5cb08bac3cff6486e5f3f99570..49ec20901f607b77fb297764b97= d75c0537b1db2 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -103,7 +103,7 @@ static const struct qcom_ubwc_cfg_data sm6115_data =3D { static const struct qcom_ubwc_cfg_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_3_0, - .ubwc_swizzle =3D 1, + .ubwc_swizzle =3D 7, .highest_bank_bit =3D 14, }; =20 --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EF32263889; Wed, 25 Jun 2025 13:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857075; cv=none; b=V+M5F5tXlT9nPcw0f7/LLdUk4i3RWExxhqgIpRkm5WPFTf+lExTEcTUdynw8/YPo+FjqzI2Eajbm1gLJVUGHIQe4iw6YZMoiOydWy3PlZcu0+9oTYjWLYfNLTjBkkj61xo3FyKxhnIvQ0pXoLbMya+0rDRAMzfsyFYtzb2Ym+KU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750857075; c=relaxed/simple; bh=HXejwBHjVhIVdEfA05YFBWpoT919/Xwuxzfki73h1Uc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mIpiC3jMrnnYraIwygF4pIMnbmD5U9YUPn2Fe8Gif4KRBXJqCjwXosxscelc81kezrhKTyazMXNTYNtENxx5zoMkhDPMmD/cVV8sQKyuSN/yCc4LmyPOVQ3TJ45ZKCLw6uMk6xnqbNbV/ACWw9X1Y4JmFTD3oJy/WvpB6E6Oj6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LvMJEDuH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LvMJEDuH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 950D6C4CEEE; Wed, 25 Jun 2025 13:11:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857075; bh=HXejwBHjVhIVdEfA05YFBWpoT919/Xwuxzfki73h1Uc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LvMJEDuHpfIast1vN40E7OCVGuwQjWUGagA77M8Y0Cb1/4sZA3Wb/8j8uTU70s7DP fOPicZgx/IfyrHwAK+mwJy7IroaMo5MD+c0FNEPekdrT6vQZoDAabF3jHqPWJQpZWX Vz8CQlI1rhIKy/ix2QlEgH0sPgGCKBdCrtSA8OjQoRKIP0tAvMNUJTZF1DAER1+sqA fr/NN30g7LGViRZHHb4hFJky6VBz0e2Zjd+wbks++jvAtXsfKvmXYRkcrOtZCU/Beh qu1qjiOTztv5DZE6Dhb6Q3SYq5Qv/VGJHiU0ojNC/nxMiLJeJ1jzEoiCY4wccFKzCX qKbTo9E9qZ9bA== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:20 +0200 Subject: [PATCH v5 12/14] soc: qcom: ubwc: Add #defines for UBWC swizzle bits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-12-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=7400; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=r+76uZPGShAF8TMlEDHNZOPYCTMe3A9KqrCqkJ5zMjY=; b=fiA7G5Qf4HN8+WerGFgF2yBjbtlzRWScsJfGR3I1qCTyJwNPDDJP+/vsoBgAOvc3pcYLSYgGB 39E0xdFtqguCVHlqzpkr6JvWtmCGKILIiljjtJxE4slgEaXnB+CUff/ X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Make the values a bit more meaningful. This commit is intentionally cross-subsystem to ease review, as the patchset is intended to be merged together, with a maintainer consensus. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/soc/qcom/ubwc_config.c | 37 +++++++++++++++++++++++--------= ---- include/linux/soc/qcom/ubwc.h | 8 ++++---- 3 files changed, 30 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e16ad298ba1c11ed5b4c70487bc09e23b2ed5cce..6612030621b1b16c8662d39453b= 609c9c9ff982f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -679,7 +679,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; bool rgb565_predicator =3D cfg->ubwc_enc_version >=3D UBWC_4_0; - u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & BIT(1)); + u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LV= L2); bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; bool min_acc_len_64b =3D false; diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 49ec20901f607b77fb297764b97d75c0537b1db2..7fb18ab067e60a8443d73d31886= acc344c11d3b1 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -32,7 +32,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data =3D { static const struct qcom_ubwc_cfg_data sa8775p_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 4, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, @@ -41,7 +41,8 @@ static const struct qcom_ubwc_cfg_data sa8775p_data =3D { static const struct qcom_ubwc_cfg_data sar2130p_data =3D { .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, .macrotile_mode =3D true, @@ -50,7 +51,8 @@ static const struct qcom_ubwc_cfg_data sar2130p_data =3D { static const struct qcom_ubwc_cfg_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -58,7 +60,8 @@ static const struct qcom_ubwc_cfg_data sc7180_data =3D { static const struct qcom_ubwc_cfg_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, .macrotile_mode =3D true, @@ -74,7 +77,8 @@ static const struct qcom_ubwc_cfg_data sc8180x_data =3D { static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 16, .macrotile_mode =3D true, @@ -95,7 +99,9 @@ static const struct qcom_ubwc_cfg_data sdm845_data =3D { static const struct qcom_ubwc_cfg_data sm6115_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 7, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -103,7 +109,9 @@ static const struct qcom_ubwc_cfg_data sm6115_data =3D { static const struct qcom_ubwc_cfg_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_3_0, - .ubwc_swizzle =3D 7, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 @@ -116,7 +124,8 @@ static const struct qcom_ubwc_cfg_data sm6150_data =3D { static const struct qcom_ubwc_cfg_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 14, }; @@ -136,7 +145,8 @@ static const struct qcom_ubwc_cfg_data sm8150_data =3D { static const struct qcom_ubwc_cfg_data sm8250_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -146,7 +156,8 @@ static const struct qcom_ubwc_cfg_data sm8250_data =3D { static const struct qcom_ubwc_cfg_data sm8350_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -156,7 +167,8 @@ static const struct qcom_ubwc_cfg_data sm8350_data =3D { static const struct qcom_ubwc_cfg_data sm8550_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, @@ -176,7 +188,8 @@ static const struct qcom_ubwc_cfg_data sm8750_data =3D { static const struct qcom_ubwc_cfg_data x1e80100_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, - .ubwc_swizzle =3D 6, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ .highest_bank_bit =3D 16, diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index 5dc41aafa0afe1fe7f66ae6f8815989663ced780..e6b13980e58d1d120c84acbb90d= b52c007242387 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -21,11 +21,11 @@ struct qcom_ubwc_cfg_data { * UBWC 1.0 always enables all three levels. * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. * UBWC 4.0 adds the optional ability to disable levels 2 & 3. - * - * This is a bitmask where BIT(0) enables level 1, BIT(1) - * controls level 2, and BIT(2) enables level 3. */ u32 ubwc_swizzle; +#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0) +#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1) +#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2) =20 /** * @highest_bank_bit: Highest Bank Bit @@ -66,7 +66,7 @@ static inline bool qcom_ubwc_get_ubwc_mode(const struct q= com_ubwc_cfg_data *cfg) { bool ret =3D cfg->ubwc_enc_version =3D=3D UBWC_1_0; =20 - if (ret && !(cfg->ubwc_swizzle & BIT(0))) + if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1)) pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0= \n"); =20 return ret; --=20 2.50.0 From nobody Wed Oct 8 17:33:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B79C263899; Wed, 25 Jun 2025 13:11:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 25 Jun 2025 13:11:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750857080; bh=MkfZzfoVVNA3pxZuMdbFXVp7BKdKAuZdCsoqILxRvRQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ruqvgjdBnqjzAwiksbIIjr7WLNzs0VwEjeUSSyTkcc+5z0EmmxbxbeX8pEsHRMh2a 3Xa7rEBHaGGlaxSFkxWVU6b4OvaUI3BsI9cEh1KHHKxa1w1ScGyPTqzM1qWQ41HbRm VvIlHWt+bvSQE/+WIHGX/U+7/m499veFYErH3Vvso0O0Vlpf0kL+z8HntGQn6n/QOa ICq0V+IUQ0HSHhLp1dS8xiunq09PGyPSY3Tt/QmpFEIRoQgvPSRL/dbdqBAd2L/eLn rjMQ13AQG/+wDr+qFNCU4D5788ap/AePqLhXnitZEq0ny7QNwojMWobSPCLnxmRmS3 2Icvo/6rMHO3A== From: Konrad Dybcio Date: Wed, 25 Jun 2025 15:10:21 +0200 Subject: [PATCH v5 13/14] soc: qcom: ubwc: Fill in UBWC swizzle cfg for platforms that lack one Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-13-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=2912; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=BYjEaeP46UE0oO20FwMEmnGxDtZiOlg0yWNCSte8Gao=; b=CkayZoiAePy0yJDF0unY93ZXDyCSxISrgOG2Kj0wWQkP3zr6T2/4Y+sZP80SyxtX+7TYxHjQ4 aWKedzK/nP5BFNnakHyH8WJGvuPOap9xekZ3/QaNC//cpHkOxmMuXUj X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The UBWC 1.0 case is easy - it must be all 3 enabled. UBWC2.0 and 3.x require that level1 is removed, follow suit. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/ubwc_config.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 7fb18ab067e60a8443d73d31886acc344c11d3b1..dd616342acbe67a76257bbe8b71= 9cc5d18a85f9f 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -15,12 +15,18 @@ static const struct qcom_ubwc_cfg_data msm8937_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_1_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data msm8998_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_1_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 @@ -70,6 +76,8 @@ static const struct qcom_ubwc_cfg_data sc7280_data =3D { static const struct qcom_ubwc_cfg_data sc8180x_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 16, .macrotile_mode =3D true, }; @@ -87,12 +95,16 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = =3D { static const struct qcom_ubwc_cfg_data sdm670_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 static const struct qcom_ubwc_cfg_data sdm845_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, }; =20 @@ -118,6 +130,8 @@ static const struct qcom_ubwc_cfg_data sm6125_data =3D { static const struct qcom_ubwc_cfg_data sm6150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; =20 @@ -133,12 +147,16 @@ static const struct qcom_ubwc_cfg_data sm6350_data = =3D { static const struct qcom_ubwc_cfg_data sm7150_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-topic-ubwc_central-v5-14-e256d18219e2@oss.qualcomm.com> References: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> In-Reply-To: <20250625-topic-ubwc_central-v5-0-e256d18219e2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Simona Vetter , Rob Clark , Abhinav Kumar , Jessica Zhang , Rob Clark , Akhil P Oommen Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750857014; l=10610; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=potIy8Dkkz/1yoAE7J/I600HrUDXJJWdkOC8tivmHWU=; b=5ZklbqY90MPGggp+8npt0zOBciPmOeioMn+oIxJDyOu0O3QbcnO8ivK3ZvkhgOLwBLGZ77dGD wUCLVWtOaKmA2famVTNUSK4fIgVhOavro6q9fmkd3TUnZ9fRV+r/0ih X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Now that Adreno specifics are out of the way, use the common config (but leave the HBB hardcoding in place until that is wired up on the other side). Acked-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 20 ++++----- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 76 ++++++++++++++++++-----------= ---- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 +-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 45 +++---------------- 4 files changed, 60 insertions(+), 87 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index 60aef079623606bb1ae44ba59ac45e391595b0ba..6a77d130446218e81ea44330eea= 284a4abe98d3a 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -835,8 +835,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu) =20 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); =20 - BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); - hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; + BUG_ON(adreno_gpu->ubwc_config->highest_bank_bit < 13); + hbb =3D adreno_gpu->ubwc_config->highest_bank_bit - 13; =20 gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb << 7); gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb << 1); @@ -1756,6 +1756,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; struct adreno_platform_config *config =3D pdev->dev.platform_data; + const struct qcom_ubwc_cfg_data *common_cfg; struct a5xx_gpu *a5xx_gpu =3D NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; @@ -1792,15 +1793,14 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *de= v) /* Set up the preemption specific bits and pieces for each ringbuffer */ a5xx_preempt_init(gpu); =20 - /* Set the highest bank bit */ - if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu)) - adreno_gpu->ubwc_config.highest_bank_bit =3D 15; - else - adreno_gpu->ubwc_config.highest_bank_bit =3D 14; + /* Inherit the common config and make some necessary fixups */ + common_cfg =3D qcom_ubwc_config_get_data(); + if (IS_ERR(common_cfg)) + return ERR_CAST(common_cfg); =20 - /* a5xx only supports UBWC 1.0, these are not configurable */ - adreno_gpu->ubwc_config.macrotile_mode =3D 0; - adreno_gpu->ubwc_config.ubwc_swizzle =3D 0x7; + /* Copy the data into the internal struct to drop the const qualifier (te= mporarily) */ + adreno_gpu->_ubwc_config =3D *common_cfg; + adreno_gpu->ubwc_config =3D &adreno_gpu->_ubwc_config; =20 adreno_gpu->uche_trap_base =3D 0x0001ffffffff0000ull; =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 6612030621b1b16c8662d39453b609c9c9ff982f..c618cebc5682fbfb21f328ca575= 6fa0ac34831d9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -605,64 +605,70 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) =20 static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) { - /* Inherit the common config and make some necessary fixups */ - gpu->common_ubwc_cfg =3D qcom_ubwc_config_get_data(); - if (IS_ERR(gpu->common_ubwc_cfg)) - return PTR_ERR(gpu->common_ubwc_cfg); + const struct qcom_ubwc_cfg_data *common_cfg; + struct qcom_ubwc_cfg_data *cfg =3D &gpu->_ubwc_config; =20 - gpu->ubwc_config.ubwc_swizzle =3D 0x6; - gpu->ubwc_config.macrotile_mode =3D 0; - gpu->ubwc_config.highest_bank_bit =3D 15; + /* Inherit the common config and make some necessary fixups */ + common_cfg =3D qcom_ubwc_config_get_data(); + if (IS_ERR(common_cfg)) + return PTR_ERR(common_cfg); + + /* Copy the data into the internal struct to drop the const qualifier (te= mporarily) */ + *cfg =3D *common_cfg; + + cfg->ubwc_swizzle =3D 0x6; + cfg->highest_bank_bit =3D 15; =20 if (adreno_is_a610(gpu)) { - gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.ubwc_swizzle =3D 0x7; + cfg->highest_bank_bit =3D 13; + cfg->ubwc_swizzle =3D 0x7; } =20 if (adreno_is_a618(gpu)) - gpu->ubwc_config.highest_bank_bit =3D 14; + cfg->highest_bank_bit =3D 14; =20 if (adreno_is_a619(gpu)) /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ - gpu->ubwc_config.highest_bank_bit =3D 13; + cfg->highest_bank_bit =3D 13; =20 if (adreno_is_a619_holi(gpu)) - gpu->ubwc_config.highest_bank_bit =3D 13; + cfg->highest_bank_bit =3D 13; =20 if (adreno_is_a621(gpu)) - gpu->ubwc_config.highest_bank_bit =3D 13; + cfg->highest_bank_bit =3D 13; =20 - if (adreno_is_a623(gpu)) { - gpu->ubwc_config.highest_bank_bit =3D 16; - gpu->ubwc_config.macrotile_mode =3D 1; - } - - if (adreno_is_a680(gpu)) - gpu->ubwc_config.macrotile_mode =3D 1; + if (adreno_is_a623(gpu)) + cfg->highest_bank_bit =3D 16; =20 if (adreno_is_a650(gpu) || adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_a730(gpu) || adreno_is_a740_family(gpu)) { - /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - gpu->ubwc_config.highest_bank_bit =3D 16; - gpu->ubwc_config.macrotile_mode =3D 1; + /* TODO: get ddr type from bootloader and use 15 for LPDDR4 */ + cfg->highest_bank_bit =3D 16; } =20 if (adreno_is_a663(gpu)) { - gpu->ubwc_config.highest_bank_bit =3D 13; - gpu->ubwc_config.macrotile_mode =3D 1; - gpu->ubwc_config.ubwc_swizzle =3D 0x4; + cfg->highest_bank_bit =3D 13; + cfg->ubwc_swizzle =3D 0x4; } =20 - if (adreno_is_7c3(gpu)) { - gpu->ubwc_config.highest_bank_bit =3D 14; - gpu->ubwc_config.macrotile_mode =3D 1; - } + if (adreno_is_7c3(gpu)) + cfg->highest_bank_bit =3D 14; =20 if (adreno_is_a702(gpu)) - gpu->ubwc_config.highest_bank_bit =3D 14; + cfg->highest_bank_bit =3D 14; + + if (cfg->highest_bank_bit !=3D common_cfg->highest_bank_bit) + DRM_WARN_ONCE("Inconclusive highest_bank_bit value: %u (GPU) vs %u (UBWC= _CFG)\n", + cfg->highest_bank_bit, common_cfg->highest_bank_bit); + + if (cfg->ubwc_swizzle !=3D common_cfg->ubwc_swizzle) + DRM_WARN_ONCE("Inconclusive ubwc_swizzle value: %u (GPU) vs %u (UBWC_CFG= )\n", + cfg->ubwc_swizzle, common_cfg->ubwc_swizzle); + + gpu->ubwc_config =3D &gpu->_ubwc_config; =20 return 0; } @@ -670,14 +676,14 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); - const struct qcom_ubwc_cfg_data *cfg =3D adreno_gpu->common_ubwc_cfg; + const struct qcom_ubwc_cfg_data *cfg =3D adreno_gpu->ubwc_config; /* * We subtract 13 from the highest bank bit (13 is the minimum value * allowed by hw) and write the lowest two bits of the remaining value * as hbb_lo and the one above it as hbb_hi to the hardware. */ - BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); - u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit - 13; + BUG_ON(cfg->highest_bank_bit < 13); + u32 hbb =3D cfg->highest_bank_bit - 13; bool rgb565_predicator =3D cfg->ubwc_enc_version >=3D UBWC_4_0; u32 level2_swizzling_dis =3D !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LV= L2); bool ubwc_mode =3D qcom_ubwc_get_ubwc_mode(cfg); @@ -719,7 +725,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) min_acc_len_64b << 23 | hbb_lo << 21); =20 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, - adreno_gpu->ubwc_config.macrotile_mode); + cfg->macrotile_mode); } =20 static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 86bff915c3e793583c81a6414ee89c1f59365c58..1251ff1b4895287340c9f3809d4= 6441aded64cfd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -420,16 +420,16 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_= file_private *ctx, *value =3D ctx->aspace->va_size; return 0; case MSM_PARAM_HIGHEST_BANK_BIT: - *value =3D adreno_gpu->ubwc_config.highest_bank_bit; + *value =3D adreno_gpu->ubwc_config->highest_bank_bit; return 0; case MSM_PARAM_RAYTRACING: *value =3D adreno_gpu->has_ray_tracing; return 0; case MSM_PARAM_UBWC_SWIZZLE: - *value =3D adreno_gpu->ubwc_config.ubwc_swizzle; + *value =3D adreno_gpu->ubwc_config->ubwc_swizzle; return 0; case MSM_PARAM_MACROTILE_MODE: - *value =3D adreno_gpu->ubwc_config.macrotile_mode; + *value =3D adreno_gpu->ubwc_config->macrotile_mode; return 0; case MSM_PARAM_UCHE_TRAP_BASE: *value =3D adreno_gpu->uche_trap_base; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index a2a211cac147cb5bc5befdcab07559b778adc2bb..e56a39df815f100caca945576de= 7cb55664980bc 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -207,45 +207,12 @@ struct adreno_gpu { /* firmware: */ const struct firmware *fw[ADRENO_FW_MAX]; =20 - struct { - /** - * @rgb565_predicator: Unknown, introduced with A650 family, - * related to UBWC mode/ver 4 - */ - u32 rgb565_predicator; - /** @uavflagprd_inv: Unknown, introduced with A650 family */ - u32 uavflagprd_inv; - /** @min_acc_len: Whether the minimum access length is 64 bits */ - u32 min_acc_len; - /** - * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling. - * - * UBWC 1.0 always enables all three levels. - * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3. - * UBWC 4.0 adds the optional ability to disable levels 2 & 3. - * - * This is a bitmask where BIT(0) enables level 1, BIT(1) - * controls level 2, and BIT(2) enables level 3. - */ - u32 ubwc_swizzle; - /** - * @highest_bank_bit: Highest Bank Bit - * - * The Highest Bank Bit value represents the bit of the highest - * DDR bank. This should ideally use DRAM type detection. - */ - u32 highest_bank_bit; - u32 amsbc; - /** - * @macrotile_mode: Macrotile Mode - * - * Whether to use 4-channel macrotiling mode or the newer - * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is - * 4-channel and 1 is 8-channel. - */ - u32 macrotile_mode; - } ubwc_config; - const struct qcom_ubwc_cfg_data *common_ubwc_cfg; + /* + * The migration to the central UBWC config db is still in flight - keep + * a copy containing some local fixups until that's done. + */ + const struct qcom_ubwc_cfg_data *ubwc_config; + struct qcom_ubwc_cfg_data _ubwc_config; =20 /* * Register offsets are different between some GPUs. --=20 2.50.0