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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0bf33b108sm106422566b.115.2025.06.25.02.13.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:13:56 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:13:47 +0200 Subject: [PATCH 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm SM7635 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-icc-v1-1-8b49200416b0@fairphone.com> References: <20250625-sm7635-icc-v1-0-8b49200416b0@fairphone.com> In-Reply-To: <20250625-sm7635-icc-v1-0-8b49200416b0@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750842835; l=8682; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=54t9W8bEFcos9T5d7Eu0wZ/vWvWROai7eof2tEZ2Zl0=; b=+Q32DRtxbNr2uBXuELRfjUdwl4eKz+OBvEQ4psFS0JEAjjzGqlxbFe/0FkSgWk2bg2D72VL7V GXvWDZM/wx2CJmxFKK7Urt2Xv4fWUYpNUQREbvRHgty3F0XBNE6Oirj X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the RPMh Network-On-Chip Interconnect of the SM7635 platform. Signed-off-by: Luca Weiss --- .../bindings/interconnect/qcom,sm7635-rpmh.yaml | 136 +++++++++++++++++= +++ .../dt-bindings/interconnect/qcom,sm7635-rpmh.h | 141 +++++++++++++++++= ++++ 2 files changed, 277 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm7635-rpm= h.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm7635-rpmh.ya= ml new file mode 100644 index 0000000000000000000000000000000000000000..6373399542d5728b4a4097876d2= c4dffc4482038 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm7635-rpmh.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm7635-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SM7635 + +maintainers: + - Luca Weiss + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provide= r is + able to communicate with the BCM through the Resource State Coordinator = (RSC) + associated with each execution environment. Provider nodes must point to= at + least one RPMh device child node pertaining to their RSC and each provid= er + can map to multiple RPMh resources. + + See also:: include/dt-bindings/interconnect/qcom,sm7635-rpmh.h + +properties: + compatible: + enum: + - qcom,sm7635-aggre1-noc + - qcom,sm7635-aggre2-noc + - qcom,sm7635-clk-virt + - qcom,sm7635-cnoc-cfg + - qcom,sm7635-cnoc-main + - qcom,sm7635-gem-noc + - qcom,sm7635-lpass-ag-noc + - qcom,sm7635-mc-virt + - qcom,sm7635-mmss-noc + - qcom,sm7635-nsp-noc + - qcom,sm7635-pcie-anoc + - qcom,sm7635-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm7635-clk-virt + - qcom,sm7635-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm7635-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm7635-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre USB3 PRIM AXI clock + - description: aggre UFS PHY AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm7635-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm7635-aggre1-noc + - qcom,sm7635-aggre2-noc + - qcom,sm7635-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + #include + + interconnect-0 { + compatible =3D "qcom,sm7635-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + interconnect@16e0000 { + compatible =3D "qcom,sm7635-aggre1-noc"; + reg =3D <0x016e0000 0x16400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; diff --git a/include/dt-bindings/interconnect/qcom,sm7635-rpmh.h b/include/= dt-bindings/interconnect/qcom,sm7635-rpmh.h new file mode 100644 index 0000000000000000000000000000000000000000..d963780ddb540825672bc411eb1= 06a298003b09f --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm7635-rpmh.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights re= served. + * Copyright (c) 2025, Luca Weiss + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM7635_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM7635_H + +#define MASTER_QUP_1 0 +#define MASTER_UFS_MEM 1 +#define MASTER_USB3_0 2 +#define SLAVE_A1NOC_SNOC 3 + +#define MASTER_QDSS_BAM 0 +#define MASTER_QSPI_0 1 +#define MASTER_QUP_0 2 +#define MASTER_CRYPTO 3 +#define MASTER_IPA 4 +#define MASTER_QDSS_ETR 5 +#define MASTER_QDSS_ETR_1 6 +#define MASTER_SDCC_1 7 +#define MASTER_SDCC_2 8 +#define SLAVE_A2NOC_SNOC 9 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define SLAVE_QUP_CORE_0 2 +#define SLAVE_QUP_CORE_1 3 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_CAMERA_CFG 3 +#define SLAVE_CLK_CTL 4 +#define SLAVE_RBCPR_CX_CFG 5 +#define SLAVE_RBCPR_MXA_CFG 6 +#define SLAVE_CRYPTO_0_CFG 7 +#define SLAVE_CX_RDPM 8 +#define SLAVE_GFX3D_CFG 9 +#define SLAVE_IMEM_CFG 10 +#define SLAVE_CNOC_MSS 11 +#define SLAVE_MX_2_RDPM 12 +#define SLAVE_MX_RDPM 13 +#define SLAVE_PDM 14 +#define SLAVE_QDSS_CFG 15 +#define SLAVE_QSPI_0 16 +#define SLAVE_QUP_0 17 +#define SLAVE_QUP_1 18 +#define SLAVE_SDC1 19 +#define SLAVE_SDCC_2 20 +#define SLAVE_TCSR 21 +#define SLAVE_TLMM 22 +#define SLAVE_UFS_MEM_CFG 23 +#define SLAVE_USB3_0 24 +#define SLAVE_VENUS_CFG 25 +#define SLAVE_VSENSE_CTRL_CFG 26 +#define SLAVE_WLAN 27 +#define SLAVE_CNOC_MNOC_HF_CFG 28 +#define SLAVE_CNOC_MNOC_SF_CFG 29 +#define SLAVE_NSP_QTB_CFG 30 +#define SLAVE_PCIE_ANOC_CFG 31 +#define SLAVE_WLAN_Q6_THROTTLE_CFG 32 +#define SLAVE_SERVICE_CNOC_CFG 33 +#define SLAVE_QDSS_STM 34 +#define SLAVE_TCU 35 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_DISPLAY_CFG 3 +#define SLAVE_IPA_CFG 4 +#define SLAVE_IPC_ROUTER_CFG 5 +#define SLAVE_PCIE_0_CFG 6 +#define SLAVE_PCIE_1_CFG 7 +#define SLAVE_PRNG 8 +#define SLAVE_TME_CFG 9 +#define SLAVE_APPSS 10 +#define SLAVE_CNOC_CFG 11 +#define SLAVE_DDRSS_CFG 12 +#define SLAVE_IMEM 13 +#define SLAVE_PIMEM 14 +#define SLAVE_SERVICE_CNOC 15 +#define SLAVE_PCIE_0 16 +#define SLAVE_PCIE_1 17 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_GFX3D 3 +#define MASTER_LPASS_GEM_NOC 4 +#define MASTER_MSS_PROC 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_COMPUTE_NOC 8 +#define MASTER_ANOC_PCIE_GEM_NOC 9 +#define MASTER_SNOC_GC_MEM_NOC 10 +#define MASTER_SNOC_SF_MEM_NOC 11 +#define MASTER_WLAN_Q6 12 +#define SLAVE_GEM_NOC_CNOC 13 +#define SLAVE_LLCC 14 +#define SLAVE_MEM_NOC_PCIE_SNOC 15 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_ICP 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_MDP 3 +#define MASTER_VIDEO 4 +#define MASTER_CNOC_MNOC_HF_CFG 5 +#define MASTER_CNOC_MNOC_SF_CFG 6 +#define SLAVE_MNOC_HF_MEM_NOC 7 +#define SLAVE_MNOC_SF_MEM_NOC 8 +#define SLAVE_SERVICE_MNOC_HF 9 +#define SLAVE_SERVICE_MNOC_SF 10 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 +#define SLAVE_SERVICE_PCIE_ANOC 4 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_APSS_NOC 2 +#define MASTER_CNOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_SNOC_GEM_NOC_GC 6 +#define SLAVE_SNOC_GEM_NOC_SF 7 + + +#endif --=20 2.50.0 From nobody Wed Oct 8 19:13:19 2025 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D44829A9CD for ; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0bf33b108sm106422566b.115.2025.06.25.02.13.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:13:57 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:13:48 +0200 Subject: [PATCH 2/2] interconnect: qcom: Add SM7635 interconnect provider driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-icc-v1-2-8b49200416b0@fairphone.com> References: <20250625-sm7635-icc-v1-0-8b49200416b0@fairphone.com> In-Reply-To: <20250625-sm7635-icc-v1-0-8b49200416b0@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750842835; l=47224; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=vrLW1qnJCDC0FLdYQbHwM+CFoiyFsyO9xdH1H9FbgME=; b=/c1TLn9NPTvHeAW94hlW9FtuxlKzZRHGbGOwG4CoW89VKSp66LNUdS7JgHw9MeKZrKu+ojKuR 1g90u/BbCk5BPBUEVuEcXCkNkfx0XyYaVrgr7wQICbkIKUFlN+Hrhgq X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add driver for the Qualcomm interconnect buses found in SM7635 based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Signed-off-by: Luca Weiss --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/sm7635.c | 1554 ++++++++++++++++++++++++++++++++= ++++ drivers/interconnect/qcom/sm7635.h | 130 +++ 4 files changed, 1695 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 1219f4f23d40ecfe6ec54af590a2d71ef01c9384..11743db636a5f596b15e7c15c21= 04c02ed259723 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -283,6 +283,15 @@ config INTERCONNECT_QCOM_SM7150 This is a driver for the Qualcomm Network-on-Chip on sm7150-based platforms. =20 +config INTERCONNECT_QCOM_SM7635 + tristate "Qualcomm SM7635 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on SM7635-based + platforms. + config INTERCONNECT_QCOM_SM8150 tristate "Qualcomm SM8150 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 7887b1e8d69b6b0193464835dbe57414f99554bf..1bf4a8021e12eb4bd88df0e2926= 5de6804db276f 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -34,6 +34,7 @@ qnoc-sdx75-objs :=3D sdx75.o qnoc-sm6115-objs :=3D sm6115.o qnoc-sm6350-objs :=3D sm6350.o qnoc-sm7150-objs :=3D sm7150.o +qnoc-sm7635-objs :=3D sm7635.o qnoc-sm8150-objs :=3D sm8150.o qnoc-sm8250-objs :=3D sm8250.o qnoc-sm8350-objs :=3D sm8350.o @@ -75,6 +76,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) +=3D qnoc-sdx75.o obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) +=3D qnoc-sm6115.o obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) +=3D qnoc-sm6350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM7150) +=3D qnoc-sm7150.o +obj-$(CONFIG_INTERCONNECT_QCOM_SM7635) +=3D qnoc-sm7635.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) +=3D qnoc-sm8150.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) +=3D qnoc-sm8250.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) +=3D qnoc-sm8350.o diff --git a/drivers/interconnect/qcom/sm7635.c b/drivers/interconnect/qcom= /sm7635.c new file mode 100644 index 0000000000000000000000000000000000000000..688b2250df0699aca79f834d31c= 926fb2ade9241 --- /dev/null +++ b/drivers/interconnect/qcom/sm7635.c @@ -0,0 +1,1554 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights re= served. + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-common.h" +#include "icc-rpmh.h" +#include "sm7635.h" + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D SM7635_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SM7635_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SM7635_MASTER_USB3_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SM7635_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .id =3D SM7635_MASTER_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .id =3D SM7635_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SM7635_MASTER_CRYPTO, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SM7635_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 =3D { + .name =3D "xm_qdss_etr_0", + .id =3D SM7635_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 =3D { + .name =3D "xm_qdss_etr_1", + .id =3D SM7635_MASTER_QDSS_ETR_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc1 =3D { + .name =3D "xm_sdc1", + .id =3D SM7635_MASTER_SDCC_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SM7635_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .id =3D SM7635_MASTER_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .id =3D SM7635_MASTER_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qsm_cfg =3D { + .name =3D "qsm_cfg", + .id =3D SM7635_MASTER_CNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 35, + .links =3D { SM7635_SLAVE_AHB2PHY_SOUTH, SM7635_SLAVE_AHB2PHY_NORTH, + SM7635_SLAVE_CAMERA_CFG, SM7635_SLAVE_CLK_CTL, + SM7635_SLAVE_RBCPR_CX_CFG, SM7635_SLAVE_RBCPR_MXA_CFG, + SM7635_SLAVE_CRYPTO_0_CFG, SM7635_SLAVE_CX_RDPM, + SM7635_SLAVE_GFX3D_CFG, SM7635_SLAVE_IMEM_CFG, + SM7635_SLAVE_CNOC_MSS, SM7635_SLAVE_MX_2_RDPM, + SM7635_SLAVE_MX_RDPM, SM7635_SLAVE_PDM, + SM7635_SLAVE_QDSS_CFG, SM7635_SLAVE_QSPI_0, + SM7635_SLAVE_QUP_0, SM7635_SLAVE_QUP_1, + SM7635_SLAVE_SDC1, SM7635_SLAVE_SDCC_2, + SM7635_SLAVE_TCSR, SM7635_SLAVE_TLMM, + SM7635_SLAVE_UFS_MEM_CFG, SM7635_SLAVE_USB3_0, + SM7635_SLAVE_VENUS_CFG, SM7635_SLAVE_VSENSE_CTRL_CFG, + SM7635_SLAVE_WLAN, SM7635_SLAVE_CNOC_MNOC_HF_CFG, + SM7635_SLAVE_CNOC_MNOC_SF_CFG, SM7635_SLAVE_NSP_QTB_CFG, + SM7635_SLAVE_PCIE_ANOC_CFG, SM7635_SLAVE_WLAN_Q6_THROTTLE_CFG, + SM7635_SLAVE_SERVICE_CNOC_CFG, SM7635_SLAVE_QDSS_STM, + SM7635_SLAVE_TCU }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc =3D { + .name =3D "qnm_gemnoc_cnoc", + .id =3D SM7635_MASTER_GEM_NOC_CNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 14, + .links =3D { SM7635_SLAVE_AOSS, SM7635_SLAVE_DISPLAY_CFG, + SM7635_SLAVE_IPA_CFG, SM7635_SLAVE_IPC_ROUTER_CFG, + SM7635_SLAVE_PCIE_0_CFG, SM7635_SLAVE_PCIE_1_CFG, + SM7635_SLAVE_PRNG, SM7635_SLAVE_TME_CFG, + SM7635_SLAVE_APPSS, SM7635_SLAVE_CNOC_CFG, + SM7635_SLAVE_DDRSS_CFG, SM7635_SLAVE_IMEM, + SM7635_SLAVE_PIMEM, SM7635_SLAVE_SERVICE_CNOC }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie =3D { + .name =3D "qnm_gemnoc_pcie", + .id =3D SM7635_MASTER_GEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM7635_SLAVE_PCIE_0, SM7635_SLAVE_PCIE_1 }, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .id =3D SM7635_MASTER_GPU_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .id =3D SM7635_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .id =3D SM7635_MASTER_APPSS_PROC, + .channels =3D 3, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC, + SM7635_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .id =3D SM7635_MASTER_GFX3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_lpass_gemnoc =3D { + .name =3D "qnm_lpass_gemnoc", + .id =3D SM7635_MASTER_LPASS_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC, + SM7635_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_mdsp =3D { + .name =3D "qnm_mdsp", + .id =3D SM7635_MASTER_MSS_PROC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC, + SM7635_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SM7635_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SM7635_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc =3D { + .name =3D "qnm_nsp_gemnoc", + .id =3D SM7635_MASTER_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC, + SM7635_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .id =3D SM7635_MASTER_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SM7635_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SM7635_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC, + SM7635_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qxm_wlan_q6 =3D { + .name =3D "qxm_wlan_q6", + .id =3D SM7635_MASTER_WLAN_Q6, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .links =3D { SM7635_SLAVE_GEM_NOC_CNOC, SM7635_SLAVE_LLCC, + SM7635_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qxm_lpass_dsp =3D { + .name =3D "qxm_lpass_dsp", + .id =3D SM7635_MASTER_LPASS_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_LPASS_GEM_NOC }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SM7635_MASTER_LLCC, + .channels =3D 2, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .id =3D SM7635_MASTER_CAMNOC_HF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp =3D { + .name =3D "qnm_camnoc_icp", + .id =3D SM7635_MASTER_CAMNOC_ICP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .id =3D SM7635_MASTER_CAMNOC_SF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp =3D { + .name =3D "qnm_mdp", + .id =3D SM7635_MASTER_MDP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video =3D { + .name =3D "qnm_video", + .id =3D SM7635_MASTER_VIDEO, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qsm_hf_mnoc_cfg =3D { + .name =3D "qsm_hf_mnoc_cfg", + .id =3D SM7635_MASTER_CNOC_MNOC_HF_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_SERVICE_MNOC_HF }, +}; + +static struct qcom_icc_node qsm_sf_mnoc_cfg =3D { + .name =3D "qsm_sf_mnoc_cfg", + .id =3D SM7635_MASTER_CNOC_MNOC_SF_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_SERVICE_MNOC_SF }, +}; + +static struct qcom_icc_node qxm_nsp =3D { + .name =3D "qxm_nsp", + .id =3D SM7635_MASTER_CDSP_PROC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { + .name =3D "qsm_pcie_anoc_cfg", + .id =3D SM7635_MASTER_PCIE_ANOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_SERVICE_PCIE_ANOC }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .id =3D SM7635_MASTER_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .id =3D SM7635_MASTER_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SM7635_MASTER_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SM7635_MASTER_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_apss_noc =3D { + .name =3D "qnm_apss_noc", + .id =3D SM7635_MASTER_APSS_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_cnoc_data =3D { + .name =3D "qnm_cnoc_data", + .id =3D SM7635_MASTER_CNOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SM7635_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SM7635_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SM7635_SLAVE_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM7635_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SM7635_SLAVE_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM7635_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .id =3D SM7635_SLAVE_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .id =3D SM7635_SLAVE_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .id =3D SM7635_SLAVE_AHB2PHY_SOUTH, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .id =3D SM7635_SLAVE_AHB2PHY_NORTH, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SM7635_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SM7635_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SM7635_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_cpr_mxa =3D { + .name =3D "qhs_cpr_mxa", + .id =3D SM7635_SLAVE_RBCPR_MXA_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SM7635_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_cx_rdpm =3D { + .name =3D "qhs_cx_rdpm", + .id =3D SM7635_SLAVE_CX_RDPM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SM7635_SLAVE_GFX3D_CFG, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SM7635_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .id =3D SM7635_SLAVE_CNOC_MSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_mx_2_rdpm =3D { + .name =3D "qhs_mx_2_rdpm", + .id =3D SM7635_SLAVE_MX_2_RDPM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_mx_rdpm =3D { + .name =3D "qhs_mx_rdpm", + .id =3D SM7635_SLAVE_MX_RDPM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SM7635_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SM7635_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .id =3D SM7635_SLAVE_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D SM7635_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .id =3D SM7635_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_sdc1 =3D { + .name =3D "qhs_sdc1", + .id =3D SM7635_SLAVE_SDC1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SM7635_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SM7635_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .id =3D SM7635_SLAVE_TLMM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SM7635_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SM7635_SLAVE_USB3_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SM7635_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SM7635_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_wlan_q6 =3D { + .name =3D "qhs_wlan_q6", + .id =3D SM7635_SLAVE_WLAN, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_mnoc_hf_cfg =3D { + .name =3D "qss_mnoc_hf_cfg", + .id =3D SM7635_SLAVE_CNOC_MNOC_HF_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_MASTER_CNOC_MNOC_HF_CFG }, +}; + +static struct qcom_icc_node qss_mnoc_sf_cfg =3D { + .name =3D "qss_mnoc_sf_cfg", + .id =3D SM7635_SLAVE_CNOC_MNOC_SF_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_MASTER_CNOC_MNOC_SF_CFG }, +}; + +static struct qcom_icc_node qss_nsp_qtb_cfg =3D { + .name =3D "qss_nsp_qtb_cfg", + .id =3D SM7635_SLAVE_NSP_QTB_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_pcie_anoc_cfg =3D { + .name =3D "qss_pcie_anoc_cfg", + .id =3D SM7635_SLAVE_PCIE_ANOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_MASTER_PCIE_ANOC_CFG }, +}; + +static struct qcom_icc_node qss_wlan_q6_throttle_cfg =3D { + .name =3D "qss_wlan_q6_throttle_cfg", + .id =3D SM7635_SLAVE_WLAN_Q6_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node srvc_cnoc_cfg =3D { + .name =3D "srvc_cnoc_cfg", + .id =3D SM7635_SLAVE_SERVICE_CNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SM7635_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SM7635_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SM7635_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SM7635_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SM7635_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .id =3D SM7635_SLAVE_IPC_ROUTER_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .id =3D SM7635_SLAVE_PCIE_0_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .id =3D SM7635_SLAVE_PCIE_1_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SM7635_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qhs_tme_cfg =3D { + .name =3D "qhs_tme_cfg", + .id =3D SM7635_SLAVE_TME_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_apss =3D { + .name =3D "qss_apss", + .id =3D SM7635_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qss_cfg =3D { + .name =3D "qss_cfg", + .id =3D SM7635_SLAVE_CNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM7635_MASTER_CNOC_CFG }, +}; + +static struct qcom_icc_node qss_ddrss_cfg =3D { + .name =3D "qss_ddrss_cfg", + .id =3D SM7635_SLAVE_DDRSS_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SM7635_SLAVE_IMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SM7635_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node srvc_cnoc_main =3D { + .name =3D "srvc_cnoc_main", + .id =3D SM7635_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .id =3D SM7635_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .id =3D SM7635_SLAVE_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc =3D { + .name =3D "qns_gem_noc_cnoc", + .id =3D SM7635_SLAVE_GEM_NOC_CNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM7635_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SM7635_SLAVE_LLCC, + .channels =3D 2, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM7635_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie =3D { + .name =3D "qns_pcie", + .id =3D SM7635_SLAVE_MEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { + .name =3D "qns_lpass_ag_noc_gemnoc", + .id =3D SM7635_SLAVE_LPASS_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM7635_MASTER_LPASS_GEM_NOC }, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SM7635_SLAVE_EBI1, + .channels =3D 2, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SM7635_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM7635_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .id =3D SM7635_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM7635_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc_hf =3D { + .name =3D "srvc_mnoc_hf", + .id =3D SM7635_SLAVE_SERVICE_MNOC_HF, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node srvc_mnoc_sf =3D { + .name =3D "srvc_mnoc_sf", + .id =3D SM7635_SLAVE_SERVICE_MNOC_SF, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_nsp_gemnoc =3D { + .name =3D "qns_nsp_gemnoc", + .id =3D SM7635_SLAVE_CDSP_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM7635_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc =3D { + .name =3D "qns_pcie_mem_noc", + .id =3D SM7635_SLAVE_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_pcie_aggre_noc =3D { + .name =3D "srvc_pcie_aggre_noc", + .id =3D SM7635_SLAVE_SERVICE_PCIE_ANOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 0, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SM7635_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM7635_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SM7635_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM7635_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .enable_mask =3D 0x1, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .enable_mask =3D 0x1, + .keepalive =3D true, + .num_nodes =3D 51, + .nodes =3D { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mxa, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_mss_cfg, + &qhs_mx_2_rdpm, &qhs_mx_rdpm, + &qhs_pdm, &qhs_qdss_cfg, + &qhs_qspi, &qhs_sdc1, + &qhs_sdc2, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qhs_wlan_q6, + &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg, + &qss_wlan_q6_throttle_cfg, &srvc_cnoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg, + &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, + &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_prng, + &qhs_tme_cfg, &qss_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc_main, &xs_pcie_0, + &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .num_nodes =3D 3, + .nodes =3D { &qhs_qup0, &qhs_qup1, + &qhs_display_cfg }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .enable_mask =3D 0x1, + .num_nodes =3D 2, + .nodes =3D { &qxm_nsp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .enable_mask =3D 0x1, + .num_nodes =3D 4, + .nodes =3D { &qnm_camnoc_hf, &qnm_camnoc_icp, + &qnm_camnoc_sf, &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 =3D { + .name =3D "QUP1", + .keepalive =3D true, + .vote_scale =3D 1, + .num_nodes =3D 1, + .nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .enable_mask =3D 0x1, + .num_nodes =3D 14, + .nodes =3D { &alm_gpu_tcu, &alm_sys_tcu, + &chm_apps, &qnm_gpu, + &qnm_mdsp, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_gemnoc, + &qnm_pcie, &qnm_snoc_gc, + &qnm_snoc_sf, &qxm_wlan_q6, + &qns_gem_noc_cnoc, &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .num_nodes =3D 2, + .nodes =3D { &qns_gemnoc_gc, &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .enable_mask =3D 0x1, + .num_nodes =3D 1, + .nodes =3D { &qxm_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .num_nodes =3D 1, + .nodes =3D { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] =3D { + [MASTER_QUP_1] =3D &qhm_qup1, + [MASTER_UFS_MEM] =3D &xm_ufs_mem, + [MASTER_USB3_0] =3D &xm_usb3_0, + [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, +}; + +static const struct qcom_icc_desc sm7635_aggre1_noc =3D { + .nodes =3D aggre1_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), + .bcms =3D aggre1_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] =3D { + [MASTER_QDSS_BAM] =3D &qhm_qdss_bam, + [MASTER_QSPI_0] =3D &qhm_qspi, + [MASTER_QUP_0] =3D &qhm_qup0, + [MASTER_CRYPTO] =3D &qxm_crypto, + [MASTER_IPA] =3D &qxm_ipa, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr_1, + [MASTER_SDCC_1] =3D &xm_sdc1, + [MASTER_SDCC_2] =3D &xm_sdc2, + [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, +}; + +static const struct qcom_icc_desc sm7635_aggre2_noc =3D { + .nodes =3D aggre2_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), + .bcms =3D aggre2_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { + &bcm_qup0, + &bcm_qup1, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [MASTER_QUP_CORE_1] =3D &qup1_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, + [SLAVE_QUP_CORE_1] =3D &qup1_core_slave, +}; + +static const struct qcom_icc_desc sm7635_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] =3D { + [MASTER_CNOC_CFG] =3D &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] =3D &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] =3D &qhs_ahb2phy1, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] =3D &qhs_cpr_cx, + [SLAVE_RBCPR_MXA_CFG] =3D &qhs_cpr_mxa, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_CX_RDPM] =3D &qhs_cx_rdpm, + [SLAVE_GFX3D_CFG] =3D &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_CNOC_MSS] =3D &qhs_mss_cfg, + [SLAVE_MX_2_RDPM] =3D &qhs_mx_2_rdpm, + [SLAVE_MX_RDPM] =3D &qhs_mx_rdpm, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QSPI_0] =3D &qhs_qspi, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_QUP_1] =3D &qhs_qup1, + [SLAVE_SDC1] =3D &qhs_sdc1, + [SLAVE_SDCC_2] =3D &qhs_sdc2, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] =3D &qhs_ufs_mem_cfg, + [SLAVE_USB3_0] =3D &qhs_usb3_0, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] =3D &qhs_vsense_ctrl_cfg, + [SLAVE_WLAN] =3D &qhs_wlan_q6, + [SLAVE_CNOC_MNOC_HF_CFG] =3D &qss_mnoc_hf_cfg, + [SLAVE_CNOC_MNOC_SF_CFG] =3D &qss_mnoc_sf_cfg, + [SLAVE_NSP_QTB_CFG] =3D &qss_nsp_qtb_cfg, + [SLAVE_PCIE_ANOC_CFG] =3D &qss_pcie_anoc_cfg, + [SLAVE_WLAN_Q6_THROTTLE_CFG] =3D &qss_wlan_q6_throttle_cfg, + [SLAVE_SERVICE_CNOC_CFG] =3D &srvc_cnoc_cfg, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sm7635_cnoc_cfg =3D { + .nodes =3D cnoc_cfg_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), + .bcms =3D cnoc_cfg_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] =3D { + [MASTER_GEM_NOC_CNOC] =3D &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] =3D &qnm_gemnoc_pcie, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_DISPLAY_CFG] =3D &qhs_display_cfg, + [SLAVE_IPA_CFG] =3D &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] =3D &qhs_pcie1_cfg, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_TME_CFG] =3D &qhs_tme_cfg, + [SLAVE_APPSS] =3D &qss_apss, + [SLAVE_CNOC_CFG] =3D &qss_cfg, + [SLAVE_DDRSS_CFG] =3D &qss_ddrss_cfg, + [SLAVE_IMEM] =3D &qxs_imem, + [SLAVE_PIMEM] =3D &qxs_pimem, + [SLAVE_SERVICE_CNOC] =3D &srvc_cnoc_main, + [SLAVE_PCIE_0] =3D &xs_pcie_0, + [SLAVE_PCIE_1] =3D &xs_pcie_1, +}; + +static const struct qcom_icc_desc sm7635_cnoc_main =3D { + .nodes =3D cnoc_main_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), + .bcms =3D cnoc_main_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] =3D { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] =3D { + [MASTER_GPU_TCU] =3D &alm_gpu_tcu, + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_APPSS_PROC] =3D &chm_apps, + [MASTER_GFX3D] =3D &qnm_gpu, + [MASTER_LPASS_GEM_NOC] =3D &qnm_lpass_gemnoc, + [MASTER_MSS_PROC] =3D &qnm_mdsp, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] =3D &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] =3D &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] =3D &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] =3D &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_WLAN_Q6] =3D &qxm_wlan_q6, + [SLAVE_GEM_NOC_CNOC] =3D &qns_gem_noc_cnoc, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, +}; + +static const struct qcom_icc_desc sm7635_gem_noc =3D { + .nodes =3D gem_noc_nodes, + .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), + .bcms =3D gem_noc_bcms, + .num_bcms =3D ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] =3D { +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] =3D { + [MASTER_LPASS_PROC] =3D &qxm_lpass_dsp, + [SLAVE_LPASS_GEM_NOC] =3D &qns_lpass_ag_noc_gemnoc, +}; + +static const struct qcom_icc_desc sm7635_lpass_ag_noc =3D { + .nodes =3D lpass_ag_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), + .bcms =3D lpass_ag_noc_bcms, + .num_bcms =3D ARRAY_SIZE(lpass_ag_noc_bcms), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI1] =3D &ebi, +}; + +static const struct qcom_icc_desc sm7635_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] =3D { + [MASTER_CAMNOC_HF] =3D &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] =3D &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] =3D &qnm_camnoc_sf, + [MASTER_MDP] =3D &qnm_mdp, + [MASTER_VIDEO] =3D &qnm_video, + [MASTER_CNOC_MNOC_HF_CFG] =3D &qsm_hf_mnoc_cfg, + [MASTER_CNOC_MNOC_SF_CFG] =3D &qsm_sf_mnoc_cfg, + [SLAVE_MNOC_HF_MEM_NOC] =3D &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] =3D &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC_HF] =3D &srvc_mnoc_hf, + [SLAVE_SERVICE_MNOC_SF] =3D &srvc_mnoc_sf, +}; + +static const struct qcom_icc_desc sm7635_mmss_noc =3D { + .nodes =3D mmss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), + .bcms =3D mmss_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] =3D { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] =3D { + [MASTER_CDSP_PROC] =3D &qxm_nsp, + [SLAVE_CDSP_MEM_NOC] =3D &qns_nsp_gemnoc, +}; + +static const struct qcom_icc_desc sm7635_nsp_noc =3D { + .nodes =3D nsp_noc_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), + .bcms =3D nsp_noc_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] =3D { + &bcm_sn4, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] =3D { + [MASTER_PCIE_ANOC_CFG] =3D &qsm_pcie_anoc_cfg, + [MASTER_PCIE_0] =3D &xm_pcie3_0, + [MASTER_PCIE_1] =3D &xm_pcie3_1, + [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, + [SLAVE_SERVICE_PCIE_ANOC] =3D &srvc_pcie_aggre_noc, +}; + +static const struct qcom_icc_desc sm7635_pcie_anoc =3D { + .nodes =3D pcie_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), + .bcms =3D pcie_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, +}; + +static struct qcom_icc_node * const system_noc_nodes[] =3D { + [MASTER_A1NOC_SNOC] =3D &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] =3D &qnm_aggre2_noc, + [MASTER_APSS_NOC] =3D &qnm_apss_noc, + [MASTER_CNOC_SNOC] =3D &qnm_cnoc_data, + [MASTER_PIMEM] =3D &qxm_pimem, + [MASTER_GIC] =3D &xm_gic, + [SLAVE_SNOC_GEM_NOC_GC] =3D &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] =3D &qns_gemnoc_sf, +}; + +static const struct qcom_icc_desc sm7635_system_noc =3D { + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,sm7635-aggre1-noc", + .data =3D &sm7635_aggre1_noc}, + { .compatible =3D "qcom,sm7635-aggre2-noc", + .data =3D &sm7635_aggre2_noc}, + { .compatible =3D "qcom,sm7635-clk-virt", + .data =3D &sm7635_clk_virt}, + { .compatible =3D "qcom,sm7635-cnoc-cfg", + .data =3D &sm7635_cnoc_cfg}, + { .compatible =3D "qcom,sm7635-cnoc-main", + .data =3D &sm7635_cnoc_main}, + { .compatible =3D "qcom,sm7635-gem-noc", + .data =3D &sm7635_gem_noc}, + { .compatible =3D "qcom,sm7635-lpass-ag-noc", + .data =3D &sm7635_lpass_ag_noc}, + { .compatible =3D "qcom,sm7635-mc-virt", + .data =3D &sm7635_mc_virt}, + { .compatible =3D "qcom,sm7635-mmss-noc", + .data =3D &sm7635_mmss_noc}, + { .compatible =3D "qcom,sm7635-nsp-noc", + .data =3D &sm7635_nsp_noc}, + { .compatible =3D "qcom,sm7635-pcie-anoc", + .data =3D &sm7635_pcie_anoc}, + { .compatible =3D "qcom,sm7635-system-noc", + .data =3D &sm7635_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qcom_icc_rpmh_probe, + .remove =3D qcom_icc_rpmh_remove, + .driver =3D { + .name =3D "qnoc-sm7635", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("SM7635 NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/sm7635.h b/drivers/interconnect/qcom= /sm7635.h new file mode 100644 index 0000000000000000000000000000000000000000..d5625e2971b36cdd2524136901b= 589be2ddafabd --- /dev/null +++ b/drivers/interconnect/qcom/sm7635.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SM7635 interconnect IDs + * + * Copyright (c) 2025, Luca Weiss + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SM7635_H +#define __DRIVERS_INTERCONNECT_QCOM_SM7635_H + +#define SM7635_MASTER_A1NOC_SNOC 0 +#define SM7635_MASTER_A2NOC_SNOC 1 +#define SM7635_MASTER_ANOC_PCIE_GEM_NOC 2 +#define SM7635_MASTER_APPSS_PROC 3 +#define SM7635_MASTER_APSS_NOC 4 +#define SM7635_MASTER_CAMNOC_HF 5 +#define SM7635_MASTER_CAMNOC_ICP 6 +#define SM7635_MASTER_CAMNOC_SF 7 +#define SM7635_MASTER_CDSP_PROC 8 +#define SM7635_MASTER_CNOC_CFG 9 +#define SM7635_MASTER_CNOC_MNOC_HF_CFG 10 +#define SM7635_MASTER_CNOC_MNOC_SF_CFG 11 +#define SM7635_MASTER_CNOC_SNOC 12 +#define SM7635_MASTER_COMPUTE_NOC 13 +#define SM7635_MASTER_CRYPTO 14 +#define SM7635_MASTER_GEM_NOC_CNOC 15 +#define SM7635_MASTER_GEM_NOC_PCIE_SNOC 16 +#define SM7635_MASTER_GFX3D 17 +#define SM7635_MASTER_GIC 18 +#define SM7635_MASTER_GPU_TCU 19 +#define SM7635_MASTER_IPA 20 +#define SM7635_MASTER_LLCC 21 +#define SM7635_MASTER_LPASS_GEM_NOC 22 +#define SM7635_MASTER_LPASS_PROC 23 +#define SM7635_MASTER_MDP 24 +#define SM7635_MASTER_MNOC_HF_MEM_NOC 25 +#define SM7635_MASTER_MNOC_SF_MEM_NOC 26 +#define SM7635_MASTER_MSS_PROC 27 +#define SM7635_MASTER_PCIE_0 28 +#define SM7635_MASTER_PCIE_1 29 +#define SM7635_MASTER_PCIE_ANOC_CFG 30 +#define SM7635_MASTER_PIMEM 31 +#define SM7635_MASTER_QDSS_BAM 32 +#define SM7635_MASTER_QDSS_ETR 33 +#define SM7635_MASTER_QDSS_ETR_1 34 +#define SM7635_MASTER_QSPI_0 35 +#define SM7635_MASTER_QUP_0 36 +#define SM7635_MASTER_QUP_1 37 +#define SM7635_MASTER_QUP_CORE_0 38 +#define SM7635_MASTER_QUP_CORE_1 39 +#define SM7635_MASTER_SDCC_1 40 +#define SM7635_MASTER_SDCC_2 41 +#define SM7635_MASTER_SNOC_GC_MEM_NOC 42 +#define SM7635_MASTER_SNOC_SF_MEM_NOC 43 +#define SM7635_MASTER_SYS_TCU 44 +#define SM7635_MASTER_UFS_MEM 45 +#define SM7635_MASTER_USB3_0 46 +#define SM7635_MASTER_VIDEO 47 +#define SM7635_MASTER_WLAN_Q6 48 +#define SM7635_SLAVE_A1NOC_SNOC 49 +#define SM7635_SLAVE_A2NOC_SNOC 50 +#define SM7635_SLAVE_AHB2PHY_NORTH 51 +#define SM7635_SLAVE_AHB2PHY_SOUTH 52 +#define SM7635_SLAVE_ANOC_PCIE_GEM_NOC 53 +#define SM7635_SLAVE_AOSS 54 +#define SM7635_SLAVE_APPSS 55 +#define SM7635_SLAVE_CAMERA_CFG 56 +#define SM7635_SLAVE_CDSP_MEM_NOC 57 +#define SM7635_SLAVE_CLK_CTL 58 +#define SM7635_SLAVE_CNOC_CFG 59 +#define SM7635_SLAVE_CNOC_MNOC_HF_CFG 60 +#define SM7635_SLAVE_CNOC_MNOC_SF_CFG 61 +#define SM7635_SLAVE_CNOC_MSS 62 +#define SM7635_SLAVE_CRYPTO_0_CFG 63 +#define SM7635_SLAVE_CX_RDPM 64 +#define SM7635_SLAVE_DDRSS_CFG 65 +#define SM7635_SLAVE_DISPLAY_CFG 66 +#define SM7635_SLAVE_EBI1 67 +#define SM7635_SLAVE_GEM_NOC_CNOC 68 +#define SM7635_SLAVE_GFX3D_CFG 69 +#define SM7635_SLAVE_IMEM 70 +#define SM7635_SLAVE_IMEM_CFG 71 +#define SM7635_SLAVE_IPA_CFG 72 +#define SM7635_SLAVE_IPC_ROUTER_CFG 73 +#define SM7635_SLAVE_LLCC 74 +#define SM7635_SLAVE_LPASS_GEM_NOC 75 +#define SM7635_SLAVE_MEM_NOC_PCIE_SNOC 76 +#define SM7635_SLAVE_MNOC_HF_MEM_NOC 77 +#define SM7635_SLAVE_MNOC_SF_MEM_NOC 78 +#define SM7635_SLAVE_MX_2_RDPM 79 +#define SM7635_SLAVE_MX_RDPM 80 +#define SM7635_SLAVE_NSP_QTB_CFG 81 +#define SM7635_SLAVE_PCIE_0 82 +#define SM7635_SLAVE_PCIE_0_CFG 83 +#define SM7635_SLAVE_PCIE_1 84 +#define SM7635_SLAVE_PCIE_1_CFG 85 +#define SM7635_SLAVE_PCIE_ANOC_CFG 86 +#define SM7635_SLAVE_PDM 87 +#define SM7635_SLAVE_PIMEM 88 +#define SM7635_SLAVE_PRNG 89 +#define SM7635_SLAVE_QDSS_CFG 90 +#define SM7635_SLAVE_QDSS_STM 91 +#define SM7635_SLAVE_QSPI_0 92 +#define SM7635_SLAVE_QUP_0 93 +#define SM7635_SLAVE_QUP_1 94 +#define SM7635_SLAVE_QUP_CORE_0 95 +#define SM7635_SLAVE_QUP_CORE_1 96 +#define SM7635_SLAVE_RBCPR_CX_CFG 97 +#define SM7635_SLAVE_RBCPR_MXA_CFG 98 +#define SM7635_SLAVE_SDC1 99 +#define SM7635_SLAVE_SDCC_2 100 +#define SM7635_SLAVE_SERVICE_CNOC 101 +#define SM7635_SLAVE_SERVICE_CNOC_CFG 102 +#define SM7635_SLAVE_SERVICE_MNOC_HF 103 +#define SM7635_SLAVE_SERVICE_MNOC_SF 104 +#define SM7635_SLAVE_SERVICE_PCIE_ANOC 105 +#define SM7635_SLAVE_SNOC_GEM_NOC_GC 106 +#define SM7635_SLAVE_SNOC_GEM_NOC_SF 107 +#define SM7635_SLAVE_TCSR 108 +#define SM7635_SLAVE_TCU 109 +#define SM7635_SLAVE_TLMM 110 +#define SM7635_SLAVE_TME_CFG 111 +#define SM7635_SLAVE_UFS_MEM_CFG 112 +#define SM7635_SLAVE_USB3_0 113 +#define SM7635_SLAVE_VENUS_CFG 114 +#define SM7635_SLAVE_VSENSE_CTRL_CFG 115 +#define SM7635_SLAVE_WLAN 116 +#define SM7635_SLAVE_WLAN_Q6_THROTTLE_CFG 117 + +#endif --=20 2.50.0