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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0aaa0a854sm270277766b.68.2025.06.25.02.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:23:09 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:22:56 +0200 Subject: [PATCH 01/14] dt-bindings: arm-smmu: document the support on SM7635 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-fp6-initial-v1-1-d9cd322eac1b@fairphone.com> References: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> In-Reply-To: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=1465; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=eQWT5rynZ1PMaMurlFu0xtL6k2P+7npo9dOzB+6rBOg=; b=gDsmUgdZBFiEdwrYEbZ8pi64XslJKaJrZmQirkFpqMll05JV6aPCYeaepteR65EJtYCQZk9aa 7x2FpL//Q9vClR/bmMVFhIADOJuoW9AUJVzbXxYdMo+K4lm7WiiCaKO X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add compatible for smmu representing support on SM7635. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Docume= ntation/devicetree/bindings/iommu/arm,smmu.yaml index 7b9d5507d6ccd6b845a57eeae59fe80ba75cc652..8545dd8e886b265caa333188c03= 1f19a44d7fa6b 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -55,6 +55,7 @@ properties: - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 + - qcom,sm7635-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 @@ -99,6 +100,7 @@ properties: - qcom,sc8280xp-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 + - qcom,sm7635-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 @@ -535,6 +537,7 @@ allOf: items: - enum: - qcom,sar2130p-smmu-500 + - qcom,sm7635-smmu-500 - qcom,sm8550-smmu-500 - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50E4D2D9EFA for ; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0aaa0a854sm270277766b.68.2025.06.25.02.23.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:23:09 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:22:57 +0200 Subject: [PATCH 02/14] dt-bindings: cpufreq: qcom-hw: document SM7635 CPUFREQ Hardware Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-fp6-initial-v1-2-d9cd322eac1b@fairphone.com> References: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> In-Reply-To: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=1256; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=cHqszQuBCaVtspU1t7iOjEc+5vwmG2p0Bi0y4m/DFOg=; b=kCR5siUeapo7dxDWp4dWExqPF+lGnBc97GFA4dxfQD8XoZ1lE5aOP6CJT2iAzeOSwdIFhC4/p Z4uY5ayq4rUBb21sP5ZjkiYsj+KLEC4ZuYf4Q18vGbyiwI2d+IWW6Oq X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the CPUFREQ Hardware on the SM7635 Platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e0242bed33420a39b8a8cff4229ba9eee994ca30..58a2222574e57a8f9c114f5fc3f= 0aa19d9794965 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -44,6 +44,7 @@ properties: - qcom,sdx75-cpufreq-epss - qcom,sm4450-cpufreq-epss - qcom,sm6375-cpufreq-epss + - qcom,sm7635-cpufreq-epss - qcom,sm8250-cpufreq-epss - qcom,sm8350-cpufreq-epss - qcom,sm8450-cpufreq-epss @@ -169,6 +170,7 @@ allOf: enum: - qcom,qcs8300-cpufreq-epss - qcom,sc7280-cpufreq-epss + - qcom,sm7635-cpufreq-epss - qcom,sm8250-cpufreq-epss - qcom,sm8350-cpufreq-epss - qcom,sm8450-cpufreq-epss --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E64F25A2C8 for ; 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Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=870; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ARurSlf9cAaTHf8riWzBxjObIWFoiMC+3sc1W+uG3PE=; b=s58rpWvVx4KEw/gWNPIbo8A+oAxUDMuwW9s3oTq9LY5OoYgLguK+Onhp3DmRNdPW9BsH3qKmf 59mx2TZBcoYBb+w1bKOg/GL7crYXeJ4Hl7R0nL42pqDOwmT/DDnmfr5 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document SM7635 compatible for the True Random Number Generator. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Docu= mentation/devicetree/bindings/crypto/qcom,prng.yaml index ed7e16bd11d33c16d0adf02c38419dbaee87ac48..c34a4267a0d5292e89f61c766c0= 8e7071bd2ff09 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -25,6 +25,7 @@ properties: - qcom,sa8255p-trng - qcom,sa8775p-trng - qcom,sc7280-trng + - qcom,sm7635-trng - qcom,sm8450-trng - qcom,sm8550-trng - qcom,sm8650-trng --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE8C52882CE for ; Wed, 25 Jun 2025 09:23:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843398; cv=none; b=R9tX1+z8aCyDZiDgHnMTBMUKVI1xeQUOQzXJwR8FKpiZC0DZPtZVJR5HLKl9Zbml9LPVekacpB7MHokjY1ExLB3eFIYO5tUkI1eUmcHIJ16dQBllKD8T0dJ1Q05u77yvJR1xJrdKzf7sqnUwETptfPbxIcXoG+MYXyrAj+4wydM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843398; c=relaxed/simple; bh=uhtUa6TuWWOeZjd4JmW5ZGjrlr6PTEqwVAXpwJZmwlQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Dy+fU42KfIX4IhBETTycEUTfZ/9P/+QF8x446Ad1q8aYs7x790j7miUXildt6AG42CskCBSoLe391Iuft4VDeGPF6XB9mX91I7wDHJMgup3DclIZv/fmEZKvSD2zg55WR1bFYIfHoyp1mxKWWq3Kpz9EDmC0fh9Nmr6if99tFfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=O6GlR2UV; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="O6GlR2UV" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-ae0b2ead33cso136825066b.0 for ; Wed, 25 Jun 2025 02:23:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1750843392; x=1751448192; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/iV2ZnPzTHx850i93QH2RHh5n0N52PnUpwC+aDpzRmE=; b=O6GlR2UVKmA+vRZ6sretyLcRkZH8+dnknTASGFtbFQ8CH32Vsxl9tlb17kWfAgHRfx wwnq0H/+GRLW7F6Q+4IGOZDQG+bPfDPY0Cj8YqWGCv84Lv8Wfw0+WSIiQO/8lXGh+ZpA M2zitDv40gMjsMe/6f1/hwUAwQEQk/c3m6StEJRB5qovZBcybrUanrcnAHjsJW94jL3H VUArGdbkMxHnJSsCCmIR1BPZdzGzHBxMz0JuGUfvDwYwdib8EzlmL/zVY7gXi2Q0XkfH 3EcCJDszdoQhhUTXbJ0yFmxDMdjhagaStygqVmfZVifs4gmFBCPh5N+0zoUPr/VH9DA8 U5Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750843392; x=1751448192; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/iV2ZnPzTHx850i93QH2RHh5n0N52PnUpwC+aDpzRmE=; b=BAE80UiCOB4mjJShv3o1fc82nf44vsBNJ7MGkWJ0SuFqFZDAT73HnfmvTDleGUtiAj SE38UVENeIBb83uw0EVlG4gDXELTjp0vREvbc8k8TYzOMv+7oEGsYn42XsOS0Ov4lJC4 RcgImZG3MYqHgWzZ6zzlIxB2XSASyZvuiGErRRO3YfFNPsydOjtauIgZGUHmVEtiz1KO BPRtD5aQBqHjFpteLM4ibxzp38ydkilgu5m3/gHnQrIIHDZJLRQgPAjmdSwhJ9rIP1QW 1Y8m5NfZlCgXej1jW0dNKMooU7U5LWvXnsVYFlynP+XAe6MqQobcwtpXu+zMwy9kFsd3 28Bg== X-Forwarded-Encrypted: i=1; AJvYcCV7EIyQBRUlEIyI076GwzlTvCl2oF2G+1xYBZv3kRwQmFMBphwUMqXWEwU2k8e29koeTiM1C6ZjKTMyDq8=@vger.kernel.org X-Gm-Message-State: AOJu0YyVKHjqkuz5JKZ8EKZr8ZkvKatERevn5w1C7jiTSA1r2tni96gK va8W+Z2CK52MmRBu8FnZtjbU879Eba7o2JGPA6tVjFVKfnZoCB3fy7kMWR+kT+2ePoA= X-Gm-Gg: ASbGncs4frLVwsdWw+hROherA/spD/HcAk8G6WqgeGivDnQZ1fdln+qcO5/3ee7YMXh B7f6U9r6mPaFhkiTT6P+90+70t3aeAzeKdHH9460/jGj7agkA45nPfNoUakRjzKKcIIIXooEh13 vEXvV1UvvTTbmd7KcIS2c9fBg/HAu6Gg+h2Hz+fX8bvU0qsTodBPmB1qCWFgzaOVMo//fII7IkF hMsYxvkIcbi6xpKtYkFrFIby24T6wL1n1mTeUVgkD8ICllg1fY/auC1ZUdyBV6+V/oQrVhA3F9q /lT2ID3Okx8ViAsPPr/QndZ1G5xfIqkfsSywZPD9ZtopMIOH7cEE5fLmMqcG1gAWUSHM15VKy9a 2nG3w28WhF5hwLb10sVNmHQqpan5Tlpm1 X-Google-Smtp-Source: AGHT+IE1gc/uvw/ng78i+q8hHmGEhnihasoPg2pJuO7nZfnd78u9Q+SnvB0RXN8h+HquieGEdTPAUQ== X-Received: by 2002:a17:907:c1c:b0:aca:95eb:12e with SMTP id a640c23a62f3a-ae0c082c6a9mr173270066b.24.1750843392378; Wed, 25 Jun 2025 02:23:12 -0700 (PDT) Received: from otso.local (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0aaa0a854sm270277766b.68.2025.06.25.02.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:23:12 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:22:59 +0200 Subject: [PATCH 04/14] dt-bindings: firmware: qcom,scm: document SM7635 SCM Firmware Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-fp6-initial-v1-4-d9cd322eac1b@fairphone.com> References: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> In-Reply-To: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=1077; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=uhtUa6TuWWOeZjd4JmW5ZGjrlr6PTEqwVAXpwJZmwlQ=; b=P52I7QLzFA0XxGiWQVSrZWCETXtQVh8QX/bEHmeiiACmOITY5bmcMCEU3Bv0O7QmN53S50sov SnkXYx/JOQTDQpqfdQvrqFD3cdiTSWKxRGwqgKDTvPdxi2Nq493mxam X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the SCM Firmware Interface on the SM7635 Platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index 8cdaac8011ba499794ebc5b4291b7983c209821b..6ae7405aac658ed5c3524ffc394= d845cd2f42798 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -63,6 +63,7 @@ properties: - qcom,scm-sm6350 - qcom,scm-sm6375 - qcom,scm-sm7150 + - qcom,scm-sm7635 - qcom,scm-sm8150 - qcom,scm-sm8250 - qcom,scm-sm8350 @@ -198,6 +199,7 @@ allOf: compatible: contains: enum: + - qcom,scm-sm7635 - qcom,scm-sm8450 - qcom,scm-sm8550 - qcom,scm-sm8650 --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB4922E0B40 for ; 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Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=893; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=kMLBa8XpPsXDlevy1KezXuXVxIBGJ+gP0d2yYQ8HaFg=; b=mdr+a+luUjX7AFv2DO5FQDsLMYgOBVUahwjTho7Ooy7Ze3zZt8tNJoSuRat0p8SJ/e1grPELu 6pVuw/hE3yPB2VtbzJkUjC9SFW/NHJPRSwLMfmGq3pXJPW/wvwZrJgp X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Power Domain Controller on the SM7635 Platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index f06b40f88778929579ef9b3b3206f075e140ba96..e809f50734bc3136a8915a12a1a= 1cba2bdb62890 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -43,6 +43,7 @@ properties: - qcom,sdx75-pdc - qcom,sm4450-pdc - qcom,sm6350-pdc + - qcom,sm7635-pdc - qcom,sm8150-pdc - qcom,sm8250-pdc - qcom,sm8350-pdc --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A43572DECDA for ; Wed, 25 Jun 2025 09:23:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843400; cv=none; b=VknStUfxdxATC63eJR9IgO330pe183roUank4kj6J/TiAQUsQuG8vJTk8W40S8NHGV4ivdJn9p/KbuYYpMLX69AXbsWFus5wyd1k0FA2o6kKCGKP7TV2YLxPeaQ4Udy0tvG5WnguSpWVqgywcn2uOtmySoi03TktcJpSaCHkAEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843400; c=relaxed/simple; bh=a9FLQid58ZrqwhwDBssnIOsYiwypbHIyY+vO7BVtkJA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=onNU8Bs+BRkttP218BKAA4sf7pWkPqQerahd+jZifZuLSDIT5aZch7TcaJRb3Cc00RRLjJLmT8JnS3qhneTgzMUOOtcvbMNTA3EMowrrA+1Q+IfTYZkIG+afCdCxNJzn4EQqNKSCk/Mpmcha1QZ1ogMIFzWtvbNodVd1oFrk12I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=o61iw4TZ; arc=none smtp.client-ip=209.85.218.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="o61iw4TZ" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-ad883afdf0cso258086166b.0 for ; Wed, 25 Jun 2025 02:23:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1750843394; x=1751448194; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GFd2WA4jaSsi6eBpJft54R30VZiUHUNL0WjIOmacH+w=; b=o61iw4TZFyTkUIj7PoZHMG4mEEXTObVv8UmhymegOnr0oJbZOhDbz/N3MhtbVS+84z xBeAFOQadwVcJSYBQsAi0wnvAnopcfdR5Z5USYokbRvfT2Dz2Z/jq8VGofmftPZLZ1n7 UiCGfLxSUFis697RiT/wcY2Q+rtRPdNzxoulxY2wZHZ0SUhXkrcOzrlWFdgUflna7wu1 GIQjqluIjgCYO/UU2o8YBNx+LoFKZAru6S/w87lsmzFEoog144obDT0KNuvpjTp5G1A9 n6jbMtQQb1NjDQk+8YREn09s/qo8G1KOIBdGQlQM9CFsubr97cc0zVjUJqXHp1g56Him VwGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750843394; x=1751448194; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GFd2WA4jaSsi6eBpJft54R30VZiUHUNL0WjIOmacH+w=; b=MH2r8/IiaIqPf+9yw9D/A/X/jyfZwvUiKFJPuRNxuuHOjN12z1bNw3ibwiDoH58TEG ideXuBLnyYmqTQyu3Wii958W67Zm0jd3iDnsTleHCElH8QP5MdzD1yA7fH4Ca1ke6Ash +a/NJFgyrpK48wYOJ/eBs9oMWt5Q2IF3czbz4KcoSbfLu8/eXZqpRgDLE3Yl5kXA6x6A hTVF6Qp++y/QzHjHYCWa4aZQzQdcuD/q2z+BHYN4bDIOg3iewePk1OoWoEmFcsY5Tplm oNI0oQLEw3bp380WgNHYZ0DJDCQF2GVu9JqsAR4OHfmAr0AwAJjuOZQCYshoUbbZ087R +tcA== X-Forwarded-Encrypted: i=1; AJvYcCVWvQ83gv9Iy5HiZLB0ZDJxX6ohHbeHCZ1tDAxpU9FSrvJ8eHGZOTpLeARMUEn1qCnqvcM0E7LFxQ8lvsM=@vger.kernel.org X-Gm-Message-State: AOJu0Yy8AHgEDJUG6wVgA+yRts8gjXYTQ4agPAHaBrvzxYmnT10KRPJp sifc9AXN4Ag9X+D5qldqo5k7RHY7PU0Zld1tEvZtgw/JbxmFn0phECQP50QgxONnlts= X-Gm-Gg: ASbGncuf+1uHQqgV6VlMoVJnuBtomsg64FZYncs5bW90PZGuawx/ayLbmV5gvMIrAp0 N1EtCDdw/sIvDdVsxgdreus7GEfo6I0gRAX6jTpDVuonHlku0Vg+fGC87CcBt4How8m0jMQQQhV GI52ao3GsdOg05hGzBMnEfBWrtptw9Y1wsP3fzM+gXEb0tMvzcflSPZKsg7FiX7TGBD8z2Dpz/b c+GmDf8W1KriFRWCmS1rsMYclLPBR9ls0Td3L3ywXfqTn5wmumCtARBqEI1tHW5jLvgGaG6v0ra 0Eta9g75E//Ge4aNTg8/ILI1xLE/QPZnu6zJyC+HNFNrLVb9AVTFAFNYHg9S4rzD4yUqV008Hc/ 3jhTTj1TycpVxa4/SpFGXg5rPxwtLbL8K X-Google-Smtp-Source: AGHT+IFjoA9LH+UlMYELvwOrDva8TbPECUBoKhrTSDmX1S6yeylMCFiLfASmbkP/9St1GzH8r2022w== X-Received: by 2002:a17:906:6a12:b0:ad4:f517:ca3 with SMTP id a640c23a62f3a-ae0be88335cmr241931166b.20.1750843394339; Wed, 25 Jun 2025 02:23:14 -0700 (PDT) Received: from otso.local (144-178-202-138.static.ef-service.nl. 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Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=857; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=a9FLQid58ZrqwhwDBssnIOsYiwypbHIyY+vO7BVtkJA=; b=M++/VIb7y2T3gKskIlMpYOFvxwe+pfbHdhyU9gVdbfRegUxNj4iL+n141nUA1eMcP60CaNCwr IDMwEV8uYYeB8lGGvP/UKlrX7LWLDpIcdln/9pd8d17sYlzfKKWktV/ X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Inter-Processor Communication Controller on the SM7635 Platfor= m. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Doc= umentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index f69c0ec5d19d3dd726a42d86f8a77433267fdf28..6e86ec36a82254ebd73c3067de4= 95795c36c6bee 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -34,6 +34,7 @@ properties: - qcom,sdx75-ipcc - qcom,sm6350-ipcc - qcom,sm6375-ipcc + - qcom,sm7635-ipcc - qcom,sm8250-ipcc - qcom,sm8350-ipcc - qcom,sm8450-ipcc --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 760222E11BB for ; Wed, 25 Jun 2025 09:23:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843404; cv=none; b=A2eA8H1exEs4npFIWFKdykiNlNDJJWA0aF0l1/3CnPiYap7JHpqw+RW68KEPEGMsHGCpjd1VYNXIZ6E12xig/uoGMfUaftTGnnwBWk9W0xviaqGDB7O+awshtoazLy4gd7b2QpvehByN5Yzk6SEeM6h5FW81mw2FoT8OraNecoQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843404; c=relaxed/simple; bh=C2JtTvyb4AXtbDuTYKqVJriQ2UbwtZ/ycgN9VosRmWY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nC3CcI9glEkXiKXadg1+spxvG5QU6bgSMp+/iaHs2n6xVs02SzUqZi108OdeoXahhZQBn60jJTpt85WBd5G1ECg4Bi+4mnd8QRXH+kV8j2UpSJbgJpcw5BnDjxdRmqDpKuXa++GabMN47yBuOETXowXCq66OPy1RWMZQNzrVhXc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=LvydARHx; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="LvydARHx" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-60c4f796446so682867a12.1 for ; Wed, 25 Jun 2025 02:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1750843395; x=1751448195; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cbAxlNGNMBjPB368qsF4KlT8ElPeOLO2pW0abGoJlYE=; b=LvydARHxuzFxtCfYscyeGvnu/FsA34ENHBLug4havR/GAfJjtcgjud1oswyXYJEGy/ 18UVrovKSP7pci7iUFXIBsoy7o297dX//je7PPKjyGig3UQLEiXTAKzM94dvClfXnKf/ eNAK9I6SOsIKRVnDXQ2qByOHUGY7tkhoEw2QBjIj8xH7u2y+T4vAelk4B0bTp3ZQTYGR oUNxVEexRMVH20ICaBFC/TsJ1eEMZzFU72nIXwPnYstPl7+aqLvx1Lyanu3MU8gY/acD 8h2Ili+bwlMoAQjEDVMcnB2H4J5nnsyfbvXTIMnWk4VISDwG3x7W+Cv2qKPetmsCXpu1 8Zww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750843395; x=1751448195; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cbAxlNGNMBjPB368qsF4KlT8ElPeOLO2pW0abGoJlYE=; b=b1lugdjyM8KXy4ObUaWb3zxbkq69SCwA2kpkODvpNlMOQlhNAFWufJdEfY7FxOvwZD T33A/QM+u7LWCXzpK73alfvTtdeuUnJe3biiTtzYinxcVDtGHysdrYMksZduUT47zt87 TF4RNHK5Wkk9tNTsmAIm6d7GTfiS4o5H8JB9CPPNv4f8cKNQWwXl8Sth6QM+v4HWwnSc XcD5p8187Q5lfQHdWxbTiqMis+O6b7Nkp97zUnXbw67SheJvTRVdyfzWTROUv+P2OqKc TPBK3wPYzUuSlB1LFG1PaDMftROWCl/tsbDKN08kSbksJXoTG/wGvr7OqMTRc0E9E+dM fg4Q== X-Forwarded-Encrypted: i=1; AJvYcCXMn/verYLxiIo7TGneLGpW1w+yYA0Q6vGAc1W/NFRybuTe2Hw0IIMVFXeyJvx00tZfz1KGXYFch7hkJwI=@vger.kernel.org X-Gm-Message-State: AOJu0YwExha0sPcB1wwAMsqQa1Y0oVAYS4TyfpEJd0/252tLdgkur8n8 sh9EpHpkoQl43Avsgpx74hQxFmeq0mTgrDZiytW2ET5qX4NkeG3gSTrcsemowxi2/uc= X-Gm-Gg: ASbGncvzazAe8rHNU8YwJMLGUhFv/uDKyMU3UCp51AuwX8cJdGr874Bors6hGpV7mU0 ugX/ltL8d4xb86eR7bcSHL8BYW86QFbWBmDwI1sa8nZXg4XtyHR2b+KmxahgLkGeCiqneNlY9k6 aJi3hS8l0vWHknIjJmArxvsM4BpTE0x2YR4/myR3LAY8UAj//DB3YwQ6dPyPvfourzzN7U1mULx KqeALoq2YVROuopsiaUFROkwBi5JVw8/eeJhF6wCwAWrhvN4Zv66J9LjohUfM43niZEWFvdH2hd /QhUJSy8aaH7f4NxGC874P2YRmcCZp350RREJKhMDKSSy22KZeagqoVX1iHPCNAFkgPXr6mxlNa ztqHJtmSM8ZYohtdynDuNsXLoiV2k07Wb X-Google-Smtp-Source: AGHT+IH5Ea6Oe8g4N7kGjKPuq2Ehn1sdorRYiGI7t0sOOA/sE5jzxQrPTZnHeS3tOTzbYiDpRieahA== X-Received: by 2002:a17:907:6d0b:b0:ae0:c539:b89a with SMTP id a640c23a62f3a-ae0c539bd16mr168789366b.19.1750843395300; Wed, 25 Jun 2025 02:23:15 -0700 (PDT) Received: from otso.local (144-178-202-138.static.ef-service.nl. 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Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=902; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=C2JtTvyb4AXtbDuTYKqVJriQ2UbwtZ/ycgN9VosRmWY=; b=NfoI5zbKRHbMeTR2sEabxYna1BsVoqMJWG6yk0k36XGqnYtuT0/2sUxemlmo/hi6+elMefc19 3axPadbKyacADeOKyW5Iv0bjZ9mnmTelUfPVfAa3dsIc/MTy+uREFd/ X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Always-On Subsystem side channel on the SM7635 Platform. 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Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=884; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=QF6zOzPisaNRx6UkDEnfUjzHboUeRh3pRf3riJuZ07g=; b=u4p3k6p/2j42YHb4XwcyOL+Rq/CqQjib4+cSu01z968A3xXWkhEPGtNDUd9b2G12MuzVho+Uv 4c01+k5CLJPAHJpvg+Bz4qlPQ4Hme44CNKKgFxwQ8y5DARbiLPoZmDF X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Temperature Sensor (TSENS) on the SM7635 Platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Do= cumentation/devicetree/bindings/thermal/qcom-tsens.yaml index 0e653bbe9884953b58c4d8569b8d096db47fd54f..76b3d4ab5a793a9bd675e52a348= ca2d62077cf58 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -65,6 +65,7 @@ properties: - qcom,sm6115-tsens - qcom,sm6350-tsens - qcom,sm6375-tsens + - qcom,sm7635-tsens - qcom,sm8150-tsens - qcom,sm8250-tsens - qcom,sm8350-tsens --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 700042EACE9 for ; Wed, 25 Jun 2025 09:23:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843405; cv=none; b=md0/KivltGzbHqjw2cTNyZiGVPZUP27WgvKPvMNhHjw8gdBJ+Jo3hEYa76Z2xyJjUTrLDoBEVn0doKpQ0cIWztDdIWBVaZSHtdz7FQFcxMzGrhEgpcp1E27s8LDOy/IkMWJRjfFkwlmOTWyUQt/zpG1ny+pnoY/mKjfYTmXEr6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843405; c=relaxed/simple; bh=YagMwxq7U7yWw9QLdcfac7nNwnvk1Yv3KEQc1uEZcGo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NVY0E1Hwk8nVKn742lUqGSfcDX7wb23g+kvWHs0JVa3nlEwuROh9RDxNLwkOc+2yvmf8U5DU0dcznlwGlVrz6KcgBNE+3RZTsdKPh8tlrNAsQlK+B/N7ZC88i/9HbGzxp/MzrfwFokwiI7XvxqtjCH1FTm/HtUkY/2t8gK1rTOg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=A3D2e6Wz; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="A3D2e6Wz" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-ae0a0cd709bso145680166b.0 for ; Wed, 25 Jun 2025 02:23:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1750843397; x=1751448197; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KpVu8A0fOF6COL52SrecDnHkcknnFYzJmrqkhyu0QC8=; b=A3D2e6WztMmy4jEZ3O6D1dgczvWWyyjAzEZFNOu2sSsJCYqOlr2kePhIDgigvRMElY +lFaLBiLHVk4ZD8KnA19OGBYvrjljoHonQwlRAOQFvI+ku+NfGt5DXsDffQTdR8vOIbm orwyEvv+AKaLDURSy+uaok56/Xf4sNkrAVEHGZU3uGlwVsdl0wuttxMC13S8Eg8SoYzU Gsx6lTpDF+XGS/6gUubDowRK6rcT5BVfFNgMidaVlaQf0LnajYRXUfZ8FlEeWBfyFidy Tl1j+tw2BKTSzMK9C1P657kaKxYxNRXi9yHJQN8eBAOsuoa6vAgOWbQWzOG+m67LIACj fllg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750843397; x=1751448197; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KpVu8A0fOF6COL52SrecDnHkcknnFYzJmrqkhyu0QC8=; b=pOeNQSlSYfGHEQ8YC2T7LPLIlZX6wtxkiXryhN4Gws4lFWbmnaYA02rxYq36Fbcdxe +Ovt/+ZEuFFoLRdod/fU9ta9GMgk4vFU+9njXWv1dmd/8Gf1CaQw9fASGRyZtU9mZVBa KrLMkwulzpMbcoTVejCW2Lt6vXJNKJ4b30CLR/fFvvhevptxsm5aTM/yCKbHTnpTzvzd gnUN5f/q7oLOJswntrwM5HkLt5oPCVAgnvzF0CvK8gtk147tUaI7niB0aG8LGQ6u7tmy PYET5LyMuuT7yG9XFgpPuazL2+5Xsf+Ygj2Zo5hE9Esx/UN9jRLoQ4ig2a8PikfJbdjA C+6g== X-Forwarded-Encrypted: i=1; AJvYcCWUko8xTkp5Je+tq6ok52A73l25So81X1nTVMCbA3n2dxMGGt983qS7ZIn2kXJzkXQxSRg/NLzal3j67RI=@vger.kernel.org X-Gm-Message-State: AOJu0YwxCF0+6epMAauZY+MCi/c9d6tcPxa9m2aQkxHb9R+KfFs+0VOo zSLM7DMdQNkt1Y7W2B2xYj9R2wwDs0LWXZMj78RXTIFe/PhA5qR0PClEnK3JLW0Q6EI= X-Gm-Gg: ASbGnctnBwHsBD+ZQwuTzj95sN8uPkMntetiz5OkJlLxdSf+Jt/eqgmTRcfCihgACuK 9Kk8GaXN6c1Eiqv/WDip14M5/vZx7/LZ5WVMH9idORcQW1eUgAQvcYo/Izuy0Rb1wHqn4WQgJY2 7qQNutSJ+MUPqXU5Lob8wUe5DZES4TNRJAkDgmCy47vcwDXrP16uKYhqMX0Dfq5khMKfPB4Bj6L E5fpNVcNB/SgEcoQH3/xeUS+FNV811eUnnfR67GIVh+K2Zeg4x9bDHvhW/N2Wvc5fFXlDoD1V2w 8+kWk8C0ZG+u/bQeUFCqvMAIKh4zvkhHqvoPIR87rCyCHWfaxypzNXC4EwvPqN0XVCsJLS1m8NN nBXufzjEPSlJTVBdXQE/DbLiHXIRBfnNc X-Google-Smtp-Source: AGHT+IGs0JOq47ozJxO/VRAvUrQrVeV04oDsRGncO0FlhvJG+pk9vEPKTSD0ngky9ofslW8b5sJSPg== X-Received: by 2002:a17:907:9715:b0:adb:2f9b:e16f with SMTP id a640c23a62f3a-ae0c07dfb11mr197384066b.16.1750843397407; Wed, 25 Jun 2025 02:23:17 -0700 (PDT) Received: from otso.local (144-178-202-138.static.ef-service.nl. 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Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=855; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=YagMwxq7U7yWw9QLdcfac7nNwnvk1Yv3KEQc1uEZcGo=; b=tKVOirX/O5H1uxQ7HfeyAyYM5D3We6xzlJ6UXlJXIztsBOvAfenyp7TbfJ/uAqV/GmjIz7RGD 07DUBwDoCwrCGr+c0KI+9cEHz1aYwkDjfvuOUxmsPxCvypnlcx1nV7q X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the GPI DMA Engine on the SM7635 Platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Document= ation/devicetree/bindings/dma/qcom,gpi.yaml index 7052468b15c87430bb98fd10bc972cbe6307a866..051b90e57d5ff42f82cd803521c= 48498ce6af35b 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -33,6 +33,7 @@ properties: - qcom,sdx75-gpi-dma - qcom,sm6115-gpi-dma - qcom,sm6375-gpi-dma + - qcom,sm7635-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - qcom,sm8550-gpi-dma --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 153432EE965 for ; Wed, 25 Jun 2025 09:23:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843407; cv=none; b=a3aqko+wDy8Tt7v2B5n/m8PKD5mpKRGX7qsRwqEyM8rEFlwXUl1jHMjZFtvWFRMzEU+kxZfc5xtpRasnnTy4RtsEcy1GShpiYVqiqKugVUHKwOcl55ShpcBVy9axOnvg897qA1/4r30TXinfqn60GGtZX7huzlMB+g3GC+anjNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843407; c=relaxed/simple; bh=9mNvIjwX0GVg9+8QJn8ze4jldqNBVe9LJDYJHk6E7+Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Km/VjoKdzeBVB+p7SMtVh289C4Fma84b84SRW8sQ4zPgdii7MgRg65p/mAUwVxIP1llPipTi90xKdMuNaQWZFzwCp/KSr9ohalqZmpjBmhudC2ojdj3AsWA6c9krVw7f2Xx5+qSIc+PXfDWYx6hVLHiSj85Ec9qqPvHqRapjtYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=niQJ8xYS; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="niQJ8xYS" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-6097de2852aso1765377a12.0 for ; Wed, 25 Jun 2025 02:23:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1750843399; x=1751448199; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=w3nipzKoLXU+khkgMT/iFK8MpGbKtAwTRvPNEeh+QTo=; b=niQJ8xYSkVwf+6xQsuuqZR5H6ES5aY8g9hs1GIGBhSdSVk4r07+N7nxdeoBrSIQEiQ a/KLk4+xMFs/rNSTKcrzTqgzhYoOwCh2jzVvKpYBQxRQOxZad1ZDGSCxE0FLSqaR9sFA E2Key73LclGtxtjAJfaNAX6BjxvMOKy6iCSkDqUjQR+QTbCdAsPMFITOGyJ8wC3418Xz SOgig9vE0ZMCGpNyMyE2Hwtg7BhUvr2sjuUI4zOD3zTnNHRD3fTpR8RKrvFxY65VUlTR 60WRWGHawqTHZ0viLDD3LwzrcRb0qT1hQQWcpx4zit7kfq1+Hi27FsYYh5OM3obNT0bW UP1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750843399; x=1751448199; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w3nipzKoLXU+khkgMT/iFK8MpGbKtAwTRvPNEeh+QTo=; b=X4S/GhJDtdbbDHW3WUMXOCsuQMwow7vDreT+0HtdXCkvxFCgl/2SZmQNOXcaEoUQnk JlzhNg/HXDz9ZAl3htUaKQ6xMliTrS+Cz44WVycVhrbA98o5MeSwPlS+mzjfDUv2N/Bh i2ZmzOffpwgfx5KVoRgEYLK6eY2bvTsUUbu+uqlxdY28IOODOx99jj1Hb5AsGuObijsU 72qyJE8hTzkdm8bLkWpbVZc5U6Y6to4aQXG/7HnXkK2cFQVvvXfzGJHgg7/4gdxry7Ks rfK5vFuI2Mu9MJuRha0tZUh79capii6vjFRIP8jccFT2mTGpNP9M5JzpL5srjOytE2O1 zsiw== X-Forwarded-Encrypted: i=1; AJvYcCUsI1gkXfv3CHEWiRF0hs1M+cbY+eaOgf+vfe/niNUF6ZLpk2Zi3t2Dc4YiFUXb8ZViwDg/xXLLX34CipI=@vger.kernel.org X-Gm-Message-State: AOJu0YzX2aQ7skmngtgfauGNVG1j5g8HsJiCZ6gdkOCjlQ8oSR7pIWgb 0HDbpedbJQ1wSjQLOb0GKuEHWnJwTYIw/7cXRt9trU93OTdL1K9hjIF0d2mH8YzQoJE= X-Gm-Gg: ASbGnct23i8z8zmZRRuEEZ8Gf7cSmTD/NGk/OMAXTk2frRpeQbUQKy7mqrpNn0fOdhS 02cvjeCVEu1LdgLxDrqGk9NL8BBVJz1OnwcUiTt73dU/CyOG5QrZtABpHng0PkTYlKjMaIbSJ7+ rxEMd/bEN4qs6fRvAeR5h8b+5KolXN9iLDZJ7IOj6w8RblmgmCXTzgOyYvmitGkyPIXS0oN++yR amyX+pZhIRUV9BV9i9q7N2UBZZw13/5vgsYPxCJoI5pw8fvVf4M+jeiZkLgLCAT5EB4otzCWlSV Z1YiIwcXHX4OpwdiRbzFezemSuvTIIRxd7ZwsZkv6/LVDslJorrfZ7RpzSK6qtpciJlzu2orObK PS7mu8wU5XGVBpqZ0UYIWPcnH55xNXV3g X-Google-Smtp-Source: AGHT+IGVifY90ul/kd9o3o6inz9kogKyytkNR1Mkk0jMmIxV8Ntq/CDmQ5WF/k7Z2pC/kCZPojhuLA== X-Received: by 2002:a17:907:1c0a:b0:ae0:ca8e:5561 with SMTP id a640c23a62f3a-ae0ca8e5732mr22602266b.13.1750843398619; Wed, 25 Jun 2025 02:23:18 -0700 (PDT) Received: from otso.local (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0aaa0a854sm270277766b.68.2025.06.25.02.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:23:18 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:23:05 +0200 Subject: [PATCH 10/14] dt-bindings: mmc: sdhci-msm: document the SM7635 SDHCI Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-fp6-initial-v1-10-d9cd322eac1b@fairphone.com> References: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> In-Reply-To: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=849; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=9mNvIjwX0GVg9+8QJn8ze4jldqNBVe9LJDYJHk6E7+Y=; b=ffd4klj28huseDrq2t0Ois6nd1kBF/j9T3yy2ZWpgFwV8hBk7iSpc/UKSVR/3ZIG3wkyYCYpY +TzW/dweg55BSVxNB51nndNlAVdd6s43fdl8zY73JdwEi8CKF8/opnC X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the SDHCI Controller on the SM7635 Platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-msm.yaml index 2b2cbce2458b70b96b98c042109b10ead26e2291..bde69ee1554642b8c2ed74b1fa0= f68b421d7d64e 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -61,6 +61,7 @@ properties: - qcom,sm6350-sdhci - qcom,sm6375-sdhci - qcom,sm7150-sdhci + - qcom,sm7635-sdhci - qcom,sm8150-sdhci - qcom,sm8250-sdhci - qcom,sm8350-sdhci --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB09B2EF9DE for ; Wed, 25 Jun 2025 09:23:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843413; cv=none; b=sgAorLe0m64kOe2N6WoRy7WXLSGamSdFkylQ4lUD4JhdGOKtAFoXzeBdDVU8qArxpWc6JpKYBDpjB6ystmEznSBezaJF6wvb84ii+6p2xM6/vHQH5Ft0fq3Db/KSt6AdKC3gU415EXg+le/lO537Y3mr+gGWHCMztLTJ1h/SdKg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843413; c=relaxed/simple; bh=jj4FXpnaY2L8qRW5W5/06pfPaCeBVQY5CbMDnnBtNOA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xjcxmjrw1x2+U/8OL546DH/7bwPQfYhxUyHuMet0UArpkJfpxvIKgwlpzUMmCKdUQlzCkQSnF1yIAYC+qGRcEFogWjHDIyll1pgWj/93Yb8rc7QArHa6FhOhan7PILjCJ6wAZLaNbpJvhX7HP2hT3qgEJOuWq55VFNT90+W/xqU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=TYWShlci; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="TYWShlci" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-adb5cb6d8f1so981639566b.3 for ; Wed, 25 Jun 2025 02:23:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1750843400; x=1751448200; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PueVIxrY0Lhx5OoYalpVzj7TJ+cyHwt+DTi/ni2FBMg=; b=TYWShlci2W5Vwl3f0oDuA0g1jKsPVsnAaplQ6wJo0q1upNo7DmpauwIWLYQWJybV1e MP3HQsU4RR+e+fV2MeWLKo14TBHoNVcCqw6nypUZJ9Cd4OyvYuRjV6hg046cDcCoOTNJ Q/Leh3Sx7qGqljcXbzOmTAWIhkUAe0vkzORj58R3RuK0OoAMVJ+97djUq9NiiVtvnfa7 3Ecc8Em4E4DW7vERFkRl5Etwnovx12CB9z2pF3Q2JgoVTyuc9U50fcRBiS1rjFHk30F8 otXqmlPtDZ4HqfC5rupSp75N7Oc9Npz5fAeW16UBNxeWoIMv1lWfnm8j0A9hrWE1QtTw zfbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750843400; x=1751448200; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PueVIxrY0Lhx5OoYalpVzj7TJ+cyHwt+DTi/ni2FBMg=; b=L9gysiCxmnCwMFRA8ziS0ulIoKYzQXgy+2TIxdXdFkeFxa++c1SFUwfYjDB4m/ApiG As6YDvn6t4hnbonaOh6DH8LZyF+N6So06gu+sHRTKM9NZvfgL4OLbUctrhhQ6QmziKUH vhKo3ypY/d+djvdH+mmiKf6iWxXEM3XWu5ujoH2GodIq1NXGgoljr0A6G5s1vISUimOF HGTUFICEkKZS2PWV5c+nzI9PK7exKMF4zU5e3cZ3+VJw0Y/Uu0Cmwg36tIhCK7GTm7W1 P1j9ORb3sEVAFh9t4CzQ6ZLGfkLHkfFcbfqmHx996ePS0KoMgPqisW2+xiEzxEQYOSup xVpQ== X-Forwarded-Encrypted: i=1; AJvYcCXjecVWPWSeKGyBtzTKIUCUFgrVQaSRtjK9Zuc9dMrHcpeYQ40GPwIqpCq9bUDWeV8CXLF8/GQwL38+CXs=@vger.kernel.org X-Gm-Message-State: AOJu0YzunRBaq6ioAYfzQbnJEf7YZZCqllOe6QTsL1v8qC68muVEex3V AwkRvUtw5KiPah0QaMX4yAfxVaQJNb9FqGBxmr7a8IUAcE83aZt9tywpICS58gSVXkM= X-Gm-Gg: ASbGncvFlG3fhk87Nm2azfLbZsxHMuj/zUyc+k2jU3YTLqskGc0biW17MILrMvGMsO2 wttinNDM6e8LPEsz9MmWXAGvCOqKwBXRPPC9HugUXbh86JcvN02t+5pqMpzms5uFfjfR/c1fzBA ZJtyhz3FFpcoDynHGByvgVD7rSF9FV+wbGMxNEjDhsIg7igHOWZu7ss0zFsyVm1xnoNVTU1LnMz e8UwNjw8Tohnr14eqj9sQuHBUGJQItGtAD3FgUZngpwIce1wEsEA8SXujsdFSGYdxxIdB3CimKv lc5ZfbrZmbLjDOKQRUkBi2xmDIWROGEqP2Rbps28wZlzHIvfaLQzercUVfun/yYveMJzPr/5Trj 9WH1QFaCTXrK/J4kMmjF6PqA/KBEeZYto X-Google-Smtp-Source: AGHT+IFufR/i6s8bQEjNP+fAneYyap2WFk8eT5JzaxB2nRH9U0X06huQYHvxc1UIF4P5JtCVtPmAUw== X-Received: by 2002:a17:906:6a12:b0:ad8:8529:4f77 with SMTP id a640c23a62f3a-ae0bea790d5mr233626966b.38.1750843400340; Wed, 25 Jun 2025 02:23:20 -0700 (PDT) Received: from otso.local (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0aaa0a854sm270277766b.68.2025.06.25.02.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:23:19 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:23:06 +0200 Subject: [PATCH 11/14] dt-bindings: soc: qcom: qcom,pmic-glink: document SM7635 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-fp6-initial-v1-11-d9cd322eac1b@fairphone.com> References: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> In-Reply-To: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=920; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=jj4FXpnaY2L8qRW5W5/06pfPaCeBVQY5CbMDnnBtNOA=; b=QKOjYfcAGy5ZXnCmFyoCw5qgS3UKBJcYTNOrXIfiYw6DV7itFoCGZHGaadZiBNtQHiCfzjhFV Na8qSuO8OQ1DyaQjIxXMBvzPUgOVhYUCHVfApprHUM0Cz5utU9EaZ19 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the SM7635 compatible used to describe the pmic glink on this platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yam= l b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 4c9e78f29523e3d77aacb4299f64ab96f9b1a831..2b77021b278dd9dca604cf31e39= d9eca98f2aa7d 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -37,6 +37,7 @@ properties: - const: qcom,pmic-glink - items: - enum: + - qcom,sm7635-pmic-glink - qcom,sm8650-pmic-glink - qcom,sm8750-pmic-glink - qcom,x1e80100-pmic-glink --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19C932E0B4E for ; Wed, 25 Jun 2025 09:23:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843411; cv=none; b=eVq07/PiP+ocnSmybhcW7W4VsqL2tvSnoG/Y1g4tl3Ng5NiqicXeHK45TYCIsCWwES0OatMSLJDm2kpyqBE3jFOgUZXQNOL+WL+xpGA19JkCIF6CI62PDCnav9oCjORmj+cqdhQFwdSkDOZbMdANDB1Faap6ucjighx0M4iFTQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843411; c=relaxed/simple; bh=lSbZQMNS3mZ2Qhlodk3BCi0I8+R0Xssr2JSReaIqHv4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bTTPbm2wYvX/EPpW/RoBGYAxl+4OqYdjIpNvcd8GhWuXAub9rNnemPJnSZAjg4BPxbnykpoaAudETAfshLOhIGaC9hZWZMSToZaeiPp4Eld9bU/t/RGLxBLiVarLG86VCu3F7kch1EqtQiMKjLZctnEe+nZi/Wbg3+b1bMB/sSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=av86R8yv; arc=none smtp.client-ip=209.85.218.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="av86R8yv" Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-ae0a0cd709bso145690966b.0 for ; Wed, 25 Jun 2025 02:23:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1750843402; x=1751448202; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=nlprjCXzNhYiu8119hAJidFX3Tj0Nj5OLp/Tir9pgMI=; b=av86R8yvptx9KLSMo40dYEQvwzrpVi2kRrZRWjZll06aOluwXC4GhtmpEXJ8t7HOXe e7WRdcLfnfownve0Cx5nNRDtBrqHXjoitLVLGsfUoimndoT/jNzeuQKUa04WifDLHQci gXUjPHI0ti9vhSmsEf1ucIP/RhKEuEM86LzzteYzSSpi+KmvohRj/0ncyUA2CJIxO7hk +EyhA11QwI88xrt+YFKWvRxQarPKFf4olPe/dIldn2eyOZpuFmCqIYH182bMQGRuWDrR mXu5hyGsMy97k8aK1+cNjVMCUuSImAqxUzvkknlLYBr4v6IUjBmfioh42UvqjKzN7Tjn 4psw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750843402; x=1751448202; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nlprjCXzNhYiu8119hAJidFX3Tj0Nj5OLp/Tir9pgMI=; b=LFGthtUfFIuhtFuiVOe4ge7CDJ7oD9bj7CDhJKmoHhbfbKwmmXlBtDUvwZFnA20jvj r2kGob/uvRRtPveShkXjpi4/urKoj/aWg3UfegRTQMKSLFdJWP24ikFJj2MukdSdRmmP WRoYRH17LlrM1Gwxahaplg8SWF41Ajno2Vc8JlQLWtrBpTL2dUdf5Bk31gR3fY4unou3 0CDhuSiBC2mxs4qGwdhB3DV5TU8KN8jvgJcMi7BoFetn88vbc6wZRApr9mSnmuczE95O OBiNcGxCEg1jXTj/iQzMEENtJfbJGm4MwFZcpj3Gd0b7c3Gp5t7Xi+m7jNfhpuQ/lEZa uQuA== X-Forwarded-Encrypted: i=1; AJvYcCWv0M//b4Ro510SvWynUSAtfBYtJ+0QhW6Y3SL2IT5gpWqrZaXFQIU5avd4j3SCsZH906Mek/hBFZHVH8M=@vger.kernel.org X-Gm-Message-State: AOJu0YyBLOQ5vRa9mH5p8bkyV6MDzWkxW9GFHW0/WFBVYpO84oB3En+E vNuIg4lRR6H8SJR5f4Wv2Fz7wGtg2dQq7gGKDikDo8Qll+c3PoBhAQNG0UCEPabj/+A= X-Gm-Gg: ASbGncu0EB4FWcF0pv6tk60PwmCl3NBwLuvM8XSEYAuWtisDuia1e0Iw3ZkwfNfop/x 8tW+SX3E4ptaC6saHzqmSC/LehH9nroGmDIBvkJJigWwua9r7vJ0GQ8X0kMUpN90YYwmz0QpVG5 7ubMLSROM/0hjuj6WE4sXVyOJpjZrI/AgyITb/DSZIOMVO7Rv9T4ATfAqwvu5hrxpxKtL83RQNG xbeLXOXBlqvpnFcXE2UDPgRiUrjSPQWT4eF0liU4gjXsEMujvYTU4FRPDkl01uET2o6mqSILA21 06MdysiDL+v51YCbtQ1aFfYqdasIFyzMqwZXUaR0q7Sru8ZST99x9WF1TTltZ5jV3/Kd54MQlrY QGZORRQGrX8V+d0N4Tf0hwkTQDqcRdNvX X-Google-Smtp-Source: AGHT+IFMjj0Y3e5vRaQHZvxh7fHnevj/9XdkbDfc1cM5LOi08SBv192uCl1KLf+bmxAA3PmbEJU5qQ== X-Received: by 2002:a17:907:608e:b0:ad8:91e4:a92b with SMTP id a640c23a62f3a-ae0c08724d9mr179615566b.30.1750843401578; Wed, 25 Jun 2025 02:23:21 -0700 (PDT) Received: from otso.local (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0aaa0a854sm270277766b.68.2025.06.25.02.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:23:21 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:23:07 +0200 Subject: [PATCH 12/14] dt-bindings: arm: qcom: Add SM7635 and The Fairphone (Gen. 6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-fp6-initial-v1-12-d9cd322eac1b@fairphone.com> References: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> In-Reply-To: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=996; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=lSbZQMNS3mZ2Qhlodk3BCi0I8+R0Xssr2JSReaIqHv4=; b=yilPxLb4+1BOE1rCFDSywXfKUexVB1szD3ZMpoPtxgrPy4d6BGvUtVW9enhV9rLTafFlsiUdc CU20Ge/ADStBELDiO8FCnFwU5QmqC34bwJqV2yiobXy45sPeekuAPH0 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the SM7635-based The Fairphone (Gen. 6) smartphone. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 56f78f0f3803fedcb6422efd6adec3bbc81c2e03..bb89f81437d4ae12ac9fa447377= d6b48e3bfa581 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -93,6 +93,7 @@ description: | sm7150 sm7225 sm7325 + sm7635 sm8150 sm8250 sm8350 @@ -1056,6 +1057,11 @@ properties: - nothing,spacewar - const: qcom,sm7325 =20 + - items: + - enum: + - fairphone,fp6 + - const: qcom,sm7635 + - items: - enum: - microsoft,surface-duo --=20 2.50.0 From nobody Wed Oct 8 19:23:11 2025 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28E6129ACEE for ; Wed, 25 Jun 2025 09:23:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843416; cv=none; b=kM9SbSqUneu4ZtIu77EqI7cggLmLGVTwvBR1L6MggnCXQy7QxRB8ASHd8xsb9ARYTlxhPvsqlEMa4cyQHUA36GAKGI/43U4RiQAiulB/chCKLN79bj/6U0Iu+IefutDFGT5lVkCAuuNTkXjSNsjCCsAndKWmFEUUG0LgvpadYWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750843416; c=relaxed/simple; bh=d/c3UyUOA3x0NuGxzjRH0ALpLawY4s+fCPlQFFikjh8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cdrHJp8PP4NS26fpxmShOYJeewZ0S/+eCj/4Hq4p+esES1o7SvpozdIfqR50p3nYjDZksREZfOHQBlCGDG8zt0sRamhaTPxgkcr1LX42TlElamzPlwKdI/leRrYlBR7TdBXSB433i9d5GM/eM3F5VeAsX2A58BcPa3rwO6/9llo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=C04KKdZB; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="C04KKdZB" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-60c3aafae23so1532568a12.1 for ; Wed, 25 Jun 2025 02:23:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1750843403; x=1751448203; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=uBmD/PsoOz/asqSbux+4nW4cZM42fL85tfGtHYo7/qs=; b=C04KKdZBwC95QCLzl84JbvSt3Do5i3iz/X2OjYNyDg8CGQA+OTx7d5eAGiGBgtDrA1 nNT2Dkacodl9nWea0cuJ1oVIL/kaXsQBLG6iY4MeiD2jP8JHmL5uQAB9PCjavk+Vzed2 aymaI5Bh5kEPpPRqYsZ+eaUpBjyKQDKLBsf3wXx/mGXeu7QZyDiUlDdXZibEnn/kQWoD aAmT97EA3My88SM8ZsydkknvSs0W/7XLcWnC0tWoIqfAyuY+2OoYu+FBkWwZxs3FdoLL 3row+if/D0IG9/zb9CcxOUazfJo0NeErBc1L1dwLz295ab2e6CYewQbBXKG5TVNdsBCM tIHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750843403; x=1751448203; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uBmD/PsoOz/asqSbux+4nW4cZM42fL85tfGtHYo7/qs=; b=mrPbocNVnXpW9GkMIbCYXv1G3WxjMFXVpeGR19CWyMb7duggjDegVs5+UunYH4wL0Z mAwfvU8UyuVei1aRAo/ir4J1K9+H0PyDUez+Uuh1P76Z/ufRqtM6QSaNl6m8D8F6m6ze y6pXI9iMDu9MukbwNSplQFKjVduUXde68/50s+OvpQoTA+YdyVOMA8iAj5pWx05scWnG 6WMfJLECL7XLx8WtAE7JSuYa3Q7uDAFPXswSql05gxm10QBYiZlEjUFxThPnHVFugxe+ Fm3iinbjlsYeVTslJyAhVDQf3JsSgMdqhajy9gX/b3nVpmZlsl9GMGbcTl7IXrKt6PZx Lqfw== X-Forwarded-Encrypted: i=1; AJvYcCVAXORj79ORb+yzbZH0a6TDlwKZC/rH00pqEkooabsRndcOgp3nPLon7xIYHpCkVmTZpB4Bv3+gCmG9V6U=@vger.kernel.org X-Gm-Message-State: AOJu0Ywd0jjcRwufY4L09N03cMwy+ZPnO+gAnIiVUH/wbXlqeDzJaQS3 UY9e2iP+JdtZto/OdZc71C4b9+W4Vxs+duSIcMRWzuByKSwQmlURW8Z/bdUT3w9Prfo= X-Gm-Gg: ASbGncs4zKjk6OsGUuFPUIfo121LtR+3ZCRlayUsJN9pK1ncRvznrxNbDCyyHphX3MN YNqz/WamN9/EDvEvmLTD/3PJFkIBAaf4+MsLaegXqYW02129QiLHuuzBLPU6yyXBEXSIrNUJLGj 3iTdbLK7LzfPtZldMkZPEV1tpQ8qJN5gT768RsrOe2Yd+vE3qwGOBWEhpn8lflwzWf/KRKn6ydB UqbFjU3NrG8zspcfGelPa1QFLp2xL1SDlTHd0FEdOYFRqrrJ3jhzYrREO8SK8pJ5Z1gznxitrZG SRq9+cvFEYq8NT62ZncY/QPfylla+GLPeL1hhugLDCl3XF0DxpVJfJiC4dMYsZ0PRzBamOLcw/c ktyqbIBPXklo0JezeJbYZcKmQX0wjbHyiYhL2jQgmzQw= X-Google-Smtp-Source: AGHT+IGuFm/leCcGVK7r6HezNtgvL1TWgJrtV/rVAk6j5FFH1iK3Y48fnUbAhUh3SFu/yXE8ngEA1A== X-Received: by 2002:a17:907:d94:b0:ade:31bf:611c with SMTP id a640c23a62f3a-ae0c069550amr178885166b.9.1750843402807; Wed, 25 Jun 2025 02:23:22 -0700 (PDT) Received: from otso.local (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0aaa0a854sm270277766b.68.2025.06.25.02.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:23:22 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:23:08 +0200 Subject: [PATCH 13/14] arm64: dts: qcom: Add initial SM7635 dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-fp6-initial-v1-13-d9cd322eac1b@fairphone.com> References: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> In-Reply-To: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=70138; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=d/c3UyUOA3x0NuGxzjRH0ALpLawY4s+fCPlQFFikjh8=; b=/1bACx/QwKk1F451Nv7aAHXbW8B9lqEsqPdFijsjplERTO6KBQS2pN9XG05GeTvTFbXlMKiYW pOU+y7uavxpDduww62iQd71YuOgGWkKzlZbxn2AhlwVNKB6OAbPsWRk X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a devicetree description for the Snapdragon 7s Gen 3 SoC. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm7635.dtsi | 2806 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 2806 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7635.dtsi b/arch/arm64/boot/dts/qco= m/sm7635.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e6a2943c372bfcf05e06c98ee85= 2afaccb95b3db --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7635.dtsi @@ -0,0 +1,2806 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <76800000>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32764>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x0>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x100>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x200>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x300>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x400>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_4>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <264>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + #cooling-cells =3D <2>; + + l2_4: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x500>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_5>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <264>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + #cooling-cells =3D <2>; + + l2_5: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x600>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_6>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <264>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + #cooling-cells =3D <2>; + + l2_6: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x700>; + + clocks =3D <&cpufreq_hw 2>; + + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_7>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <287>; + + qcom,freq-domain =3D <&cpufreq_hw 2>; + + #cooling-cells =3D <2>; + + l2_7: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + silver_cpu_sleep_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "pc"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <250>; + exit-latency-us =3D <700>; + min-residency-us =3D <5200>; + local-timer-stop; + }; + + silver_cpu_sleep_1: cpu-sleep-0-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <550>; + exit-latency-us =3D <750>; + min-residency-us =3D <6700>; + local-timer-stop; + }; + + gold_cpu_sleep_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <400>; + exit-latency-us =3D <900>; + min-residency-us =3D <5511>; + local-timer-stop; + }; + + gold_cpu_sleep_1: cpu-sleep-1-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <600>; + exit-latency-us =3D <1300>; + min-residency-us =3D <8136>; + local-timer-stop; + }; + + gold_plus_cpu_sleep_0: cpu-sleep-2-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-plus-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <600>; + exit-latency-us =3D <1500>; + min-residency-us =3D <8551>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <750>; + exit-latency-us =3D <2350>; + min-residency-us =3D <9144>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41003344>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-sm7635", "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x19000>; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,sm7635-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,sm7635-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@0 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0 0 0 0>; + }; + + pmu-a520 { + compatible =3D "arm,cortex-a520-pmu"; + interrupts =3D ; + }; + + pmu-a720 { + compatible =3D "arm,cortex-a720-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_plus_cpu_sleep_0>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_0>, <&cluster_sleep_1>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp-region@80000000 { + reg =3D <0x0 0x80000000 0x0 0xe00000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@81800000 { + reg =3D <0x0 0x81800000 0x0 0x40000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@81840000 { + reg =3D <0x0 0x81840000 0x0 0x1c0000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog-region@81a00000 { + reg =3D <0x0 0x81a00000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump-region@81a40000 { + reg =3D <0x0 0x81a40000 0x0 0x1c0000>; + no-map; + }; + + aop_image_mem: aop-image-region@81c00000 { + reg =3D <0x0 0x81c00000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config-region@81c80000 { + reg =3D <0x0 0x81c80000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump-region@81ca0000 { + reg =3D <0x0 0x81ca0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log-region@81ce0000 { + reg =3D <0x0 0x81ce0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log-region@81ce4000 { + reg =3D <0x0 0x81ce4000 0x0 0x10000>; + no-map; + }; + + chipinfo_mem: chipinfo-region@81cf4000 { + reg =3D <0x0 0x81cf4000 0x0 0x1000>; + no-map; + }; + + secdata_apss_mem: secdata-apss-region@81cff000 { + reg =3D <0x0 0x81cff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem-region@81d00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x81d00000 0x0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg =3D <0x0 0x81f00000 0x0 0x20000>; + no-map; + }; + + pvm_fw_mem: pvm-fw-region@824a0000 { + reg =3D <0x0 0x824a0000 0x0 0x100000>; + no-map; + }; + + hyp_mem_database_mem: hyp-mem-database-region@825a0000 { + reg =3D <0x0 0x825a0000 0x0 0x60000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg =3D <0x0 0x82600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg =3D <0x0 0x82700000 0x0 0x100000>; + no-map; + }; + + qdss_apps_mem: qdss-apps-region@82800000 { + reg =3D <0x0 0x82800000 0x0 0x2000000>; + reusable; + }; + + mpss_mem: mpss-region@8ac00000 { + reg =3D <0x0 0x8ac00000 0x0 0xe600000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 { + reg =3D <0x0 0x99200000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 { + reg =3D <0x0 0x99280000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@99300000 { + reg =3D <0x0 0x99300000 0x0 0x2800000>; + no-map; + }; + + wpss_mem: wpss-region@9bb00000 { + reg =3D <0x0 0x9bb00000 0x0 0x1900000>; + no-map; + }; + + video_mem: video-region@9d400000 { + reg =3D <0x0 0x9d400000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9db00000 { + reg =3D <0x0 0x9db00000 0x0 0xf00000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 { + reg =3D <0x0 0x9ea00000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9ea80000 { + reg =3D <0x0 0x9ea80000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9ea90000 { + reg =3D <0x0 0x9ea90000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@9ea9a000 { + reg =3D <0x0 0x9ea9a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera-region@9eb00000 { + reg =3D <0x0 0x9eb00000 0x0 0x800000>; + no-map; + }; + + wlan_msa_mem: wlan-msa-region@a6400000 { + reg =3D <0x0 0xa6400000 0x0 0xc00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@e0600000 { + reg =3D <0x0 0xe0600000 0x0 0x400000>; + no-map; + }; + + rmtfs_mem: rmtfs@e1f00000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0xe1f00000 0x0 0x600000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D ; + }; + + qtee_mem: qtee-region@e8900000 { + reg =3D <0x0 0xe8900000 0x0 0x500000>; + no-map; + }; + + tags_mem: tags-region@e8e00000 { + reg =3D <0x0 0xe8e00000 0x0 0x700000>; + no-map; + }; + + trusted_apps_mem: trusted-apps-region@e9500000 { + reg =3D <0x0 0xe9500000 0x0 0x1200000>; + no-map; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <94>, <432>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + smp2p_ipa_out: ipa-ap-to-modem { + qcom,entry-name =3D "ipa"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_ipa_in: ipa-modem-to-ap { + qcom,entry-name =3D "ipa"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wpss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <617>, <616>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <13>; + + smp2p_wpss_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_wpss_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + smp2p_wlan_out: wlan-ap-to-wpss { + qcom,entry-name =3D "wlan"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_wlan_in: wlan-wpss-to-ap { + qcom,entry-name =3D "wlan"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0 0 0 0 0x10 0>; + ranges =3D <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,sm7635-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f4200>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, /* pcie_0_pipe_clk */ + <0>, /* pcie_1_pipe_clk */ + <0>, /* ufs_phy_rx_symbol_0_clk */ + <0>, /* ufs_phy_rx_symbol_1_clk */ + <0>, /* ufs_phy_tx_symbol_0_clk */ + <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ + protected-clocks =3D , , + , , + , , + , , + , , + , ; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + ipcc: mailbox@405000 { + compatible =3D "qcom,sm7635-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x00405000 0x0 0x1000>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + + #mbox-cells =3D <2>; + }; + + gpi_dma1: dma-controller@800000 { + compatible =3D "qcom,sm7635-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00800000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x3f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x36 0x0>; + dma-coherent; + + status =3D "disabled"; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core"; + + iommus =3D <&apps_smmu 0x23 0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + i2c7: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c7_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart11: serial@890000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart11_default>, <&qup_uart11_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + gpi_dma0: dma-controller@a00000 { + compatible =3D "qcom,sm7635-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x3e>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x576 0x0>; + dma-coherent; + + status =3D "disabled"; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core"; + + iommus =3D <&apps_smmu 0x563 0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + spi0: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c1: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart5: serial@a94000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart5_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + rng: rng@10c3000 { + compatible =3D "qcom,sm7635-trng", "qcom,trng"; + reg =3D <0x0 0x010c3000 0x0 0x1000>; + }; + + mmss_noc: interconnect@1400000 { + compatible =3D "qcom,sm7635-mmss-noc"; + reg =3D <0x0 0x01400000 0x0 0xdb800>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,sm7635-cnoc-main"; + reg =3D <0x0 0x01500000 0x0 0x14400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + cnoc_cfg: interconnect@1600000 { + compatible =3D "qcom,sm7635-cnoc-cfg"; + reg =3D <0x0 0x01600000 0x0 0x6e00>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,sm7635-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x40000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16c0000 { + compatible =3D "qcom,sm7635-pcie-anoc"; + reg =3D <0x0 0x016c0000 0x0 0x12400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,sm7635-aggre1-noc"; + reg =3D <0x0 0x016e0000 0x0 0x16400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,sm7635-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1f400>; + #interconnect-cells =3D <2>; + clocks =3D <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells =3D <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible =3D "qcom,sm7635-tcsr", "syscon"; + reg =3D <0x0 0x01fc0000 0x0 0xa0000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible =3D "qcom,sm7635-adsp-pas"; + reg =3D <0x0 0x03000000 0x0 0x10000>; + + interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names =3D "lcx", + "lmx"; + + interconnects =3D <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region =3D <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "lpass"; + qcom,remote-pid =3D <2>; + }; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible =3D "qcom,sm7635-lpass-ag-noc"; + reg =3D <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sm7635-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sm7635-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names =3D "hlos", + "bus", + "iface", + "ahb"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible =3D "qcom,sm7635-mpss-pas"; + reg =3D <0x0 0x04080000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names =3D "cx", + "mss"; + + interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region =3D <&mpss_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_modem_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "mpss"; + qcom,remote-pid =3D <1>; + }; + }; + + sdhc_2: mmc@8804000 { + compatible =3D "qcom,sm7635-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x08804000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "core", + "xo"; + + interconnects =3D <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "sdhc-ddr", + "cpu-sdhc"; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + + iommus =3D <&apps_smmu 0x540 0>; + + bus-width =3D <4>; + + qcom,dll-config =3D <0x0007442c>; + qcom,ddr-config =3D <0x80040868>; + + dma-coherent; + + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + usb_1_hsphy: phy@88e3000 { + compatible =3D "qcom,sm7635-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg =3D <0x0 0x088e3000 0x0 0x154>; + #phy-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status =3D "disabled"; + }; + + remoteproc_wpss: remoteproc@8a00000 { + compatible =3D "qcom,sm7635-wpss-pas"; + reg =3D <0x0 0x08a00000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "cx", + "mx"; + + memory-region =3D <&wpss_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_wpss_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "wpss"; + qcom,remote-pid =3D <13>; + }; + }; + + usb_1: usb@a600000 { + compatible =3D "qcom,sm7635-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a600000 0x0 0x10000>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <133333333>; + + interrupts-extended =3D <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + iommus =3D <&apps_smmu 0x40 0x0>; + power-domains =3D <&gcc USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + phys =3D <&usb_1_hsphy>; + phy-names =3D "usb2-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,has-lpm-erratum; + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,parkmode-disable-ss-quirk; + tx-fifo-resize; + dma-coherent; + usb-role-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + }; + }; + + videocc: clock-controller@aaf0000 { + compatible =3D "qcom,sm7635-videocc"; + reg =3D <0x0 0x0aaf0000 0x0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@adb0000 { + compatible =3D "qcom,sm7635-camcc"; + reg =3D <0x0 0x0adb0000 0x0 0x40000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,sm7635-dispcc"; + reg =3D <0x0 0x0af00000 0x0 0x20000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, /* dsi0_phy_pll_out_byteclk */ + <0>, /* dsi0_phy_pll_out_dsiclk */ + <0>, /* dp0_phy_pll_link_clk */ + <0>; /* dp0_phy_pll_vco_div_clk */ + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,sm7635-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; + interrupt-parent =3D <&intc>; + + qcom,pdc-ranges =3D <0 480 40>, <40 140 11>, <51 527 47>, + <98 609 31>, <129 63 1>, <130 716 12>, + <142 251 5>; + + #interrupt-cells =3D <2>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c228000 { + compatible =3D "qcom,sm7635-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c228000 0x0 0x1ff>, /* TM */ + <0x0 0x0c222000 0x0 0x1ff>; /* SROT */ + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <15>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible =3D "qcom,sm7635-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c229000 0x0 0x1ff>, /* TM */ + <0x0 0x0c223000 0x0 0x1ff>; /* SROT */ + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <14>; + + #thermal-sensor-cells =3D <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,sm7635-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + + interrupt-parent =3D <&ipcc>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_= QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + sram@c3f0000 { + compatible =3D "qcom,rpmh-stats"; + reg =3D <0x0 0x0c3f0000 0x0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x10000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + + qcom,ee =3D <0>; + qcom,channel =3D <0>; + qcom,bus-id =3D <0>; + + interrupt-controller; + #interrupt-cells =3D <4>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,sm7635-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0x300000>; + + interrupts =3D ; + + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-ranges =3D <&tlmm 0 0 168>; + + wakeup-parent =3D <&pdc>; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio4", "gpio5"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio15", "gpio16"; + function =3D "qup0_se3"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio32", "gpio33"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins =3D "gpio3"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio0", "gpio1", "gpio2"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins =3D "gpio25", "gpio26"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins =3D "gpio50", "gpio51"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart11_cts_rts: qup-uart11-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio48", "gpio49"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "gpio62"; + function =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio61"; + function =3D "sdc2_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio58", "gpio57", "gpio35", "gpio34"; + function =3D "sdc2_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "gpio62"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio61"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio58", "gpio57", "gpio35", "gpio34"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,sm7635-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17100000 0x0 0x10000>, /* GICD */ + <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #redistributor-regions =3D <1>; + redistributor-stride =3D <0 0x40000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: msi-controller@17140000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17140000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + timer@17420000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17420000 0x0 0x1000>; + + ranges =3D <0 0 0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17421000 { + reg =3D <0x17421000 0x1000>, + <0x17422000 0x1000>; + + interrupts =3D , + ; + + frame-number =3D <0>; + }; + + frame@17423000 { + reg =3D <0x17423000 0x1000>; + + interrupts =3D ; + + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@17425000 { + reg =3D <0x17425000 0x1000>; + + interrupts =3D ; + + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@17427000 { + reg =3D <0x17427000 0x1000>; + + interrupts =3D ; + + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@17429000 { + reg =3D <0x17429000 0x1000>; + + interrupts =3D ; + + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@1742b000 { + reg =3D <0x1742b000 0x1000>; + + interrupts =3D ; + + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@1742d000 { + reg =3D <0x1742d000 0x1000>; + + interrupts =3D ; + + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + + interrupts =3D , + , + ; + + power-domains =3D <&cluster_pd>; + + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + + label =3D "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,sm7635-rpmh-clk"; + + clocks =3D <&xo_board>; + clock-names =3D "xo"; + + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,sm7635-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level =3D ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible =3D "qcom,sm7635-cpufreq-epss", "qcom,cpufreq-epss"; + reg =3D <0x0 0x17d91000 0x0 0x1000>, + <0x0 0x17d92000 0x0 0x1000>, + <0x0 0x17d93000 0x0 0x1000>; + reg-names =3D "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts =3D , + , + ; + interrupt-names =3D "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + + gem_noc: interconnect@24100000 { + compatible =3D "qcom,sm7635-gem-noc"; + reg =3D <0x0 0x24100000 0x0 0xff080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nsp_noc: interconnect@320c0000 { + compatible =3D "qcom,sm7635-nsp-noc"; + reg =3D <0x0 0x320c0000 0x0 0xe080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible =3D "qcom,sm7635-cdsp-pas"; + reg =3D <0x0 0x32300000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "cx", + "mx"; + + interconnects =3D <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region =3D <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "cdsp"; + qcom,remote-pid =3D <5>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + aoss0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + aoss0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + cpuss0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + cpuss0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + cpuss1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + cpuss1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu4-left-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 3>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-right-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 4>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-left-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 5>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-right-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 6>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-left-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 7>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-right-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 8>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-left-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 9>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-right-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 10>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu0-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + thermal-sensors =3D <&tsens0 12>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu1-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 13>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu2-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 14>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + aoss1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + aoss1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 1>; + + trips { + nsphvx0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + nsphvx0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 2>; + + trips { + nsphmx1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + nsphmx1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 3>; + + trips { + nsphmx0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + nsphmx0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 4>; + + trips { + gpu0_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + gpuss0-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 5>; + + trips { + gpu1_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + gpuss1-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors =3D <&tsens1 7>; + + trips { + video-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + video-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 8>; + + trips { + ddr-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + ddr-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors =3D <&tsens1 9>; + + trips { + camera0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + camera0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 10>; + + trips { + modem0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 11>; + + trips { + modem1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 12>; + + trips { + modem2-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem2-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 13>; + + trips { + modem3-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem3-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0aaa0a854sm270277766b.68.2025.06.25.02.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:23:23 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:23:09 +0200 Subject: [PATCH 14/14] arm64: dts: qcom: Add The Fairphone (Gen. 6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-fp6-initial-v1-14-d9cd322eac1b@fairphone.com> References: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> In-Reply-To: <20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750843387; l=22034; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=b1L8T64hp6GAFH9idBAVVMlsB+uDom6OB0svksRrRtA=; b=6wEHmsKRLfFnwKu02OdfcHJvVK9QXGRgOWwPAr7b1FFxeIsI8uFOclBVLITGPRc51pgfVDOzJ HqrQ7RwE1EyAdixR9FhzQC4qs0mDjec7XrfgjGtWWzdQI/KfWMuZXJN X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based on the SM7635 SoC. Supported functionality as of this initial submission: * Debug UART * Regulators (PM7550, PM8550VS, PMR735B, PM8008) * Remoteprocs (ADSP, CDSP, MPSS, WPSS) * Power Button, Volume Keys, Switch * Display (using simple-framebuffer) * PMIC-GLINK (Charger, Fuel gauge, USB-C mode switching) * Camera flash/torch LED * SD card * USB Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm7635-fairphone-fp6.dts | 837 ++++++++++++++++++= ++++ 2 files changed, 838 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 669b888b27a1daa93ac15f47e8b9a302bb0922c2..c06c93a92fb9ce24aed9dee51c0= 907ab22903ac5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -266,6 +266,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm7125-xiaomi-curtana.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm7125-xiaomi-joyeuse.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm7225-fairphone-fp4.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm7325-nothing-spacewar.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sm7635-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8150-microsoft-surface-duo.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8150-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm7635-fairphone-fp6.dts b/arch/arm64= /boot/dts/qcom/sm7635-fairphone-fp6.dts new file mode 100644 index 0000000000000000000000000000000000000000..d687e4e75f21afbe317093cd3b4= 8030354411592 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7635-fairphone-fp6.dts @@ -0,0 +1,837 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +/dts-v1/; + +#define PMIV0104_SID 7 + +#include +#include +#include +#include "sm7635.dtsi" +#include "pm8550vs.dtsi" +#include "pmiv0104.dtsi" /* PMIV0108 */ +#include "pmk8550.dtsi" /* PMK7635 */ +#include "pmr735b.dtsi" +#include "pmxr2230.dtsi" /* PM7550 */ + +/ { + model =3D "The Fairphone (Gen. 6)"; + compatible =3D "fairphone,fp6", "qcom,sm7635"; + chassis-type =3D "handset"; + + aliases { + serial0 =3D &uart5; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer0: framebuffer@e3940000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0xe3940000 0x0 (2484 * 1116 * 4)>; + width =3D <1116>; + height =3D <2484>; + stride =3D <(1116 * 4)>; + format =3D "a8r8g8b8"; + panel =3D <&panel>; + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_default>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + gpios =3D <&pmxr2230_gpios 6 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + switch { + label =3D "Switch"; + gpios =3D <&tlmm 107 GPIO_ACTIVE_HIGH>; + linux,input-type =3D ; + linux,code =3D ; + }; + }; + + /* Dummy panel for simple-framebuffer dimension info */ + panel: panel { + compatible =3D "boe,bj631jhm-t71-d900"; + width-mm =3D <65>; + height-mm =3D <146>; + }; + + pmic-glink { + compatible =3D "qcom,sm7635-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 131 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + }; + }; + }; + + vreg_ff_afvdd_2p8: regulator-ff-afvdd-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "ff_afvdd_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 93 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_bob>; + }; + + vreg_uw_afvdd_2p8: regulator-uw-afvdd-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "uw_afvdd_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_bob>; + }; + + vreg_uw_dvdd: regulator-uw-dvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "uw_dvdd"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_s1b>; + }; + + vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "ois_avdd0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_bob>; + }; + + vreg_ois_vdd: regulator-ois-vdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "ois_vdd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + }; + + vreg_oled_dvdd_1p2: regulator-oled-dvdd-1p2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "oled_dvdd_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + + gpio =3D <&tlmm 54 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_s2b>; + + regulator-boot-on; + }; + + vreg_s1j: regulator-pm3001a-s1j { + compatible =3D "regulator-fixed"; + regulator-name =3D "pm3001a_s1j"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <2200000>; + startup-delay-us =3D <1000>; + + gpio =3D <&pmr735b_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + + pinctrl-0 =3D <&s1j_enable_default>; + pinctrl-names =3D "default"; + }; + + vreg_vtof_ldo_3p3: regulator-vtof-ldo-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vtof_ldo_3p3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + /* + * ABL is powering down display and controller if this node is + * not named exactly "splash_region". + */ + splash_region@e3940000 { + reg =3D <0x0 0xe3940000 0x0 0x2b00000>; + no-map; + }; + }; + + thermal-zones { + pm8008-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pm8008>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s1b>; + vdd-l2-l3-supply =3D <&vreg_s3b>; + vdd-l4-l5-supply =3D <&vreg_s2b>; + vdd-l6-supply =3D <&vreg_s2b>; + vdd-l7-supply =3D <&vreg_s1b>; + vdd-l8-supply =3D <&vreg_s1b>; + vdd-l9-l10-supply =3D <&vreg_s1b>; + vdd-l11-supply =3D <&vreg_s1b>; + vdd-l12-l14-supply =3D <&vreg_bob>; + vdd-l13-l16-supply =3D <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply =3D <&vreg_bob>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "b"; + + vreg_s1b: smps1 { + regulator-name =3D "vreg_s1b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2080000>; + regulator-initial-mode =3D ; + }; + + vreg_s2b: smps2 { + regulator-name =3D "vreg_s2b"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1408000>; + regulator-initial-mode =3D ; + }; + + vreg_s3b: smps3 { + regulator-name =3D "vreg_s3b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <1040000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b: ldo2 { + regulator-name =3D "vreg_l2b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l3b: ldo3 { + regulator-name =3D "vreg_l3b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l4b: ldo4 { + regulator-name =3D "vreg_l4b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b: ldo5 { + regulator-name =3D "vreg_l5b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b: ldo7 { + regulator-name =3D "vreg_l7b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b: ldo8 { + regulator-name =3D "vreg_l8b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b: ldo9 { + regulator-name =3D "vreg_l9b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b: ldo10 { + regulator-name =3D "vreg_l10b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b: ldo11 { + regulator-name =3D "vreg_l11b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b: ldo12 { + regulator-name =3D "vreg_l12b"; + /* + * Skip voltage voting for UFS VCC. + */ + regulator-initial-mode =3D ; + }; + + vreg_l13b: ldo13 { + regulator-name =3D "vreg_l13b"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b: ldo14 { + regulator-name =3D "vreg_l14b"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b: ldo15 { + regulator-name =3D "vreg_l15b"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_l16b: ldo16 { + regulator-name =3D "vreg_l16b"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b: ldo17 { + regulator-name =3D "vreg_l17b"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b: ldo18 { + regulator-name =3D "vreg_l18b"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l19b: ldo19 { + regulator-name =3D "vreg_l19b"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + }; + + vreg_l20b: ldo20 { + regulator-name =3D "vreg_l20b"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l21b: ldo21 { + regulator-name =3D "vreg_l21b"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l22b: ldo22 { + regulator-name =3D "vreg_l22b"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + }; + + vreg_l23b: ldo23 { + regulator-name =3D "vreg_l23b"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_bob: bob { + regulator-name =3D "vreg_bob"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3b>; + vdd-l3-supply =3D <&vreg_s3b>; + + qcom,pmic-id =3D "c"; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <650000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmr735b-rpmh-regulators"; + + vdd-l1-l2-supply=3D <&vreg_s3b>; + vdd-l3-supply=3D <&vreg_s3b>; + vdd-l4-supply=3D <&vreg_s1b>; + vdd-l5-supply=3D <&vreg_s2b>; + vdd-l6-supply=3D <&vreg_s2b>; + vdd-l7-l8-supply=3D <&vreg_s2b>; + vdd-l9-supply=3D <&vreg_s3b>; + vdd-l10-supply=3D <&vreg_s1b>; + vdd-l11-supply=3D <&vreg_s3b>; + vdd-l12-supply=3D <&vreg_s3b>; + + qcom,pmic-id =3D "f"; + + vreg_l1f: ldo1 { + regulator-name =3D "vreg_l1f"; + regulator-min-microvolt =3D <852000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f: ldo2 { + regulator-name =3D "vreg_l2f"; + regulator-min-microvolt =3D <751000>; + regulator-max-microvolt =3D <824000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f: ldo3 { + regulator-name =3D "vreg_l3f"; + regulator-min-microvolt =3D <650000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f: ldo4 { + regulator-name =3D "vreg_l4f"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + }; + + vreg_l5f: ldo5 { + regulator-name =3D "vreg_l5f"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + + vreg_l6f: ldo6 { + regulator-name =3D "vreg_l6f"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l7f: ldo7 { + regulator-name =3D "vreg_l7f"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D ; + }; + + vreg_l8f: ldo8 { + regulator-name =3D "vreg_l8f"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + + vreg_l9f: ldo9 { + regulator-name =3D "vreg_l9f"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + }; + + vreg_l10f: ldo10 { + regulator-name =3D "vreg_l10f"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11f: ldo11 { + regulator-name =3D "vreg_l11f"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <864000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&dispcc { + /* Disable for now so simple-framebuffer continues working */ + status =3D "disabled"; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&i2c1 { + /* Samsung NFC @ 0x27 */ + + status =3D "okay"; +}; + +&i2c3 { + /* AW88261FCR amplifier (top) @ 0x34 */ + /* AW88261FCR amplifier (bottom) @ 0x35 */ + + status =3D "okay"; +}; + +&i2c7 { + status =3D "okay"; + + pm8008: pmic@8 { + compatible =3D "qcom,pm8008"; + reg =3D <0x8>; + + interrupts-extended =3D <&tlmm 125 IRQ_TYPE_EDGE_RISING>; + reset-gpios =3D <&pmr735b_gpios 3 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply =3D <&vreg_s2b>; + vdd-l3-l4-supply =3D <&vreg_bob>; + vdd-l5-supply =3D <&vreg_bob>; + vdd-l6-supply =3D <&vreg_s1b>; + vdd-l7-supply =3D <&vreg_bob>; + + pinctrl-0 =3D <&pm8008_int_default>, <&pm8008_reset_n_default>; + pinctrl-names =3D "default"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + #thermal-sensor-cells =3D <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name =3D "vreg_l1p"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name =3D "vreg_l2p"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1144000>; + }; + + vreg_l3p: ldo3 { + regulator-name =3D "vreg_l3p"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3000000>; + }; + + vreg_l4p: ldo4 { + regulator-name =3D "vreg_l4p"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2900000>; + }; + + vreg_l5p: ldo5 { + regulator-name =3D "vreg_l5p"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <2900000>; + }; + + vreg_l6p: ldo6 { + regulator-name =3D "vreg_l6p"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <1896000>; + }; + + vreg_l7p: ldo7 { + regulator-name =3D "vreg_l7p"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3400000>; + }; + }; + }; + + /* VL53L3 ToF @ 0x29 */ + /* AW86938FCR vibrator @ 0x5a */ +}; + +&pm8550vs_d { + status =3D "disabled"; +}; + +&pm8550vs_e { + status =3D "disabled"; +}; + +&pm8550vs_g { + status =3D "disabled"; +}; + +&pmiv0104_eusb2_repeater { + vdd18-supply =3D <&vreg_l7b>; + vdd3-supply =3D <&vreg_l17b>; + + qcom,tune-res-fsdif =3D /bits/ 8 <0x5>; + qcom,tune-usb2-amplitude =3D /bits/ 8 <0x8>; + qcom,tune-usb2-disc-thres =3D /bits/ 8 <0x7>; + qcom,tune-usb2-preem =3D /bits/ 8 <0x6>; +}; + +&pmr735b_gpios { + pm8008_reset_n_default: pm8008-reset-n-default-state { + pins =3D "gpio3"; + function =3D PMIC_GPIO_FUNC_NORMAL; + bias-pull-down; + }; + + s1j_enable_default: s1j-enable-default-state { + pins =3D "gpio1"; + function =3D PMIC_GPIO_FUNC_NORMAL; + power-source =3D <0>; + bias-disable; + output-low; + }; +}; + +&pmxr2230_gpios { + volume_up_default: volume-up-default-state { + pins =3D "gpio6"; + function =3D PMIC_GPIO_FUNC_NORMAL; + power-source =3D <1>; + bias-pull-up; + }; +}; + +&pmxr2230_flash { + status =3D "okay"; + + led-0 { + function =3D LED_FUNCTION_FLASH; + color =3D ; + led-sources =3D <1>, <4>; + led-max-microamp =3D <350000>; + flash-max-microamp =3D <1500000>; + flash-max-timeout-us =3D <400000>; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm7635/fairphone/fp6/adsp.mbn", + "qcom/sm7635/fairphone/fp6/adsp_dtb.mbn"; + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/sm7635/fairphone/fp6/cdsp.mbn", + "qcom/sm7635/fairphone/fp6/cdsp_dtb.mbn"; + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/sm7635/fairphone/fp6/modem.mbn"; + status =3D "okay"; +}; + +&remoteproc_wpss { + firmware-name =3D "qcom/sm7635/fairphone/fp6/wpss.mbn"; + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 65 GPIO_ACTIVE_HIGH>; + + vmmc-supply =3D <&vreg_l13b>; + vqmmc-supply =3D <&vreg_l23b>; + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&spi0 { + /* Eswin EPH8621 touchscreen @ 0 */ +}; + +&tlmm { + /* + * 8-11: Fingerprint SPI + * 13: NC + * 63-64: WLAN UART + */ + gpio-reserved-ranges =3D <8 4>, <13 1>, <63 2>; + + pm8008_int_default: pm8008-int-default-state { + pins =3D "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins =3D "gpio65"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; +}; + +&uart5 { + status =3D "okay"; +}; + +&usb_1 { + dr_mode =3D "otg"; + + /* USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + + status =3D "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l2b>; + vdda12-supply =3D <&vreg_l4b>; + + phys =3D <&pmiv0104_eusb2_repeater>; + + status =3D "okay"; +}; --=20 2.50.0