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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0b887ab4csm154937366b.129.2025.06.25.02.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 02:12:37 -0700 (PDT) From: Luca Weiss Date: Wed, 25 Jun 2025 11:12:27 +0200 Subject: [PATCH 09/10] dt-bindings: clock: qcom: document the SM7635 Video Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-sm7635-clocks-v1-9-ca3120e3a80e@fairphone.com> References: <20250625-sm7635-clocks-v1-0-ca3120e3a80e@fairphone.com> In-Reply-To: <20250625-sm7635-clocks-v1-0-ca3120e3a80e@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750842748; l=3535; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=Y9F/e6dicZGN3H4g41Qmi3nJ59/DcdHmY62nX1l3Gag=; b=AMHHXFNnJ6Ll+3mffP0MiXjndN5s6haTHL7MeIv69HRFSzP/4lEvoQUN4OZvjidrFyajoGU90 l/QBKmOSX+cA7K9MvCsHndDtFPDUWu3Ol4jSXQ1NbtaxhwH83+Lwp8P X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add bindings documentation for the SM7635 Video Clock Controller. Signed-off-by: Luca Weiss --- .../bindings/clock/qcom,sm7635-videocc.yaml | 53 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,sm7635-videocc.h | 36 +++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7635-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sm7635-videocc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e893c37ddd0ee4fcc9cdf9faeac= a75eb6a29c0b2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm7635-videocc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm7635-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SM7635 + +maintainers: + - Luca Weiss + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SM7635. + + See also: include/dt-bindings/clock/qcom,sm7635-videocc.h + +properties: + compatible: + const: qcom,sm7635-videocc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: Video AHB clock from GCC + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@aaf0000 { + compatible =3D "qcom,sm7635-videocc"; + reg =3D <0x0aaf0000 0x10000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,sm7635-videocc.h b/include/dt-b= indings/clock/qcom,sm7635-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..5461250792c30e216dc812db722= 562fba7e40dd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7635-videocc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2025, Luca Weiss + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM7635_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM7635_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_PLL0 0 +#define VIDEO_CC_AHB_CLK 1 +#define VIDEO_CC_AHB_CLK_SRC 2 +#define VIDEO_CC_MVS0_CLK 3 +#define VIDEO_CC_MVS0_CLK_SRC 4 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 5 +#define VIDEO_CC_MVS0_SHIFT_CLK 6 +#define VIDEO_CC_MVS0C_CLK 7 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define VIDEO_CC_MVS0C_SHIFT_CLK 9 +#define VIDEO_CC_SLEEP_CLK 10 +#define VIDEO_CC_SLEEP_CLK_SRC 11 +#define VIDEO_CC_XO_CLK 12 +#define VIDEO_CC_XO_CLK_SRC 13 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_MVS0C_BCR 3 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 + +#endif --=20 2.50.0