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Wed, 25 Jun 2025 10:45:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 55PAjFpF007621 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Jun 2025 10:45:15 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Jun 2025 03:45:09 -0700 From: Taniya Das Date: Wed, 25 Jun 2025 16:13:34 +0530 Subject: [PATCH v10 09/10] clk: qcom: videocc-qcs615: Add QCS615 video clock controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250625-qcs615-mm-v10-clock-controllers-v10-9-ec48255f90d8@quicinc.com> References: <20250625-qcs615-mm-v10-clock-controllers-v10-0-ec48255f90d8@quicinc.com> In-Reply-To: <20250625-qcs615-mm-v10-clock-controllers-v10-0-ec48255f90d8@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Catalin Marinas" , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das , Bryan O'Donoghue , Dmitry Baryshkov X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=CPYqXQrD c=1 sm=1 tr=0 ts=685bd33b cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=qYpWxANyOF6Ti2HRg9EA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI1MDA4MCBTYWx0ZWRfX2DnNns4w9HEG kDQUptwP2gXd2cm/sm4kC8b6XD8JQkM78Tj/F/ZczGG0GMSrRlASD97MDEZrKOHUkp7ybkZUwqg ndyhZnquPZc/MyvbbUmAoX2YGp1ZvgQMwS/CHKVbRmGhTugSMnYLwC2WXhChLriTMdR5q/a/6kT vaZsVWf+XQcYINbL2I2oQpicFbOJCdMBbKRlKlpbYlpK8gaY9Y+zJmSPc0ZmHz7aYDz+qooE+CB d14X/aRewuHrKMG/M/7OKWH0p2+Nw2j+lFIPBgzJW6q4YGCs+6MDuIEqpVV5T+JG+3GEBQmWYkZ uuktMKWn9GNImtKi+pCKEBKOSzmQ5hju/3vIlmeXuvD7BtRRUFbKWANtkw4rRs2PG5cfcTDgzTo LxK3q7a9tSm6Q/IC3vTtpvw9LAhogAmsIYW+/xGFbFpAsc2dwtE6nW/lX6+/mrDrkx8gRGNV X-Proofpoint-GUID: k2TFBHYdYxBtNMJbsNFVhqwDGWIdMT_p X-Proofpoint-ORIG-GUID: k2TFBHYdYxBtNMJbsNFVhqwDGWIdMT_p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-25_03,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 impostorscore=0 suspectscore=0 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506250080 Add support for the video clock controller for video clients to be able to request for the clocks on QCS615 platform. Reviewed-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-qcs615.c | 338 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 347 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 204319dc23b58ca816bafb967ff84eb3c069170a..759b24d2c55066b641b1eaf8115= 7aa024e641e92 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -556,6 +556,14 @@ config QCS_GPUCC_615 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config QCS_VIDEOCC_615 + tristate "QCS615 Video Clock Controller" + select QCS_GCC_615 + help + Support for the video clock controller on QCS615 devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config SC_CAMCC_7180 tristate "SC7180 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 35b7f038647a6ed183a4a5ee3ecaefa23525b119..2af0dae787dbacf3a97fd423e73= d15bacfed85ba 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_QCS_GCC_404) +=3D gcc-qcs404.o obj-$(CONFIG_QCS_GCC_615) +=3D gcc-qcs615.o obj-$(CONFIG_QCS_GCC_8300) +=3D gcc-qcs8300.o obj-$(CONFIG_QCS_GPUCC_615) +=3D gpucc-qcs615.o +obj-$(CONFIG_QCS_VIDEOCC_615) +=3D videocc-qcs615.o obj-$(CONFIG_QCS_Q6SSTOP_404) +=3D q6sstop-qcs404.o obj-$(CONFIG_QCS_TURING_404) +=3D turingcc-qcs404.o obj-$(CONFIG_QDU_ECPRICC_1000) +=3D ecpricc-qdu1000.o diff --git a/drivers/clk/qcom/videocc-qcs615.c b/drivers/clk/qcom/videocc-q= cs615.c new file mode 100644 index 0000000000000000000000000000000000000000..1b41fa44c17ea05d637f2cd8dd8= c5b9b94faeeb1 --- /dev/null +++ b/drivers/clk/qcom/videocc-qcs615.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_SLEEP_CLK, + P_VIDEO_PLL0_OUT_AUX, + P_VIDEO_PLL0_OUT_AUX2, + P_VIDEO_PLL0_OUT_MAIN, +}; + +static const struct pll_vco video_cc_pll0_vco[] =3D { + { 500000000, 1000000000, 2 }, +}; + +/* 600MHz configuration VCO - 2 */ +static struct alpha_pll_config video_pll0_config =3D { + .l =3D 0x1f, + .alpha_hi =3D 0x40, + .alpha =3D 0x00, + .alpha_en_mask =3D BIT(24), + .vco_val =3D BIT(21), + .vco_mask =3D GENMASK(21, 20), + .main_output_mask =3D BIT(0), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, +}; + +static struct clk_alpha_pll video_pll0 =3D { + .offset =3D 0x42c, + .config =3D &video_pll0_config, + .vco_table =3D video_cc_pll0_vco, + .num_vco =3D ARRAY_SIZE(video_cc_pll0_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_slew_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0_ao[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_MAIN, 1 }, + { P_VIDEO_PLL0_OUT_AUX, 2 }, + { P_VIDEO_PLL0_OUT_AUX2, 3 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_pll0.clkr.hw }, + { .hw =3D &video_pll0.clkr.hw }, + { .hw =3D &video_pll0.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0xaf8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D video_cc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0_ao), + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_venus_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(133333333, P_VIDEO_PLL0_OUT_MAIN, 4.5, 0, 0), + F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + F(380000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + F(410000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + F(460000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_venus_clk_src =3D { + .cmd_rcgr =3D 0x7f0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_venus_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_venus_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch video_cc_sleep_clk =3D { + .halt_reg =3D 0xb18, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xb18, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "video_cc_sleep_clk", + .parent_data =3D &(const struct clk_parent_data){ + .hw =3D &video_cc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_vcodec0_axi_clk =3D { + .halt_reg =3D 0x8f0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8f0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_vcodec0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_vcodec0_core_clk =3D { + .halt_reg =3D 0x890, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x890, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_vcodec0_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_venus_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ahb_clk =3D { + .halt_reg =3D 0x9b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_venus_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ctl_axi_clk =3D { + .halt_reg =3D 0x8d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_venus_ctl_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ctl_core_clk =3D { + .halt_reg =3D 0x850, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x850, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_venus_ctl_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_venus_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc vcodec0_gdsc =3D { + .gdscr =3D 0x874, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "vcodec0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR, +}; + +static struct gdsc venus_gdsc =3D { + .gdscr =3D 0x814, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "venus_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR, +}; + +static struct clk_regmap *video_cc_qcs615_clocks[] =3D { + [VIDEO_CC_SLEEP_CLK] =3D &video_cc_sleep_clk.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_VCODEC0_AXI_CLK] =3D &video_cc_vcodec0_axi_clk.clkr, + [VIDEO_CC_VCODEC0_CORE_CLK] =3D &video_cc_vcodec0_core_clk.clkr, + [VIDEO_CC_VENUS_AHB_CLK] =3D &video_cc_venus_ahb_clk.clkr, + [VIDEO_CC_VENUS_CLK_SRC] =3D &video_cc_venus_clk_src.clkr, + [VIDEO_CC_VENUS_CTL_AXI_CLK] =3D &video_cc_venus_ctl_axi_clk.clkr, + [VIDEO_CC_VENUS_CTL_CORE_CLK] =3D &video_cc_venus_ctl_core_clk.clkr, + [VIDEO_PLL0] =3D &video_pll0.clkr, +}; + +static struct gdsc *video_cc_qcs615_gdscs[] =3D { + [VCODEC0_GDSC] =3D &vcodec0_gdsc, + [VENUS_GDSC] =3D &venus_gdsc, +}; + +static const struct qcom_reset_map video_cc_qcs615_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x8b0 }, + [VIDEO_CC_VCODEC0_BCR] =3D { 0x870 }, + [VIDEO_CC_VENUS_BCR] =3D { 0x810 }, +}; + +static struct clk_alpha_pll *video_cc_qcs615_plls[] =3D { + &video_pll0, +}; + +static u32 video_cc_qcs615_critical_cbcrs[] =3D { + 0xab8, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_qcs615_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xb94, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data video_cc_qcs615_driver_data =3D { + .alpha_plls =3D video_cc_qcs615_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_qcs615_plls), + .clk_cbcrs =3D video_cc_qcs615_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_qcs615_critical_cbcrs), +}; + +static const struct qcom_cc_desc video_cc_qcs615_desc =3D { + .config =3D &video_cc_qcs615_regmap_config, + .clks =3D video_cc_qcs615_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_qcs615_clocks), + .resets =3D video_cc_qcs615_resets, + .num_resets =3D ARRAY_SIZE(video_cc_qcs615_resets), + .gdscs =3D video_cc_qcs615_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_qcs615_gdscs), + .driver_data =3D &video_cc_qcs615_driver_data, +}; + +static const struct of_device_id video_cc_qcs615_match_table[] =3D { + { .compatible =3D "qcom,qcs615-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_qcs615_match_table); + +static int video_cc_qcs615_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_qcs615_desc); +} + +static struct platform_driver video_cc_qcs615_driver =3D { + .probe =3D video_cc_qcs615_probe, + .driver =3D { + .name =3D "videocc-qcs615", + .of_match_table =3D video_cc_qcs615_match_table, + }, +}; + +module_platform_driver(video_cc_qcs615_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC QCS615 Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1