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Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83c= eca331097ae37 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 +#include +#include #include +#include +#include #include #include #include @@ -1506,6 +1510,18 @@ data-pins { }; }; =20 + gpucc: clock-controller@5090000 { + compatible =3D "qcom,qcs615-gpucc"; + reg =3D <0 0x05090000 0 0x9000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + stm@6002000 { compatible =3D "arm,coresight-stm", "arm,primecell"; reg =3D <0x0 0x06002000 0x0 0x1000>, @@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + videocc: clock-controller@ab00000 { + compatible =3D "qcom,qcs615-videocc"; + reg =3D <0 0x0ab00000 0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@ad00000 { + compatible =3D "qcom,qcs615-camcc"; + reg =3D <0 0x0ad00000 0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,qcs615-dispcc"; + reg =3D <0 0x0af00000 0 0x20000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,qcs615-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x30000>, --=20 2.34.1