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Wed, 25 Jun 2025 11:14:26 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 55PBEPUS012767 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Jun 2025 11:14:25 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Jun 2025 04:14:21 -0700 From: Taniya Das Date: Wed, 25 Jun 2025 16:44:00 +0530 Subject: [PATCH v4 1/2] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250625-qcs615-mm-cpu-dt-v4-v4-1-9ca880c53560@quicinc.com> References: <20250625-qcs615-mm-cpu-dt-v4-v4-0-9ca880c53560@quicinc.com> In-Reply-To: <20250625-qcs615-mm-cpu-dt-v4-v4-0-9ca880c53560@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , Taniya Das , "Konrad Dybcio" X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=YYu95xRf c=1 sm=1 tr=0 ts=685bda12 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=eX7r7zjc-4eniw70hzgA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: oeXgYCeTKFsMakJyaonn4qTyzeFNaQip X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI1MDA4NCBTYWx0ZWRfX7ZGX3A5Myw5Z gD2Gvl3GjrSDm9VutiZmxRi7HAKhLWf49ZCMxb+22WV85NHvFeAqInu7kVVSYwLWOAm+W+WhekZ LTWPPNQLwYp4z/IRL4lRWNQWqGESCNyzKJlx3uGucsxXUrRBHxUzepmo7MfhX9YxONUT3kNtrZF 8xd63jq/U679+4GqlOvqyecmtRi4mjIT8l+KCn+l3EDFpZX7MSkIjT4YIRyvR7/NfrcfPCQBSNC 8Tvsce7pVqKORY8ywAbR9DWxjK/En+gTMhne0UfQ6JtY12w4aTmHq85bK3xs5Wf+DZ5ZtiC1czw lVPGH7eP+UFo+BA3u/QamQHCa37YvU4jflNZrT3lp8GXiW7pEfNT2ERKNDVKTmFPpn3iGm0eCyu lV3/VwY5qMXvGAgy0Fv55Hu/tpQWOQ9o+GX9wAUPEZdvViHDOuZXalcM8z/oF0H531um+DIE X-Proofpoint-ORIG-GUID: oeXgYCeTKFsMakJyaonn4qTyzeFNaQip X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-25_03,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506250084 Add support for video, camera, display and gpu clock controller nodes for QCS615 platform. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83c= eca331097ae37 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 +#include +#include #include +#include +#include #include #include #include @@ -1506,6 +1510,18 @@ data-pins { }; }; =20 + gpucc: clock-controller@5090000 { + compatible =3D "qcom,qcs615-gpucc"; + reg =3D <0 0x05090000 0 0x9000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + stm@6002000 { compatible =3D "arm,coresight-stm", "arm,primecell"; reg =3D <0x0 0x06002000 0x0 0x1000>, @@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + videocc: clock-controller@ab00000 { + compatible =3D "qcom,qcs615-videocc"; + reg =3D <0 0x0ab00000 0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@ad00000 { + compatible =3D "qcom,qcs615-camcc"; + reg =3D <0 0x0ad00000 0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; 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Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 5adf409d7ce7226042c759cc83ceca331097ae37..d06fc1c157454f635389ff0645f= cf4b378270dbc 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -36,6 +36,8 @@ cpu0: cpu@0 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_0>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; =20 l2_0: l2-cache { @@ -56,6 +58,8 @@ cpu1: cpu@100 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_100>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_100: l2-cache { compatible =3D "cache"; @@ -75,6 +79,8 @@ cpu2: cpu@200 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_200>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_200: l2-cache { compatible =3D "cache"; @@ -94,6 +100,8 @@ cpu3: cpu@300 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_300>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_300: l2-cache { compatible =3D "cache"; @@ -113,6 +121,8 @@ cpu4: cpu@400 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_400>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_400: l2-cache { compatible =3D "cache"; @@ -132,6 +142,8 @@ cpu5: cpu@500 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&l2_500>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; =20 l2_500: l2-cache { compatible =3D "cache"; @@ -151,6 +163,8 @@ cpu6: cpu@600 { capacity-dmips-mhz =3D <1740>; dynamic-power-coefficient =3D <404>; next-level-cache =3D <&l2_600>; + clocks =3D <&cpufreq_hw 1>; + qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; =20 l2_600: l2-cache { @@ -171,6 +185,8 @@ cpu7: cpu@700 { capacity-dmips-mhz =3D <1740>; dynamic-power-coefficient =3D <404>; next-level-cache =3D <&l2_700>; + clocks =3D <&cpufreq_hw 1>; + qcom,freq-domain =3D <&cpufreq_hw 1>; =20 l2_700: l2-cache { compatible =3D "cache"; @@ -3891,6 +3907,19 @@ glink_edge: glink-edge { qcom,remote-pid =3D <2>; }; }; + + cpufreq_hw: cpufreq@18323000 { + compatible =3D "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; + reg =3D <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; + reg-names =3D "freq-domain0", "freq-domain1"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + }; =20 arch_timer: timer { --=20 2.34.1