From nobody Wed Oct 8 17:34:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00ADC264A74; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; cv=none; b=Di2UldZrYpgFereibpCjUi+8M6/v/U49iHsMBSbDoKhc+WmnziCLZgLvmpDb7Q9a0Bz2iHlmwGWt37qDw0TcexcZZYKz+yV/Opb4I+7xrM7qYGSuZP8S+SvwwEnNmjA66A2DsA7YpMo1PwcTckzJUjRwCoc9LFQLeygqykeCH3Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; c=relaxed/simple; bh=GKbzOIdtzFvop5ar2d9+3emwLLF5QXNzgs6b3CUkOPk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AIvTX2dyd0fLJmp6yQETGIgM2H8gUsteCE/9JtBbsHCGRAIrD+/z6bFycPxwxkzt7mICO/HU7xT2OYu0yujq+ndHb5QgG4VH6V41ZWGAFNSF2sVudreXoOd/VHvWgxpheUJtoqf/i/vAMJJHyxDrxVH2j3AsLx0DeOiHxRjJ7Po= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=flDlzeJn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="flDlzeJn" Received: by smtp.kernel.org (Postfix) with ESMTPS id 91366C4CEEA; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750861259; bh=GKbzOIdtzFvop5ar2d9+3emwLLF5QXNzgs6b3CUkOPk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=flDlzeJnraRftrK84Q+l68/q/JKOEfSgZhA69SlgO8yO+F9A1fEf7ng+zjIViJzs7 ZA9xWqh9g40IUaVwyRpV3XOzl00L9NIvk/0hhnsrxLvRpxqQrR2TvtQ6Bt8fUxCWCB hL/0es/zvq16yRcaRGV6X5Te0cpG7lJ81cR0VJQ6olIXCtNIK91TB7YcgFTvT2LkDy C1vzQW1Ev4O7Ki8iv7RM0d2QARCni3nXLyRe1I5wdjhl1oVvH7hvjabf5wQ06fXTxZ qKHPOgp75vG4+ZhvpHi0FbWejHOBxx1nFrYKzY+sKh93l1mu3oBoUGgbjlTRo7vetE 0qGeMVrsWsHNA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77C42C7115C; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 25 Jun 2025 16:20:56 +0200 Subject: [PATCH v4 1/7] dt-bindings: riscv: Add xmipsexectl ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-p8700-pause-v4-1-6c7dd7f85756@htecgroup.com> References: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> In-Reply-To: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750861257; l=1302; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=h13o/f46vhfOxj3D4iHSUN8apIuhKjiCZWPiTgA7Dm8=; b=bybQmtA8JYGfk8SiLTuOilDEXK5tT9xmFca05oXB0CyhBAtjNDrFXIGgHUHKdAijZXjcbV3p1 JgyhwV4egd+C8PDaz7ap5wnXKVTad51WO59WymZenWRomONPsWUPyfr X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic The xmipsexectl extension is described in the MIPS RV64 P8700/P8700-F Multiprocessing System Programmer=E2=80=99s Guide linked at [1]. Link: https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Referen= ce_Manual_Rev1.84_5-31-2025.pdf Signed-off-by: Aleksa Paunovic Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index ede6a58ccf5347d92785dc085a011052c1aade14..de41a6f074d3af2ceaf5293dfe7= 5d16f43d416d6 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -662,6 +662,12 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.= 0.0-Datasheet.pdf =20 + # MIPS + - const: xmipsexectl + description: + The MIPS extension for execution control as documented in + https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_= Reference_Manual_Rev1.84_5-31-2025.pdf + # SiFive - const: xsfvqmaccdod description: --=20 2.34.1 From nobody Wed Oct 8 17:34:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00B40264A7C; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; cv=none; b=ZRp1FY9zy/V4om3Fe9Nuy+NYO2QPqnSZ0mqRBB1H8iDtU1LvIO1BCdbebVwzfLbGoQps7V5iM9YLfFsdm6lKwiqZIa7Hglzo/6HmMa7LA+Tc4P7U93QvwSHEM+3sbPLRiWu3hgEUKi68sxeYmWFKe4stPEbd2UNebaZg40Tmbus= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; c=relaxed/simple; bh=9/w0s/AcGaLZDmP6rWTTjg/6zkeEgbPdsIflpQ6oanA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=t1H9nMTvDq++dlLQTkxhRFWqbBRngFGP6fMqu751JoPUa/T7mBdHSY7L/vakUSO5Q0Nw+e6JxIzrEi9/K4eURJM9J8/ye3kKCPj1Awgk4CPQ/SUSmn8VO/8+1FL0BnUQJpbzh/sgqYUSfAwlbMRSNgTicOJT6OMq05VdjYRv5RE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e7aZOUAR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e7aZOUAR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 992DCC4CEF5; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750861259; bh=9/w0s/AcGaLZDmP6rWTTjg/6zkeEgbPdsIflpQ6oanA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=e7aZOUARc1frPkmKfagHGLCYTy3tPMQdQQDI+w/lAp9DynbrZw3Zu5uemFrsY6Esr CrNaBA72KxpGpWLkOmVdYVtbgOBj2IGiH2BnSwk0/GKVv/2kqK5+3G/OmeO7Pf8+/u ai0Fdwe88avpsX+x9Ln2m3ItJAFwylGtJfTgNq4PPQ7MC6AYXisIrQBOiGvnzMFfI5 Nk27QuGKaBNxM01loTxWBcu9OVxrVu81qhbwWMfS4JFsg3fi5+fk18HT7HLNNrOL+S 2MbckYw2CKVR6/sHz2lLAXp71VYY2+oR8gQTypAUhdBl36arkOtcXXyknCUdqoSWIY QOWWtlRGSoOVQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86B96C7EE33; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 25 Jun 2025 16:20:57 +0200 Subject: [PATCH v4 2/7] riscv: Add xmipsexectl as a vendor extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-p8700-pause-v4-2-6c7dd7f85756@htecgroup.com> References: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> In-Reply-To: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750861257; l=5238; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=idU65tzeIlPrlIohcZNq9ktJdzyHclYmJbVJ2jCsPDc=; b=kO8mk5hvK45YHZ9X0kMzHOWgOPjhwHEqgpLRpKkIBTkcoqrd7zNTg6y6OhQE5GZL2eta/yfJ3 OztvXZ7CAAoBNl8EU1u+SK5GUzcENCVAIkFvVXUwFyZyaIx3FeXY9hj X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add support for MIPS vendor extensions. Add support for the xmipsexectl vendor extension. Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- arch/riscv/Kconfig.vendor | 13 +++++++++++++ arch/riscv/include/asm/vendor_extensions/mips.h | 16 ++++++++++++++++ arch/riscv/kernel/vendor_extensions.c | 10 ++++++++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + arch/riscv/kernel/vendor_extensions/mips.c | 22 ++++++++++++++++++++++ 5 files changed, 62 insertions(+) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index e14f26368963c178e3271e0f716b27fff7671e78..3c1f92e406c3f21481b56e61229= 716fd02ab81b2 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES If you don't know what to do here, say Y. endmenu =20 +menu "MIPS" +config RISCV_ISA_VENDOR_EXT_MIPS + bool "MIPS vendor extension support" + select RISCV_ISA_VENDOR_EXT + default y + help + Say N here to disable detection of and support for all MIPS vendor + extensions. Without this option enabled, MIPS vendor extensions will + not be detected at boot and their presence not reported to userspace. + + If you don't know what to do here, say Y. +endmenu + menu "SiFive" config RISCV_ISA_VENDOR_EXT_SIFIVE bool "SiFive vendor extension support" diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/i= nclude/asm/vendor_extensions/mips.h new file mode 100644 index 0000000000000000000000000000000000000000..757c941cfd86e9fced6169b1a82= 200e6bb5c6132 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/mips.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 MIPS. + */ + +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H + +#include +#include + +#define RISCV_ISA_VENDOR_EXT_XMIPSEXECTL 0 + +extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mip= s; + +#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vend= or_extensions.c index 92d8ff81f42c9ceba63bef0170ab134564a24a4e..bb4a7592368560ebacbcd8a5ce3= 35eea6312ea5c 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include =20 @@ -16,6 +17,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_e= xt_list[] =3D { #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES &riscv_isa_vendor_ext_list_andes, #endif +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS + &riscv_isa_vendor_ext_list_mips, +#endif #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE &riscv_isa_vendor_ext_list_sifive, #endif @@ -49,6 +53,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, uns= igned long vendor, unsig cpu_bmap =3D riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap; break; #endif + #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS + case MIPS_VENDOR_ID: + bmap =3D &riscv_isa_vendor_ext_list_mips.all_harts_isa_bitmap; + cpu_bmap =3D riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap; + break; + #endif #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE case SIFIVE_VENDOR_ID: bmap =3D &riscv_isa_vendor_ext_list_sifive.all_harts_isa_bitmap; diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index a4eca96d1c8a2fd165220f6439a3884cf90a9593..ccad4ebafb43412e72e654da3bd= b9face53b80c6 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) +=3D mips.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive_hwprobe.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o diff --git a/arch/riscv/kernel/vendor_extensions/mips.c b/arch/riscv/kernel= /vendor_extensions/mips.c new file mode 100644 index 0000000000000000000000000000000000000000..f691129f96c21f2ef089124f4b6= 4a6f0a8e6d4aa --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/mips.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include + +#include +#include +#include + +/* All MIPS vendor extensions supported in Linux */ +static const struct riscv_isa_ext_data riscv_isa_vendor_ext_mips[] =3D { + __RISCV_ISA_EXT_DATA(xmipsexectl, RISCV_ISA_VENDOR_EXT_XMIPSEXECTL), +}; + +struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips =3D { + .ext_data_count =3D ARRAY_SIZE(riscv_isa_vendor_ext_mips), + .ext_data =3D riscv_isa_vendor_ext_mips, +}; --=20 2.34.1 From nobody Wed Oct 8 17:34:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 330A8265CBE; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; cv=none; b=VbyhLt7CMBGQbGuto50fLey/AWYVp47iZZmnZH9VxDG6O1Mzbt1wpYpJzH+LVUb22H6WZxupIshnuTS6MYZrOl9tgISWce0JWZ51mxvvN8y70CEqhbDrEUNKiMlB00NZLgOhXBw/Hiuv95AwqF29TrV3gniAqxWzVJTQsukBYwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; c=relaxed/simple; bh=IdkAyRPazTQAAsOxhm5SnUrAbQOii+a0gCXU9wFfUG8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iH7THjfdLMfE8ikeoA1OmS7CGYU9TRev1RK1pWsDr9FYNIMX3u/3w7YHHZLf3VJyXIr7OKSz5BWwhJzMsc98c83YzagoHjvaqivngYF1u76pMGsMdUS5kHSZgCs0whCqrDpeZ8Mq/KfIQsB5dm1/2kBCcdGqiIoJfM19Az0i3pc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rvOjBZOB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rvOjBZOB" Received: by smtp.kernel.org (Postfix) with ESMTPS id A8E3FC4CEF6; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750861259; bh=IdkAyRPazTQAAsOxhm5SnUrAbQOii+a0gCXU9wFfUG8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rvOjBZOBmfMmqRPKiOAKQTC0hFb3FygpSI3wKZzzWuUPNcuPyxBvyLmaLFmJ0wq1e hwY5kZeBIFiNWQFr+mtws+j2Mk1Y54XtLsT8aTzPZ9f0GtK43oKE/mwRta7C2QPfWv 4KjJZouymgDF0lGn3wmbEjPUn14IVz8POE1S2+E1THqdoHnY49hn2RObIi8FzJUF0w 8g4woFZT/ybEtLgnazg5DPWtvfX9VpJs6vzak420MYf3G4lBoXZzlRBbvq2wzie+l/ d3l+GVrte1OvnWUlHUIvTqiB2nHXn6Ts5uVCd4ZC+RDYs+urCAPpb/cXcBgbdB5Krb +qRErtRMfcaow== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 977B3C7EE30; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 25 Jun 2025 16:20:58 +0200 Subject: [PATCH v4 3/7] riscv: Add xmipsexectl PAUSE instruction Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-p8700-pause-v4-3-6c7dd7f85756@htecgroup.com> References: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> In-Reply-To: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750861257; l=1045; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=H0DxxoGpB6+hFMlnoBCgKy/YEJN661bNeg8dzqTTc9Y=; b=j7mQ6M5PdjVnNF0Zd2eESw6UiAPu59p74ZSfKVOFi6F9oGfE+2+5A6EVzEf/XaS+NC9vhT0Du XMLyI4dbDM9AoC8vs7d+rXKvwQOcX3466I12/JDG/c8n/dmgsVwKKJ/ X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add MIPS.PAUSE instruction opcode. This instruction is a part of the xmipsexectl vendor extension. Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/vendor_extensions/mips.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/i= nclude/asm/vendor_extensions/mips.h index 757c941cfd86e9fced6169b1a82200e6bb5c6132..f8eca0bcf53e2de1bbdc66821fe= 95987105ed85a 100644 --- a/arch/riscv/include/asm/vendor_extensions/mips.h +++ b/arch/riscv/include/asm/vendor_extensions/mips.h @@ -13,4 +13,11 @@ =20 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mip= s; =20 +/* MIPS.PAUSE is an alternative opcode which is implemented to have the */ +/* same behavior as PAUSE on some MIPS RISCV cores. */ +/* It is a =E2=80=98hint=E2=80=99 encoding of the SLLI instruction, */ +/* with rd =3D 0, rs1 =3D 0 and imm =3D 5. */ + +#define MIPS_PAUSE ".4byte 0x00501013\n\t" + #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H --=20 2.34.1 From nobody Wed Oct 8 17:34:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 318D1265CAA; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; cv=none; b=cMw58WaqkWzY3K6lT5M8qyxoKqFLBkmwe7+Mrzp0BdlkKaMSkTuoSCLcQeVmZTg+uZ/r4oI3UfkmECSTsCOliE4F0VjGAyh0qDJ2lqaUeUd8PP0Ad70MZSoXY6vkxq5+WiJZf+mWIemfXaQmHI/u0bcg5UOtMcBKyJu0WKALEO4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; c=relaxed/simple; bh=r/g52Sw7NE3cZ4s+t+ohbfBzr9iGvkNvjqfeVNpE7FQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DwnEsX4GK/KQ5PD4HOeiVQju3nYna1sT2hCEmBTGqxNfHOsZI4IKu77Kvbuo54/40syWej3f+onoNU4t29qcP+sKbn5nS5SawZnfxGJYYzuWa7zR95A8ZpVfxdqnH5y5l3ZUUHIxGeZlT0/FdUCjNGSmGn02kHoM+DkkUPI5oyc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=upzViby8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="upzViby8" Received: by smtp.kernel.org (Postfix) with ESMTPS id B6F0DC4AF0D; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750861259; bh=r/g52Sw7NE3cZ4s+t+ohbfBzr9iGvkNvjqfeVNpE7FQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=upzViby8EQuva8lr/4oenmGINdY9cilyMktgzhlfDm9eJCX+RFmyuthJv498IYo5e 04XAyroc0vg8RaNHfV4H0ycOk3CmJpXFBlNl/f86j7/yBmU5ifttGnnP7az+EDGwON 6XraF55xTvqJLFYlkJmOhY1aojILQh7P1wu+Jx/qDkX3rrVDpKoeoBcF39LtpinDnA oQxUWOb/eM/8EVyPlwGRIpjewvlLrbrOK33FJ08hiqTr1+F3DFJjikHFo7IVKODMNf 1vjM7HKnXWzF7K/scCSBz+S82jLwhAUhXwLt6mYy93Hj2miK3UpJJijA6/cz8B0Hkx oWb9shvPDBuiw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5668C7EE39; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 25 Jun 2025 16:20:59 +0200 Subject: [PATCH v4 4/7] riscv: hwprobe: Add MIPS vendor extension probing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-p8700-pause-v4-4-6c7dd7f85756@htecgroup.com> References: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> In-Reply-To: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750861257; l=5977; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=/ra2A5ZQBIS0eY7nK1+Pygc9iGRZBnPpkjFyim2jAcM=; b=DKnf1MnaJfdG4LaMyGA42WkhQmot9xI5Tl2HPA2YoVTRV69zvFWo+5MJTGdWmn3ejdsDCkkjI gBuFjf9NjEHD27S1ci/8j0AnZGzSBn9L6JtoKkBqwRfZyA1CFDVQS4K X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" which allows userspace to probe for the new xmipsexectl vendor extension. Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/hwprobe.h | 3 ++- .../include/asm/vendor_extensions/mips_hwprobe.h | 23 ++++++++++++++++++= ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/include/uapi/asm/vendor/mips.h | 3 +++ arch/riscv/kernel/sys_hwprobe.c | 4 ++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + arch/riscv/kernel/vendor_extensions/mips_hwprobe.c | 22 ++++++++++++++++++= +++ 7 files changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 7fe0a379474ae2c64d300d6fee4a012173f6a6d7..948d2b34e94e84e4c2c351ffe91= f4b3afcefc3f7 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,7 +8,7 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 13 +#define RISCV_HWPROBE_MAX_KEY 14 =20 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { @@ -22,6 +22,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) case RISCV_HWPROBE_KEY_IMA_EXT_0: case RISCV_HWPROBE_KEY_CPUPERF_0: case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: + case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0: case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0: return true; } diff --git a/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h b/arch= /riscv/include/asm/vendor_extensions/mips_hwprobe.h new file mode 100644 index 0000000000000000000000000000000000000000..0af8c07c22f293b5f772709f774= de78dd60c7f39 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 MIPS. + */ + +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_ +#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_ + +#include +#include + + +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS +void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair, const struc= t cpumask *cpus); +#else +static inline void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pai= r, + const struct cpumask *cpus) +{ + pair->value =3D 0; +} +#endif + +#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index aaf6ad97049931381f9542bb9316c873ec6ab9f6..5d30a4fae37a82ef4d968d20b18= 7420772ad8946 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -106,6 +106,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 11 #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13 +#define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 /* Flags */ diff --git a/arch/riscv/include/uapi/asm/vendor/mips.h b/arch/riscv/include= /uapi/asm/vendor/mips.h new file mode 100644 index 0000000000000000000000000000000000000000..11d41651178233a5f06ab9541ea= 0506d9883aa19 --- /dev/null +++ b/arch/riscv/include/uapi/asm/vendor/mips.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#define RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 0b170e18a2beba576f4f8787d6ef6aa67c5c3d0e..6c73e167ef4ccc7f99dd2793acd= e2595fffdcbad 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -309,6 +310,9 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: hwprobe_isa_vendor_ext_thead_0(pair, cpus); break; + case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0: + hwprobe_isa_vendor_ext_mips_0(pair, cpus); + break; =20 /* * For forward compatibility, unknown keys don't fail the whole diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index ccad4ebafb43412e72e654da3bdb9face53b80c6..bf116c82b6bdb3aee23e27fc0b2= a69be7c7a5ccb 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -2,6 +2,7 @@ =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) +=3D mips.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) +=3D mips_hwprobe.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive_hwprobe.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o diff --git a/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c b/arch/risc= v/kernel/vendor_extensions/mips_hwprobe.c new file mode 100644 index 0000000000000000000000000000000000000000..43944f2b484af257fa358cda53c= 12b4d6f54b78b --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include + +#include +#include + +#include +#include + +void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + VENDOR_EXTENSION_SUPPORTED( + pair, cpus, riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap, + { VENDOR_EXT_KEY(XMIPSEXECTL); }); +} --=20 2.34.1 From nobody Wed Oct 8 17:34:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C197265CDD; Wed, 25 Jun 2025 14:21:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; cv=none; b=BN9lSM531+SANoB1BZYHz8Wj75762WF3tbsVL9+TScPqsx+hG2cSVW4l1YnaLGJWGgnWu/ocS6PCCW1cJ0MWWyHgyErZzad7BOJRi6Fs0Fp+oQfn7oGOW/XGpb7zbN02bIW8iWeUp4Pm3kzlA6Ch6qsRvucUaQnfcgW66f/CPvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; c=relaxed/simple; bh=MUzSQxk+uv5LHDef99dQW3jjbO9uT/OkYjA1LD8vXs4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lDobcqfihb+mAWpBXDuqMY6R3fPCS5r+wy/8CyRPzpMrZAOcCDh9bKhbRpzli9lCTSC4S4K6tfhpLNqiedevCRwPUOOYcy8OJfzTKyHwmONfTyKSPmhO8bQyx0mse8t9W+7P6fO+C2fynn+8QiGmB9LT25C7uUE4hQIgfZ2qf2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oFfCTGzv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oFfCTGzv" Received: by smtp.kernel.org (Postfix) with ESMTPS id BECA8C113CF; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750861259; bh=MUzSQxk+uv5LHDef99dQW3jjbO9uT/OkYjA1LD8vXs4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oFfCTGzvb4Bl6w9ywnJZTx1aXzKR3gwgfv6u7wB07Es6QWTqfqW9cRH/1PgBL4SFk bZQ+htWAiQr5A1sViXdUafNvAb0O+Sx76eUBxjKI8+HZ0UJ69fcm3tM+dsTpEV2D9H e7vxu7gyunNTk5Oqn1Z12BoqJMKt0S/GlgO2wACq4mbjvm8S5M1NJPQ1q3nidVHXU8 M/bBj+6Bay1xKMFEI7vLhTNr4ViVwhkqYvTRoQilDRqmfjGtQ2T2zn5Y6aj6zu45r2 PX5BuYLc0XusREkesoIiBC9YvcE+drO5kpefQmSbYJHzUHWjtd6Ob8v6JKSyux2Enl uYfg43FZ99/4w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4976C7EE3A; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 25 Jun 2025 16:21:00 +0200 Subject: [PATCH v4 5/7] riscv: hwprobe: Document MIPS xmipsexectl vendor extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-p8700-pause-v4-5-6c7dd7f85756@htecgroup.com> References: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> In-Reply-To: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750861258; l=1433; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=ONKDrupJVIvTuOPl4HYtUjJG9+vS9PioyKkmG/eBvIA=; b=lB3maqHxBHGl1G03VPK/N0rQBhStz3QP5CAL+JiHBDDtytrfEuPLDlOiUTcZ54+Wunt80Dc/n VTN80isflIeA6/Zvx9uUZq8VhatdJ0LTU1vbFSaPLzkjJx/eqQBSufN X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Document support for MIPS vendor extensions using the key "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" and xmipsexectl vendor extension using the key "RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL". Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- Documentation/arch/riscv/hwprobe.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 2aa9be272d5de1c15559a978a956bc36c34de81c..2f449c9b15bdd6b9813c9a968de= ca1a4c4ff9b14 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -327,6 +327,15 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vec= tor accesses are not supported at all and will generate a misaligned address fault. =20 +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the + mips vendor extensions that are compatible with the + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * MIPS + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl ven= dor + extension is supported in the MIPS ISA extensions spec. + * :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the thead vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. --=20 2.34.1 From nobody Wed Oct 8 17:34:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D9D3266B41; Wed, 25 Jun 2025 14:21:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; cv=none; b=Dbkna5536mo90OtehQwF3qkdSCg+QxZnn9m+42Td2fKH+fc8173OdnBC+cgrp/Iqoi3POkenPYvuPwcd/SnzA9yfJTBgNJOI6hNTfIY8+3hWMOn5DeytIkIz0TSB95v/kDZ/n1xURu2ikwZ7CJdDph3lmfnmJKQ6QHgLDt9OFWo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; c=relaxed/simple; bh=ekFrZC5Q8HAZmivsKkul5NZgQJY/Ur7Qwq0Ni+Ze2Wo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d/T2ACV2FNXNjT142+5PVebQnL7RPVKfh+IKVIg/8fcY9f2bI+q7ldvgep/yx+9YuWnTpMv28hUIGFyAplFzOjIZwdL1ZugGJ4iOw0kWyfSudlnv/H93IENf5Gok2j05A3jN9qYyQwbQJT0E0UuPY2UOCEmNWJEVKmFRjnoy7fc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sKjlndDf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sKjlndDf" Received: by smtp.kernel.org (Postfix) with ESMTPS id CCA1DC113D0; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750861259; bh=ekFrZC5Q8HAZmivsKkul5NZgQJY/Ur7Qwq0Ni+Ze2Wo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=sKjlndDfq6MxaQtVWwjpM2UFDVFv9aVG+aWi320g51XsmRAGUa+nh68dzP1bsD0uQ KF4FtQ9Ar02z5Eb8VY0cT8okQXRWcHAuyVTqYIMJUWDEU77NXD8xq1ttGC60QU6Aak bxnUU4r4h2sU1ij6LANPdsS5RnV+229meHCYZzxP+sA+iZPPSqYG/vP919FdSRvX/Z XIVmGBKVO93O9/xVT+KEoL1A6KwPTZDJmVgRbCzXGGa+tBqdAY1COvjpwtF+G2Gx5M 60upm3f37RC3wKnMiWKMpMsFn5lGSo0ibNjxtb917MBPs3rOqDpffq/PCKV/BDK9H1 K3ggruSE/8BVA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1D68C77B7C; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 25 Jun 2025 16:21:01 +0200 Subject: [PATCH v4 6/7] riscv: Add tools support for xmipsexectl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-p8700-pause-v4-6-6c7dd7f85756@htecgroup.com> References: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> In-Reply-To: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750861258; l=1752; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=fl56XWVJR0cTZUk8jRyTT/lTH2lW6qnyqDJH+9PnqIY=; b=Mto7g5DhM1M9UonaHroS3dZuhWFPjWkGx378MbcFfXJMl3jVTE46hQiw0X4lreIe3FgNutkbE L075sqhpGpaCKa3IvHFij2pGGw2CdOaZ1s0MKYdbLOQsfXKWFHo4R1e X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Use the hwprobe syscall to decide which PAUSE instruction to execute in userspace code. Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++------= ---- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/ris= cv/include/asm/vdso/processor.h index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f82= 24af29498707c 100644 --- a/tools/arch/riscv/include/asm/vdso/processor.h +++ b/tools/arch/riscv/include/asm/vdso/processor.h @@ -4,26 +4,33 @@ =20 #ifndef __ASSEMBLY__ =20 +#include +#include +#include #include =20 static inline void cpu_relax(void) { + struct riscv_hwprobe pair; + bool has_mipspause; #ifdef __riscv_muldiv int dummy; /* In lieu of a halt instruction, induce a long-latency stall. */ __asm__ __volatile__ ("div %0, %0, zero" : "=3Dr" (dummy)); #endif =20 -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE - /* - * Reduce instruction retirement. - * This assumes the PC changes. - */ - __asm__ __volatile__ ("pause"); -#else - /* Encoding of the pause instruction */ - __asm__ __volatile__ (".4byte 0x100000F"); -#endif + pair.key =3D RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0; + __riscv_hwprobe(&pair, 1, 0, NULL, 0); + has_mipspause =3D pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL; + + if (has_mipspause) { + /* Encoding of the mips pause instruction */ + __asm__ __volatile__(".4byte 0x00501013"); + } else { + /* Encoding of the pause instruction */ + __asm__ __volatile__(".4byte 0x100000F"); + } + barrier(); } =20 --=20 2.34.1 From nobody Wed Oct 8 17:34:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7456D266F15; Wed, 25 Jun 2025 14:21:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; cv=none; b=qMpuZTutaLoLq4oLu/QyFVca7Jvzt4mvV7Ph8p9BybSXQKUV/tXKtWfwPKmP+H87TxBkHLOaAvpsjZ84DJFft0MD//PwmC55kzuk+j7eA3EEg56Dfur9ItH8HOLSbzhcuTrAdQ4le7psaU033fupBUQuAhOP2DPsXhGc/T6XgoE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750861260; c=relaxed/simple; bh=wmBPWtMoM+wFS8GN4VZ0OTHCumM78Iu976yjPsYyihs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=g2aCrgS1gMEnAzUedOh8g36uRsNfTOVHBFAR8VB/7KxgHGhEY8kB0YZYinU34ZwxaP+lpd8d3OLJph5hYUx0XsEDj7XHwfCgOpNbK0Lp4JBJ36FEM/q2jtFK3QAZCC9yjp7JaySkLKV7KuPrS5HMWIGxXsmG3iajaUdGPo+0jJ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F1/xGXc3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F1/xGXc3" Received: by smtp.kernel.org (Postfix) with ESMTPS id E08C4C4AF10; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750861260; bh=wmBPWtMoM+wFS8GN4VZ0OTHCumM78Iu976yjPsYyihs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=F1/xGXc3e+YomSe+9RTzgU0UCdzPkBrKUap54QVuUGgg3RyNN6PldEG+sGPxsqhq4 Q3waTzsemhaNOueUnGSjD5VFM9+l9TuvXG/Ms6TsUdQ5ZaVjCHkPip4boKckMgQFJk aQgbIgCCj5fdmsYSPiuCb99mJoqcidtHUZ3Xwc2h2rUqD+5O2VNQY/37frR+6rOxFk 4fug/0Imab9gtGiEm+xdM60gbHBjTiIV4j1OaIiUn2fNuvCqmvMExLW+gaqHLSANJF GN/KsyVk1pm/fTSj8MN62q6cR2jIj2igFI4Z+at4EqSLRZFPnwGI0IMCy1rkalBmUK 5UOtbKhYofUzw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF4A7C7EE33; Wed, 25 Jun 2025 14:20:59 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 25 Jun 2025 16:21:02 +0200 Subject: [PATCH v4 7/7] riscv: errata: Fix the PAUSE Opcode for MIPS P8700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-p8700-pause-v4-7-6c7dd7f85756@htecgroup.com> References: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> In-Reply-To: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic , Djordje Todorovic , Aleksandar Rikalo , Raj Vishwanathan4 X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750861258; l=10530; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=ieaO9S2ok/je5oJYp/rO2uITgquZ3AoPbwIaliUX7A8=; b=IZVDL0F4scFZTJalYI0TYrVZXOsLbMhASsUCMkJXhVwDDNtRwXCVJlGpIxKDZruxXEm715Pgd g1xbL4grb5uB65/KEZZtQTsow2QtiBZgJuX41VBFVHem8v72cTn4dqS X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Djordje Todorovic Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs. Handle errata for the MIPS PAUSE instruction. Signed-off-by: Djordje Todorovic Signed-off-by: Aleksandar Rikalo Signed-off-by: Raj Vishwanathan4 Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- arch/riscv/Kconfig.errata | 23 +++++++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/mips/Makefile | 5 +++ arch/riscv/errata/mips/errata.c | 67 +++++++++++++++++++++++++++++= ++++ arch/riscv/include/asm/alternative.h | 3 ++ arch/riscv/include/asm/cmpxchg.h | 3 +- arch/riscv/include/asm/errata_list.h | 17 ++++++++- arch/riscv/include/asm/vdso/processor.h | 4 +- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/alternative.c | 5 +++ arch/riscv/kernel/entry.S | 2 + arch/riscv/mm/init.c | 1 + 12 files changed, 129 insertions(+), 3 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e318119d570de0acc0850a2e1a2505ecb71bea08..aca9b0cfcfecf91d4d1910f294e= e109ed15f2d6c 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -21,6 +21,29 @@ config ERRATA_ANDES_CMO =20 If you don't know what to do here, say "Y". =20 +config ERRATA_MIPS + bool "MIPS errata" + depends on RISCV_ALTERNATIVE + help + All MIPS errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all MIPS errata. Please say "Y" + here if your platform uses MIPS CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_MIPS_P8700_PAUSE_OPCODE + bool "Fix the PAUSE Opcode for MIPS P8700" + depends on ERRATA_MIPS && 64BIT + default n + help + The RISCV MIPS P8700 uses a different opcode for PAUSE. + It is a 'hint' encoding of the SLLI instruction, + with rd=3D0, rs1=3D0 and imm=3D5. It will behave as a NOP + instruction if no additional behavior beyond that of + SLLI is implemented. + + If you are not using the P8700 processor, say n. + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index bc6c77ba837d2da4c98dabab18083d27f46629c7..02a7a3335b1d557933e04cd6d0c= f7bf4260b8c40 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -13,5 +13,6 @@ endif endif =20 obj-$(CONFIG_ERRATA_ANDES) +=3D andes/ +obj-$(CONFIG_ERRATA_MIPS) +=3D mips/ obj-$(CONFIG_ERRATA_SIFIVE) +=3D sifive/ obj-$(CONFIG_ERRATA_THEAD) +=3D thead/ diff --git a/arch/riscv/errata/mips/Makefile b/arch/riscv/errata/mips/Makef= ile new file mode 100644 index 0000000000000000000000000000000000000000..6278c389b801ee6e54e808c80e6= e236c026329c7 --- /dev/null +++ b/arch/riscv/errata/mips/Makefile @@ -0,0 +1,5 @@ +ifdef CONFIG_RISCV_ALTERNATIVE_EARLY +CFLAGS_errata.o :=3D -mcmodel=3Dmedany +endif + +obj-y +=3D errata.o diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errat= a.c new file mode 100644 index 0000000000000000000000000000000000000000..e984a8152208c34690f89d81015= 71b097485c360 --- /dev/null +++ b/arch/riscv/errata/mips/errata.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static inline bool errata_probe_pause(void) +{ + if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE)) + return false; + + if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL)) + return false; + + return true; +} + +static u32 mips_errata_probe(void) +{ + u32 cpu_req_errata =3D 0; + + if (errata_probe_pause()) + cpu_req_errata |=3D BIT(ERRATA_MIPS_P8700_PAUSE_OPCODE); + + return cpu_req_errata; +} + +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage) +{ + struct alt_entry *alt; + u32 cpu_req_errata =3D mips_errata_probe(); + u32 tmp; + + BUILD_BUG_ON(ERRATA_MIPS_NUMBER >=3D RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + for (alt =3D begin; alt < end; alt++) { + if (alt->vendor_id !=3D MIPS_VENDOR_ID) + continue; + + if (alt->patch_id >=3D ERRATA_MIPS_NUMBER) { + WARN(1, "MIPS errata id:%d not in kernel errata list\n", + alt->patch_id); + continue; + } + + tmp =3D (1U << alt->patch_id); + if (cpu_req_errata && tmp) { + mutex_lock(&text_mutex); + patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt), + alt->alt_len); + mutex_unlock(&text_mutex); + } + } +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/= alternative.h index 3c2b59b25017929df92b4e6741ac1a9308bfec54..bc3ada8190a9e7dc7d904aeb317= 4c78329e4d8d7 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -48,6 +48,9 @@ struct alt_entry { void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *en= d, unsigned long archid, unsigned long impid, unsigned int stage); +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *e= nd, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 0b749e7102162477432f7cf9a34768fbdf2e8cc7..80bd52363c68690f33bfd54e0cc= 40399cd60b57b 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -14,6 +14,7 @@ #include #include #include +#include =20 #define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append, \ swap_append, r, p, n) \ @@ -438,7 +439,7 @@ static __always_inline void __cmpwait(volatile void *pt= r, return; =20 no_zawrs: - asm volatile(RISCV_PAUSE : : : "memory"); + ALT_RISCV_PAUSE(); } =20 #define __cmpwait_relaxed(ptr, val) \ diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 6e426ed7919a4acd997b60b723c0d5cfddb4cff6..618dee38d8d1347711fd46a459b= fc8d2cb7bf42b 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -5,7 +5,6 @@ #ifndef ASM_ERRATA_LIST_H #define ASM_ERRATA_LIST_H =20 -#include #include #include #include @@ -29,6 +28,11 @@ #define ERRATA_THEAD_NUMBER 3 #endif =20 +#ifdef CONFIG_ERRATA_MIPS +#define ERRATA_MIPS_P8700_PAUSE_OPCODE 0 +#define ERRATA_MIPS_NUMBER 1 +#endif + #ifdef __ASSEMBLY__ =20 #define ALT_INSN_FAULT(x) \ @@ -59,6 +63,17 @@ asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIV= E_VENDOR_ID, \ ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ : : "r" (addr), "r" (asid) : "memory") =20 +#define ALT_RISCV_PAUSE() \ +asm(ALTERNATIVE( \ + RISCV_PAUSE, /* Original RISC=E2=80=91V pause insn */ \ + ".4byte 0x00501013", /* Replacement for MIPS P8700 */ \ + MIPS_VENDOR_ID, /* Vendor ID to match */ \ + ERRATA_MIPS_P8700_PAUSE_OPCODE, /* patch_id */ \ + CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE) \ + : /* no outputs */ \ + : /* no inputs */ \ + : "memory") + /* * _val is marked as "will be overwritten", so need to set it to 0 * in the default case. diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/a= sm/vdso/processor.h index 8f383f05a290f123d941226b5dd975381d7d8536..8f749552ecfe6220bbc35f1c467= 7c6de8f7abdec 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -5,6 +5,8 @@ #ifndef __ASSEMBLY__ =20 #include + +#include #include =20 static inline void cpu_relax(void) @@ -19,7 +21,7 @@ static inline void cpu_relax(void) * Reduce instruction retirement. * This assumes the PC changes. */ - __asm__ __volatile__ (RISCV_PAUSE); + ALT_RISCV_PAUSE(); barrier(); } =20 diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index a5150cdf34d87f01baf6d3ef843bc2d6d8d54095..3b09874d7a6dfb8f8aa45b0be41= c20711d539e78 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -9,5 +9,6 @@ #define MICROCHIP_VENDOR_ID 0x029 #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 +#define MIPS_VENDOR_ID 0x722 =20 #endif diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 7eb3cb1215c62130c63a72fc650cddff6bae62af..7642704c7f1841f67fc23738063= f22b4ecf58194 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -47,6 +47,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufactu= rer_info_t *cpu_mfr_info cpu_mfr_info->patch_func =3D andes_errata_patch_func; break; #endif +#ifdef CONFIG_ERRATA_MIPS + case MIPS_VENDOR_ID: + cpu_mfr_info->patch_func =3D mips_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: cpu_mfr_info->patch_func =3D sifive_errata_patch_func; diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 75656afa2d6be8ca5f2c4711455567c7f8fc0b97..b18373ed23d65df0dc828246269= e9039bb0b0c6b 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -15,6 +15,8 @@ #include #include #include +#include + #include =20 .section .irqentry.text, "ax" diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 8d0374d7ce8ed72320f58e4cea212d0e2bce8fd4..7ee95ebadc258a3a46e59698cd1= 43266f6797a0c 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -33,6 +33,7 @@ #include #include #include +#include =20 #include "../kernel/head.h" =20 --=20 2.34.1