From nobody Wed Oct 8 19:21:33 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91D5B1DDC1E for ; Wed, 25 Jun 2025 04:56:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750827407; cv=none; b=AfxiuG2TSs+cL5s/bazKzS7e+jdhkJ46WuFs2IT3gWjKexy12oSMRFOAvDuj0SaP+dB0brfRi8or05lnswwCaf+dN5Lyq9my7RzYPqrcMItjjb4HfqgDOv09o6JnZ7AiR7WyCWZJl+MVdpj6W897InFWHKsfepDpnzW/O93ZrBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750827407; c=relaxed/simple; bh=e/mJTOaSWA2P1JapKy8sNOWJL14LCqY1jBMNxyjcl4o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=R1RCfNAwTOwluEo1/cekpx5LmblSvQqtc9lZbkfNtPoM5+fcMMMaNekRWeqXYw1hmTNgQgjJJ+oVJ/RfDx28dlAchIjpmhDdS6BQHg4iJuVf3uVqaBy44CCI1+CUGG/djGzJnHwgD9oWVHhKfaT+yumCDYGf5dqe6Q/5y7Cso7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=lcKluhHs; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="lcKluhHs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750827405; x=1782363405; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=e/mJTOaSWA2P1JapKy8sNOWJL14LCqY1jBMNxyjcl4o=; b=lcKluhHsxBhXnZ8ae9c0XAHGpORG9qxm2nGh54Sb063GGA7vSm8NsPI/ NenwnY1MWkLQz4rBlHvE1qJUbXvDkLmk/3uMKR/eqHkpCXKybTLVj5ULL CZxfz/d673omS3MN3dzK9p6V7lUHT2WsldEmUy850DIP/FzfjlcfKNDiX buir083JJjMrE1K5D4QcCyfC+pKvTeDVOhUHJevwuch7VIfX2tCXOVJXk RrcsZfrwwqa/hrf5Aj/O2bAv3LIMpQ0fqSuf5bCWg2dC+AUgnb5RrAR30 umd3lnCIUQs8mJ5D6gVsQhTR+jCLNTApo5rXzZn9BXArODzWXrOulWJOF w==; X-CSE-ConnectionGUID: AhZgIOJERfil50n8LIfntw== X-CSE-MsgGUID: Ottw10F8RHGo9SV422wKFg== X-IronPort-AV: E=Sophos;i="6.16,263,1744095600"; d="scan'208";a="42713913" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 21:56:37 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 21:56:25 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 21:56:19 -0700 From: Dharma Balasubiramani Date: Wed, 25 Jun 2025 10:26:09 +0530 Subject: [PATCH v5 1/4] drm/bridge: microchip-lvds: Remove unused drm_panel and redundant port node lookup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250625-microchip-lvds-v5-1-624cf72b2651@microchip.com> References: <20250625-microchip-lvds-v5-0-624cf72b2651@microchip.com> In-Reply-To: <20250625-microchip-lvds-v5-0-624cf72b2651@microchip.com> To: Manikandan Muralidharan , Andrzej Hajda , Neil Armstrong , "Robert Foss" , Laurent Pinchart , Jonas Karlman , "Jernej Skrabec" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , "Dharma Balasubiramani" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750827371; l=1861; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=e/mJTOaSWA2P1JapKy8sNOWJL14LCqY1jBMNxyjcl4o=; b=t1+npYydtMChl3XcRSzWZulvNLHRGo1f5cRnLqjyWS/apXPU1mSdxu508JLvCOp8TEYIak2TA IaaxLS0qeGBAoz+yR9lz9vIk94RFDhek0g3J+Sy/hVRu5+KBvT7ktbQ X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= Drop the unused drm_panel field from the mchp_lvds structure, and remove the unnecessary port device node lookup, as devm_drm_of_get_bridge() already performs the required checks internally. Signed-off-by: Dharma Balasubiramani Reviewed-by: Maxime Ripard --- drivers/gpu/drm/bridge/microchip-lvds.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/brid= ge/microchip-lvds.c index 9f4ff82bc6b4..06d4169a2d8f 100644 --- a/drivers/gpu/drm/bridge/microchip-lvds.c +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -56,7 +55,6 @@ struct mchp_lvds { struct device *dev; void __iomem *regs; struct clk *pclk; - struct drm_panel *panel; struct drm_bridge bridge; struct drm_bridge *panel_bridge; }; @@ -151,7 +149,6 @@ static int mchp_lvds_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct mchp_lvds *lvds; - struct device_node *port; int ret; =20 if (!dev->of_node) @@ -173,19 +170,6 @@ static int mchp_lvds_probe(struct platform_device *pde= v) return dev_err_probe(lvds->dev, PTR_ERR(lvds->pclk), "could not get pclk_lvds\n"); =20 - port =3D of_graph_get_remote_node(dev->of_node, 1, 0); - if (!port) { - dev_err(dev, - "can't find port point, please init lvds panel port!\n"); - return -ENODEV; - } - - lvds->panel =3D of_drm_find_panel(port); - of_node_put(port); - - if (IS_ERR(lvds->panel)) - return -EPROBE_DEFER; - lvds->panel_bridge =3D devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); =20 if (IS_ERR(lvds->panel_bridge)) --=20 2.43.0 From nobody Wed Oct 8 19:21:33 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D9301DEFE7 for ; Wed, 25 Jun 2025 04:56:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750827407; cv=none; b=LAdIzV27eL16mdW734FKnFDXLRtsC0/U+TXY3rdOy3uJDTzP4WnHg1Jn2/E5P9jkuYlQhLnqjnUJgKGmJ3ZhiDdSIM88EzoBX9IHbfra37mhyGKLwBRg/5mlOt8cjOpixg5+sFDwb5rOhTBzpley2kIRjUjV2ReeHRKyLRq8Spw= ARC-Message-Signature: i=1; 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Tue, 24 Jun 2025 21:56:31 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 21:56:26 -0700 From: Dharma Balasubiramani Date: Wed, 25 Jun 2025 10:26:10 +0530 Subject: [PATCH v5 2/4] drm/bridge: microchip-lvds: migrate to atomic bridge ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250625-microchip-lvds-v5-2-624cf72b2651@microchip.com> References: <20250625-microchip-lvds-v5-0-624cf72b2651@microchip.com> In-Reply-To: <20250625-microchip-lvds-v5-0-624cf72b2651@microchip.com> To: Manikandan Muralidharan , Andrzej Hajda , Neil Armstrong , "Robert Foss" , Laurent Pinchart , Jonas Karlman , "Jernej Skrabec" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , "Dharma Balasubiramani" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750827371; l=1753; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=3nqEZxV/Y5uq+XwWCf1wbzoSm47wfpCQv/tVq85eryQ=; b=4sdzPsgpBa4OlnMTfa/2tULoTtkrEe19367c/589Yny1LsbWdncOmxsb744sWmSNmJtkcdHMs Kz2M9gtS92sA3b/dmDiT0U19OeSBoOxF4/AQHGY5kC632yNsUV1DnXY X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= Replace legacy .enable and .disable callbacks with their atomic counterparts .atomic_enable and .atomic_disable. Also, add turn off the serialiser inside atomic_disable(). Signed-off-by: Dharma Balasubiramani --- drivers/gpu/drm/bridge/microchip-lvds.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/brid= ge/microchip-lvds.c index 06d4169a2d8f..c40c8717f026 100644 --- a/drivers/gpu/drm/bridge/microchip-lvds.c +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -111,7 +111,8 @@ static int mchp_lvds_attach(struct drm_bridge *bridge, bridge, flags); } =20 -static void mchp_lvds_enable(struct drm_bridge *bridge) +static void mchp_lvds_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) { struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); int ret; @@ -131,18 +132,22 @@ static void mchp_lvds_enable(struct drm_bridge *bridg= e) lvds_serialiser_on(lvds); } =20 -static void mchp_lvds_disable(struct drm_bridge *bridge) +static void mchp_lvds_atomic_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) { struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); =20 + /* Turn off the serialiser */ + lvds_writel(lvds, LVDSC_CR, 0); + pm_runtime_put(lvds->dev); clk_disable_unprepare(lvds->pclk); } =20 static const struct drm_bridge_funcs mchp_lvds_bridge_funcs =3D { .attach =3D mchp_lvds_attach, - .enable =3D mchp_lvds_enable, - .disable =3D mchp_lvds_disable, + .atomic_enable =3D mchp_lvds_atomic_enable, + .atomic_disable =3D mchp_lvds_atomic_disable, }; =20 static int mchp_lvds_probe(struct platform_device *pdev) --=20 2.43.0 From nobody Wed Oct 8 19:21:33 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BC5E1DF991 for ; Wed, 25 Jun 2025 04:56:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750827408; cv=none; b=uWmc/TfLVQ+CUJCiG4sLQqtsdpeUvnF+QB+OUPpFVdENvsCTzALO95JzxiCBKDuzai7i8ruXL/DhzQvVkvpMfnV8P6x/Vg8dGhvcqyTSMcdCgpZ/DyC+HBD5FgllSsPulQJoGRtlbYUDT3NJi2f+bveqia5Jchd8HnQhqGOLlvM= ARC-Message-Signature: i=1; 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Tue, 24 Jun 2025 21:56:37 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 21:56:32 -0700 From: Dharma Balasubiramani Date: Wed, 25 Jun 2025 10:26:11 +0530 Subject: [PATCH v5 3/4] drm/bridge: microchip-lvds: add atomic pre_enable() and post_disable() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250625-microchip-lvds-v5-3-624cf72b2651@microchip.com> References: <20250625-microchip-lvds-v5-0-624cf72b2651@microchip.com> In-Reply-To: <20250625-microchip-lvds-v5-0-624cf72b2651@microchip.com> To: Manikandan Muralidharan , Andrzej Hajda , Neil Armstrong , "Robert Foss" , Laurent Pinchart , Jonas Karlman , "Jernej Skrabec" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , "Dharma Balasubiramani" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750827371; l=2425; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=QE4zUYyP981F+5VE7+ZTFWVBH1tBQt/2P/4OLcHIcbw=; b=sQHGhpQdgAwF6+teRgSAuveZIlU9LLriIJHN6qLdE5xtUivcSM7MUiBjbL7qP4b03sWHlXvuP rZ8nQFzp4m2C4dfmzTTjezKPhGyZ8Ye+kkuTnDm6CSiMAwwPFJrOcke X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= pm_runtime_get_sync() and clk_prepare_enable() must be outside the atomic context, hence move the sleepable operations accordingly. - atomic_pre_enable() handles pm_runtime and clock preparation - atomic_enable() enables the serializer based on panel format - atomic_disable() turns off the serializer - atomic_post_disable() disables clock and releases runtime PM Signed-off-by: Dharma Balasubiramani --- drivers/gpu/drm/bridge/microchip-lvds.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/brid= ge/microchip-lvds.c index c40c8717f026..b1800f78008c 100644 --- a/drivers/gpu/drm/bridge/microchip-lvds.c +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -111,8 +111,8 @@ static int mchp_lvds_attach(struct drm_bridge *bridge, bridge, flags); } =20 -static void mchp_lvds_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) +static void mchp_lvds_atomic_pre_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) { struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); int ret; @@ -128,7 +128,12 @@ static void mchp_lvds_atomic_enable(struct drm_bridge = *bridge, dev_err(lvds->dev, "failed to get pm runtime: %d\n", ret); return; } +} =20 +static void mchp_lvds_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); lvds_serialiser_on(lvds); } =20 @@ -139,6 +144,12 @@ static void mchp_lvds_atomic_disable(struct drm_bridge= *bridge, =20 /* Turn off the serialiser */ lvds_writel(lvds, LVDSC_CR, 0); +} + +static void mchp_lvds_atomic_post_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); =20 pm_runtime_put(lvds->dev); clk_disable_unprepare(lvds->pclk); @@ -146,8 +157,10 @@ static void mchp_lvds_atomic_disable(struct drm_bridge= *bridge, =20 static const struct drm_bridge_funcs mchp_lvds_bridge_funcs =3D { .attach =3D mchp_lvds_attach, + .atomic_pre_enable =3D mchp_lvds_atomic_pre_enable, .atomic_enable =3D mchp_lvds_atomic_enable, .atomic_disable =3D mchp_lvds_atomic_disable, + .atomic_post_disable =3D mchp_lvds_atomic_post_disable, }; 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Tue, 24 Jun 2025 21:56:38 -0700 From: Dharma Balasubiramani Date: Wed, 25 Jun 2025 10:26:12 +0530 Subject: [PATCH v5 4/4] drm/bridge: microchip-lvds: fix bus format mismatch with VESA displays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250625-microchip-lvds-v5-4-624cf72b2651@microchip.com> References: <20250625-microchip-lvds-v5-0-624cf72b2651@microchip.com> In-Reply-To: <20250625-microchip-lvds-v5-0-624cf72b2651@microchip.com> To: Manikandan Muralidharan , Andrzej Hajda , Neil Armstrong , "Robert Foss" , Laurent Pinchart , Jonas Karlman , "Jernej Skrabec" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , "Dharma Balasubiramani" , Sandeep Sheriker M X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750827371; l=3511; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=XPdN3yNq+4xxWHJZCxZu1TvKWFL4HUSh9KffafY4s5Y=; b=Kd/PKU2kq2u+h6bfBPW48z/fB9KPLwGHGAtZUwzVWHuwI2Y+7FZpeSjWMcqHg77TRCJ/54cny PAPvOsXD9h0Dsz6E8J+XP6slZt7jhO8JijdinWAIqlU6Spa2DohOst2 X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= The LVDS controller was hardcoded to JEIDA mapping, which leads to distorted output on panels expecting VESA mapping. Update the driver to dynamically select the appropriate mapping and pixel size based on the panel's advertised media bus format. This ensures compatibility with both JEIDA and VESA displays. Signed-off-by: Sandeep Sheriker M Signed-off-by: Dharma Balasubiramani Reviewed-by: Maxime Ripard --- drivers/gpu/drm/bridge/microchip-lvds.c | 38 +++++++++++++++++++++++++++--= ---- 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/brid= ge/microchip-lvds.c index b1800f78008c..29d18ec00883 100644 --- a/drivers/gpu/drm/bridge/microchip-lvds.c +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -40,9 +41,11 @@ =20 /* Bitfields in LVDSC_CFGR (Configuration Register) */ #define LVDSC_CFGR_PIXSIZE_24BITS 0 +#define LVDSC_CFGR_PIXSIZE_18BITS BIT(0) #define LVDSC_CFGR_DEN_POL_HIGH 0 #define LVDSC_CFGR_DC_UNBALANCED 0 #define LVDSC_CFGR_MAPPING_JEIDA BIT(6) +#define LVDSC_CFGR_MAPPING_VESA 0 =20 /*Bitfields in LVDSC_SR */ #define LVDSC_SR_CS BIT(0) @@ -74,9 +77,10 @@ static inline void lvds_writel(struct mchp_lvds *lvds, u= 32 offset, u32 val) writel_relaxed(val, lvds->regs + offset); } =20 -static void lvds_serialiser_on(struct mchp_lvds *lvds) +static void lvds_serialiser_on(struct mchp_lvds *lvds, u32 bus_format) { unsigned long timeout =3D jiffies + msecs_to_jiffies(LVDS_POLL_TIMEOUT_MS= ); + u8 map, pix_size; =20 /* The LVDSC registers can only be written if WPEN is cleared */ lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD & @@ -91,11 +95,24 @@ static void lvds_serialiser_on(struct mchp_lvds *lvds) usleep_range(1000, 2000); } =20 + switch (bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + map =3D LVDSC_CFGR_MAPPING_JEIDA; + pix_size =3D LVDSC_CFGR_PIXSIZE_18BITS; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + map =3D LVDSC_CFGR_MAPPING_VESA; + pix_size =3D LVDSC_CFGR_PIXSIZE_24BITS; + break; + default: + map =3D LVDSC_CFGR_MAPPING_JEIDA; + pix_size =3D LVDSC_CFGR_PIXSIZE_24BITS; + break; + } + /* Configure the LVDSC */ - lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA | - LVDSC_CFGR_DC_UNBALANCED | - LVDSC_CFGR_DEN_POL_HIGH | - LVDSC_CFGR_PIXSIZE_24BITS)); + lvds_writel(lvds, LVDSC_CFGR, map | LVDSC_CFGR_DC_UNBALANCED | + LVDSC_CFGR_DEN_POL_HIGH | pix_size); =20 /* Enable the LVDS serializer */ lvds_writel(lvds, LVDSC_CR, LVDSC_CR_SER_EN); @@ -134,7 +151,16 @@ static void mchp_lvds_atomic_enable(struct drm_bridge = *bridge, struct drm_atomic_state *state) { struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); - lvds_serialiser_on(lvds); + struct drm_connector *connector; + + /* default to jeida-24 */ + u32 bus_format =3D MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA; + + connector =3D drm_atomic_get_new_connector_for_encoder(state, bridge->enc= oder); + if (connector && connector->display_info.num_bus_formats) + bus_format =3D connector->display_info.bus_formats[0]; + + lvds_serialiser_on(lvds, bus_format); } =20 static void mchp_lvds_atomic_disable(struct drm_bridge *bridge, --=20 2.43.0