From nobody Sat Feb 7 07:31:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28DF82ECE88; Wed, 25 Jun 2025 11:26:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750850764; cv=none; b=mSZAYzfce2S6J8LEXpJFKJDXz/W5Y7luZLxqB/zvF92/1Y+Bubkzm3TtMXt+POOFl2MRct0QQUsK3i2bFb+60CyImi0i0Eyg9sn9ntjbG25a6IjpFFIYjCQLCHgWWELLzpLNZojcTraQy0WNy0sVPHNiOjO0QUYkVBciaG7gnQg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750850764; c=relaxed/simple; bh=ffkxZH/7L4xrwhzE4HLTZSuTIJi+LZUlSy7jJp6bhoA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KJY6QROcwCTbaoHl6lOKslXnfbUJAtJE8o3Bhax59LSX17VxctZzBxI5o9rJSQXFDkVuMnl5YGtdMAinZtGMG1aeftlHmUWtGbQ8oaLlnlFxcXtCB9wt+YJxD+uvI9j88mzt9MYEKpeOaCBkriA1drd/5NbKbNRr1BtOMc/nC+Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nFxKT6Wa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nFxKT6Wa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BFEDAC4CEEE; Wed, 25 Jun 2025 11:26:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750850764; bh=ffkxZH/7L4xrwhzE4HLTZSuTIJi+LZUlSy7jJp6bhoA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nFxKT6WaBkHebCsc+TE9IVZAf/XyB/GM21+hrjZ1jLLc+DmkPIKPHzHJLuYiAIKKm 751lV/Wz32W+gvCI2waq2DkEmxOpLVssIGY5LAgCSYyrWME6IuFLjBIysSOlAg83jI MyKN78w0MWEcNtvKbXyFg935rq9jy4gqPeRjx/UsXnhU2MM9AX+Rj44XRxN9q+s/q7 baPDfrPMD1Hv/r8Wpqz65TNIlX7yS30cetJN6kNlRrVO1AswktMMCy5+X43N9eBeLn fAvxM/bmaqX2QGzcESAFtZdr1zKuf+0UeeTPj6KSDQhJHpvpdjhF1obiyvDZ0LE/Gq h8aC9CUPrGxIw== From: Mark Brown Date: Wed, 25 Jun 2025 11:48:12 +0100 Subject: [PATCH v6 21/28] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-kvm-arm64-sme-v6-21-114cff4ffe04@kernel.org> References: <20250625-kvm-arm64-sme-v6-0-114cff4ffe04@kernel.org> In-Reply-To: <20250625-kvm-arm64-sme-v6-0-114cff4ffe04@kernel.org> To: Marc Zyngier , Oliver Upton , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan Cc: Dave Martin , Fuad Tabba , Mark Rutland , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-08c49 X-Developer-Signature: v=1; a=openpgp-sha256; l=3596; i=broonie@kernel.org; h=from:subject:message-id; bh=ffkxZH/7L4xrwhzE4HLTZSuTIJi+LZUlSy7jJp6bhoA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoW9x1S6U9Djc0/YcgJMo+NNYP9tRdlyK6yyzk5 F6pPlNM2mOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaFvcdQAKCRAk1otyXVSH 0PbsCACEEN3PHl6o6oLjPnOVbidwRs2LvB4LuiZ1evd0IcPQ9VNBu2TcFFhLhLu3twEFqzDxOKb EFm6GLgJg0YwhKMc+MB6kUV7K5j5nIlbPQyHWw3R395mmNiYEa4QyCuRahQ+b0dKjSnvzjVDv3d A5wGNZNMweCAKO44qC1OVUr0BYNyl4Cne5lPLqg3P8xt3AZuGoyjw4QnhNjIxNdhnfHC4qx7dxx IKBz43iTNq5B0i6veWRRGG/YWQrdoc17wUGTf6Dr+2dK8CKk3nSkhkihBAVW8UYrxNXzNG+tcw6 ko9GrCnHKjSvVXuEypfhMKpdN/eP5aXsXnu1lXLu0CwoBCrI X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Writes to the physical SVCR.SM and SVCR.ZA change the state of PSTATE.SM and PSTATE.ZA, causing other floating point state to reset. Emulate this behaviour for writes done via the KVM userspace ABI. Setting PSTATE.ZA to 1 causes ZA and ZT0 to be reset to 0, these are stored in sme_state. Setting PSTATE.ZA to 0 causes ZA and ZT0 to become inaccesible so no reset is needed. Any change in PSTATE.SM causes the V, Z, P, FFR and FPMR registers to be reset to 0 and FPSR to be reset to 0x800009f. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 24 ++++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 29 ++++++++++++++++++++++++++++- 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 5ce9e06324b5..431e5c0ce119 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1123,6 +1123,30 @@ struct kvm_vcpu_arch { =20 #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.max_= vl[ARM64_VEC_SVE]) =20 +#define vcpu_sme_state(vcpu) (kern_hyp_va((vcpu)->arch.sme_state)) + +#define sme_state_size_from_vl(vl, sme2) ({ \ + size_t __size_ret; \ + unsigned int __vq; \ + \ + if (WARN_ON(!sve_vl_valid(vl))) { \ + __size_ret =3D 0; \ + } else { \ + __vq =3D sve_vq_from_vl(vl); \ + __size_ret =3D ZA_SIG_REGS_SIZE(__vq); \ + if (sme2) \ + __size_ret +=3D ZT_SIG_REG_SIZE; \ + } \ + \ + __size_ret; \ +}) + +#define vcpu_sme_state_size(vcpu) ({ \ + unsigned long __vl; \ + __vl =3D (vcpu)->arch.max_vl[ARM64_VEC_SME]; \ + sme_state_size_from_vl(__vl, vcpu_has_sme2(vcpu)); \ +}) + /* * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the * memory backed version of a register, and not the one most recently diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1fee8e534615..edc61a53ba64 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -806,6 +806,33 @@ static bool access_smidr(struct kvm_vcpu *vcpu, return true; } =20 +static int set_svcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + u64 val) +{ + u64 old =3D __vcpu_sys_reg(vcpu, rd->reg); + + if (val & SVCR_RES0) + return -EINVAL; + + if ((val & SVCR_ZA) && !(old & SVCR_ZA) && vcpu->arch.sme_state) + memset(vcpu->arch.sme_state, 0, vcpu_sme_state_size(vcpu)); + + if ((val & SVCR_SM) !=3D (old & SVCR_SM)) { + memset(vcpu->arch.ctxt.fp_regs.vregs, 0, + sizeof(vcpu->arch.ctxt.fp_regs.vregs)); + + if (vcpu->arch.sve_state) + memset(vcpu->arch.sve_state, 0, + vcpu_sve_state_size(vcpu)); + + __vcpu_assign_sys_reg(vcpu, FPMR, 0); + vcpu->arch.ctxt.fp_regs.fpsr =3D 0x800009f; + } + + __vcpu_assign_sys_reg(vcpu, rd->reg, val); + return 0; +} + static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -3175,7 +3202,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { CTR_EL0_DminLine_MASK | CTR_EL0_L1Ip_MASK | CTR_EL0_IminLine_MASK), - { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility =3D s= me_visibility }, + { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility =3D s= me_visibility, .set_user =3D set_svcr }, { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility =3D f= p8_visibility }, =20 { PMU_SYS_REG(PMCR_EL0), .access =3D access_pmcr, .reset =3D reset_pmcr, --=20 2.39.5