From nobody Wed Oct 8 19:57:29 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F9682D29D5; Wed, 25 Jun 2025 11:25:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750850746; cv=none; b=oZ/xswksR/CBK6W/sbUQgiyZgy5Z2LB+H0rmXzQVH6ZgjQUMXB8v5zjE4SV3jWifPgP+ZBz51sfsFTL54IQopxfA5/q7rnVaxk1WQ+z4mDgPuSa3FUcjMGNdvOYSi9GHytJNiZnhQJS+VjxcoABsW8q8u+UkS/6zkZIXjgMM6k4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750850746; c=relaxed/simple; bh=Itu3gAJKdKTzlEwTcjmKxTBS1TUBvFAB1KWkEO9nXn4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ohwvPbOn836wGZfll/kOXQ7UbOjLBmH3IWe1iX8qzmmpdv3cPvMxmr26b6GpWndnFqhICc0EX51GUN2Q+m/4sFcJ/b2aWA1p/J5u4i2yRg8ndNdNeNxW5ySfXZyHyTqbCTyybrAckmIdXoSWC78pBULs7MYk4lczo6CZdFvnwFo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AsRMatQK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AsRMatQK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87C64C4CEEE; Wed, 25 Jun 2025 11:25:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750850745; bh=Itu3gAJKdKTzlEwTcjmKxTBS1TUBvFAB1KWkEO9nXn4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AsRMatQKCMd5PigxtitybOgkCsthTisYzMjMBhJanZasz54/FB/AX3m+PjanWz1z8 etxc2oDLoEXBt/+c69DksbSW0PplD7AAd50wrzhg+nnRTmGFyzjU+UsUVoYX3DIYQi cWwFRoiasdQDtzogjD+5LCErhgLzESA4/heDdqF9Wu9x8+3VLLO02xKjsUh0bILw5d 7n4dDRS0uhLQYS1jafgnmrTg8LTWwIntzHZqEn/0eo04WaSYIVTZSJ/kT8ywQx0urY yn0acbukIsTOttSp0dWPs+tSTnouB5homHub8ysMrFF4bz0kdIoPlPmTkKZqNyczQP 1FhNmK+3Hd6Ow== From: Mark Brown Date: Wed, 25 Jun 2025 11:48:07 +0100 Subject: [PATCH v6 16/28] KVM: arm64: Support TPIDR2_EL0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250625-kvm-arm64-sme-v6-16-114cff4ffe04@kernel.org> References: <20250625-kvm-arm64-sme-v6-0-114cff4ffe04@kernel.org> In-Reply-To: <20250625-kvm-arm64-sme-v6-0-114cff4ffe04@kernel.org> To: Marc Zyngier , Oliver Upton , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan Cc: Dave Martin , Fuad Tabba , Mark Rutland , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-08c49 X-Developer-Signature: v=1; a=openpgp-sha256; l=3463; i=broonie@kernel.org; h=from:subject:message-id; bh=Itu3gAJKdKTzlEwTcjmKxTBS1TUBvFAB1KWkEO9nXn4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoW9xxTa3/DjL2jDUZfiu5RfSJ4qHwf551F2b6h QafCPh4ggmJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaFvccQAKCRAk1otyXVSH 0IfhB/9EOtPhsqeEiYzU7VP1zfpC6u1EuPPiPOqV277ydgwSrHtgGRRNgejYkf1U5G/km1hOWCn MLRQKYBMNeZ60tb8faGdumq4LWmqn5b3y/ehsxHN2lqpLtYT4pGhrLwKSMEL86MmpXEbLno1W2M rpriMzmsc9bqxggn9a5DUvlrwQjRvzS9AP+Cc0DxINe/9qsEykK1VJa+BrARaunLnU5ghY19Mo0 r2AtQaixnOl6+2hU03I0CfiN+9YVu2nsNJ3W/RB79p2ceuAvYedt1XhYGAwT9qFoVRqiyDkN3GB vcoEGr5rkyojdqf0OAB7Zj9TQAHYz/FLIAnmU/WJOd+gyxAW X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME adds a new thread ID register, TPIDR2_EL0. This is used in userspace for delayed saving of the ZA state but in terms of the architecture is not really connected to SME other than being part of FEAT_SME. It has an independent fine grained trap and the runtime connection with the rest of SME is purely software defined. Expose the register as a system register if the guest supports SME, context switching it along with the other EL0 TPIDRs. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 15 +++++++++++++++ arch/arm64/kvm/sys_regs.c | 3 ++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 14179e1ddb3e..c26099f74648 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -450,6 +450,7 @@ enum vcpu_sysreg { CSSELR_EL1, /* Cache Size Selection Register */ TPIDR_EL0, /* Thread ID, User R/W */ TPIDRRO_EL0, /* Thread ID, User R/O */ + TPIDR2_EL0, /* Thread ID, Register 2 */ TPIDR_EL1, /* Thread ID, Privileged */ CNTKCTL_EL1, /* Timer Control Register (EL1) */ PAR_EL1, /* Physical Address Register */ diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index 223819e95405..efd1e0707f77 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -66,6 +66,17 @@ static inline bool ctxt_has_s1poe(struct kvm_cpu_context= *ctxt) return kvm_has_s1poe(kern_hyp_va(vcpu->kvm)); } =20 +static inline bool ctxt_has_sme(struct kvm_cpu_context *ctxt) +{ + struct kvm_vcpu *vcpu; + + if (!system_supports_sme()) + return false; + + vcpu =3D ctxt_to_vcpu(ctxt); + return kvm_has_sme(kern_hyp_va(vcpu->kvm)); +} + static inline bool ctxt_is_guest(struct kvm_cpu_context *ctxt) { return host_data_ptr(host_ctxt) !=3D ctxt; @@ -105,6 +116,8 @@ static inline void __sysreg_save_user_state(struct kvm_= cpu_context *ctxt) { ctxt_sys_reg(ctxt, TPIDR_EL0) =3D read_sysreg(tpidr_el0); ctxt_sys_reg(ctxt, TPIDRRO_EL0) =3D read_sysreg(tpidrro_el0); + if (ctxt_has_sme(ctxt)) + ctxt_sys_reg(ctxt, TPIDR2_EL0) =3D read_sysreg_s(SYS_TPIDR2_EL0); } =20 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) @@ -174,6 +187,8 @@ static inline void __sysreg_restore_user_state(struct k= vm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); + if (ctxt_has_sme(ctxt)) + write_sysreg_s(ctxt_sys_reg(ctxt, TPIDR2_EL0), SYS_TPIDR2_EL0); } =20 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt, diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 90923edb3355..caa90dae8184 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -3170,7 +3170,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { .visibility =3D s1poe_visibility }, { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, - { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, + { SYS_DESC(SYS_TPIDR2_EL0), NULL, reset_unknown, TPIDR2_EL0, + .visibility =3D sme_visibility}, =20 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, =20 --=20 2.39.5