From nobody Wed Oct 8 21:41:34 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92F0E259CBB; Tue, 24 Jun 2025 22:12:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750803165; cv=none; b=YEeuHrNuvpwAV8QgIZakRgql5GVJLerV7mclqq5jgsqmzYCh34yb8jCGELp1QmtztiyrXB2HgvoAi/WUio+jwLC2ZpNvrbHoOz7SSjTEQ/7NR5gsVyhrWneG/Xp0QUvbjvrOwY/VWwwsYGbabkyhJiAOVB066nQa8c2RaNpvR8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750803165; c=relaxed/simple; bh=fwP6WJajlbF0dFz8/xjQx+4WKNl5as/lo5yVIQOZl0I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IXOZ2YxENz22UF/n8I641aWCk+0z8j8g8R5Z4kxK4EPuhm2g4ZQMyY8yTcMMpkDFRsnZMyrHLu4puuDWlK6h7nPOnO9fxelt8t1c1r21RFWzdPZitiYU6HfP4HKZwdBYw0wNxAdrwzFHYzt/eIthWp0dxnQ7WFB3KlfnbH05X1g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=m0BxnkM8; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="m0BxnkM8" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55OMCVfg1932977; Tue, 24 Jun 2025 17:12:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750803151; bh=XXGnLwf/tFwhXvoFqY+YB6Y5NH9zFpUBSbtdZJ0M63U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=m0BxnkM8LM+4HhzZzajTzUFgpI8hXtNUzfywA98wRIJVa9niUQijywU887GFXeLNR Agl15SoaWyRajy2tprWQ0sdXNjbZms2muPwu3MrVEYu+UznK2xXkGBvV9tVR70q4Ru Wv2H+wO4J77+gHwOpGTYbdsuhyRFrHkMc0kVKJ38= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55OMCUg21942544 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 24 Jun 2025 17:12:30 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 24 Jun 2025 17:12:30 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 24 Jun 2025 17:12:30 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55OMCU9M2248346; Tue, 24 Jun 2025 17:12:30 -0500 From: Judith Mendez To: Judith Mendez , Ulf Hansson , Adrian Hunter , Vignesh Raghavendra CC: Nishanth Menon , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Subject: [PATCH 3/3] arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file Date: Tue, 24 Jun 2025 17:12:30 -0500 Message-ID: <20250624221230.1952291-4-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250624221230.1952291-1-jm@ti.com> References: <20250624221230.1952291-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This moves pinmux child nodes for sdhci0 node from k3-am62x-sk-common to each top level board file. This is needed since we require internal pullups for AM62x SK and not for AM62 LP SK since it has external pullups on DATA 1-7. Internal pulls are required for AM62 SK as per JESD84 spec recommendation to prevent unconnected lines floating. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 25 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am625-sk.dts | 25 +++++++++++++++++++ .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 24 ------------------ 3 files changed, 50 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts= /ti/k3-am62-lp-sk.dts index aafdb90c0eb7..973b145bb244 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -74,6 +74,22 @@ vddshv_sdio: regulator-4 { }; =20 &main_pmx0 { + main_mmc0_pins_default: main-mmc0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (V3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (Y1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (V2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (V1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (W2) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (W1) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (Y2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (W3) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (W4) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (V4) MMC0_DAT7 */ + >; + }; + vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins =3D < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ @@ -144,6 +160,15 @@ exp2: gpio@23 { }; }; =20 +&sdhci0 { + bootph-all; + status =3D "okay"; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mmc0_pins_default>; + disable-wp; +}; + &sdhci1 { vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vddshv_sdio>; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/t= i/k3-am625-sk.dts index 2fbfa3719345..4fc018174470 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -106,6 +106,22 @@ vcc_1v8: regulator-5 { }; =20 &main_pmx0 { + main_mmc0_pins_default: main-mmc0-default-pins { + bootph-all; + pinctrl-single,pins =3D < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + main_rgmii2_pins_default: main-rgmii2-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -195,6 +211,15 @@ exp1: gpio@22 { }; }; =20 +&sdhci0 { + bootph-all; + status =3D "okay"; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mmc0_pins_default>; + disable-wp; +}; + &sdhci1 { vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv>; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index ee8337bfbbfd..13e1d36123d5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -203,22 +203,6 @@ AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) G= PMC0_CSn3.I2C2_SDA */ >; }; =20 - main_mmc0_pins_default: main-mmc0-default-pins { - bootph-all; - pinctrl-single,pins =3D < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ - >; - }; - main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -457,14 +441,6 @@ &main_i2c2 { clock-frequency =3D <400000>; }; =20 -&sdhci0 { - bootph-all; - status =3D "okay"; - non-removable; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&main_mmc0_pins_default>; -}; - &sdhci1 { /* SD/MMC */ bootph-all; --=20 2.49.0