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Tue, 24 Jun 2025 10:30:38 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:a522:16f6:ec97:d332]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4535ead202asm181662565e9.27.2025.06.24.10.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 10:30:37 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 4/6] clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting Date: Tue, 24 Jun 2025 18:30:28 +0100 Message-ID: <20250624173030.472196-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250624173030.472196-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250624173030.472196-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for fixed-factor module clocks that can report their enable status through the module status monitor. Introduce a new clock type, CLK_TYPE_FF_MOD_STATUS, and define the associated structure, rzv2h_ff_mod_status_clk, to manage these clocks. Implement the .is_enabled callback by reading the module status register using monitor index and bit definitions. Provide a helper macro, DEF_FIXED_MOD_STATUS, to simplify the definition of such clocks. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 83 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 22 +++++++++ 2 files changed, 105 insertions(+) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index 11325980379a..a511f34abf18 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -150,6 +150,22 @@ struct ddiv_clk { =20 #define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div) =20 +/** + * struct rzv2h_ff_mod_status_clk - Fixed Factor Module Status Clock + * + * @priv: CPG private data + * @conf: fixed mod configuration + * @fix: fixed factor clock + */ +struct rzv2h_ff_mod_status_clk { + struct rzv2h_cpg_priv *priv; + struct fixed_mod_conf conf; + struct clk_fixed_factor fix; +}; + +#define to_rzv2h_ff_mod_status_clk(_hw) \ + container_of(_hw, struct rzv2h_ff_mod_status_clk, fix.hw) + static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw) { struct pll_clk *pll_clk =3D to_pll(hw); @@ -421,6 +437,70 @@ rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *= core, return clk_hw->clk; } =20 +static int +rzv2h_clk_ff_mod_status_is_enabled(struct clk_hw *hw) +{ + struct rzv2h_ff_mod_status_clk *fix =3D to_rzv2h_ff_mod_status_clk(hw); + struct rzv2h_cpg_priv *priv =3D fix->priv; + u32 offset =3D GET_CLK_MON_OFFSET(fix->conf.mon_index); + u32 bitmask =3D BIT(fix->conf.mon_bit); + u32 val; + + val =3D readl(priv->base + offset); + return !!(val & bitmask); +} + +static struct clk_ops rzv2h_clk_ff_mod_status_ops; + +static struct clk * __init +rzv2h_cpg_fixed_mod_status_clk_register(const struct cpg_core_clk *core, + struct rzv2h_cpg_priv *priv) +{ + struct rzv2h_ff_mod_status_clk *clk_hw_data; + struct clk_init_data init =3D { }; + struct clk_fixed_factor *fix; + const struct clk *parent; + const char *parent_name; + int ret; + + WARN_DEBUG(core->parent >=3D priv->num_core_clks); + parent =3D priv->clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + parent_name =3D __clk_get_name(parent); + parent =3D priv->clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + clk_hw_data =3D devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); + if (!clk_hw_data) + return ERR_PTR(-ENOMEM); + + clk_hw_data->priv =3D priv; + clk_hw_data->conf =3D core->cfg.fixed_mod; + + rzv2h_clk_ff_mod_status_ops =3D clk_fixed_factor_ops; + rzv2h_clk_ff_mod_status_ops.is_enabled =3D rzv2h_clk_ff_mod_status_is_ena= bled; + + init.name =3D core->name; + init.ops =3D &rzv2h_clk_ff_mod_status_ops; + init.flags =3D CLK_SET_RATE_PARENT; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + fix =3D &clk_hw_data->fix; + fix->hw.init =3D &init; + fix->mult =3D core->mult; + fix->div =3D core->div; + + ret =3D devm_clk_hw_register(priv->dev, &clk_hw_data->fix.hw); + if (ret) + return ERR_PTR(ret); + + return clk_hw_data->fix.hw.clk; +} + static struct clk *rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, void *data) @@ -499,6 +579,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *= core, else clk =3D clk_hw->clk; break; + case CLK_TYPE_FF_MOD_STATUS: + clk =3D rzv2h_cpg_fixed_mod_status_clk_register(core, priv); + break; case CLK_TYPE_PLL: clk =3D rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops); break; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 7321b085f937..317c8ee2e2d5 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -93,6 +93,23 @@ struct smuxed { .width =3D (_width), \ }) =20 +/** + * struct fixed_mod_conf - Structure for fixed module configuration + * + * @mon_index: monitor index + * @mon_bit: monitor bit + */ +struct fixed_mod_conf { + u8 mon_index; + u8 mon_bit; +}; + +#define FIXED_MOD_CONF_PACK(_index, _bit) \ + ((struct fixed_mod_conf){ \ + .mon_index =3D (_index), \ + .mon_bit =3D (_bit), \ + }) + #define CPG_SSEL0 (0x300) #define CPG_SSEL1 (0x304) #define CPG_CDDIV0 (0x400) @@ -151,6 +168,7 @@ struct cpg_core_clk { struct ddiv ddiv; struct pll pll; struct smuxed smux; + struct fixed_mod_conf fixed_mod; } cfg; const struct clk_div_table *dtable; const char * const *parent_names; @@ -163,6 +181,7 @@ enum clk_types { /* Generic */ CLK_TYPE_IN, /* External Clock Input */ CLK_TYPE_FF, /* Fixed Factor Clock */ + CLK_TYPE_FF_MOD_STATUS, /* Fixed Factor Clock which can report the status= of module clock */ CLK_TYPE_PLL, CLK_TYPE_DDIV, /* Dynamic Switching Divider */ CLK_TYPE_SMUX, /* Static Mux */ @@ -178,6 +197,9 @@ enum clk_types { DEF_TYPE(_name, _id, CLK_TYPE_IN) #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div =3D _div, .mult =3D _mult) +#define DEF_FIXED_MOD_STATUS(_name, _id, _parent, _mult, _div, _gate) \ + DEF_BASE(_name, _id, CLK_TYPE_FF_MOD_STATUS, _parent, .div =3D _div, \ + .mult =3D _mult, .cfg.fixed_mod =3D _gate) #define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \ .cfg.ddiv =3D _ddiv_packed, \ --=20 2.49.0