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Tue, 24 Jun 2025 10:30:36 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:a522:16f6:ec97:d332]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4535ead202asm181662565e9.27.2025.06.24.10.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 10:30:36 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/6] clk: renesas: r9a09g057: Add support for xspi mux and divider Date: Tue, 24 Jun 2025 18:30:27 +0100 Message-ID: <20250624173030.472196-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250624173030.472196-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250624173030.472196-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and pllcm33_xspi divider to select different clock rates. Add support for both. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/r9a09g057-cpg.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a0= 9g057-cpg.c index da908e820950..39065d63df61 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -16,7 +16,7 @@ =20 enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK =3D R9A09G057_GBETH_1_CLK_PTP_REF_I, + LAST_DT_CORE_CLK =3D R9A09G057_SPI_CLK_SPI, =20 /* External Input Clocks */ CLK_AUDIO_EXTAL, @@ -33,9 +33,14 @@ enum clk_ids { CLK_PLLGPU, =20 /* Internal Core Clocks */ + CLK_PLLCM33_DIV3, CLK_PLLCM33_DIV4, + CLK_PLLCM33_DIV5, CLK_PLLCM33_DIV4_PLLCM33, CLK_PLLCM33_DIV16, + CLK_SMUX2_XSPI_CLK0, + CLK_SMUX2_XSPI_CLK1, + CLK_PLLCM33_XSPI, CLK_PLLCLN_DIV2, CLK_PLLCLN_DIV8, CLK_PLLCLN_DIV16, @@ -78,6 +83,14 @@ static const struct clk_div_table dtable_2_4[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_2_16[] =3D { + {0, 2}, + {1, 4}, + {2, 8}, + {3, 16}, + {0, 0}, +}; + static const struct clk_div_table dtable_2_64[] =3D { {0, 2}, {1, 4}, @@ -99,6 +112,8 @@ static const char * const smux2_gbe0_rxclk[] =3D { ".pll= eth_gbe0", "et0_rxclk" }; static const char * const smux2_gbe0_txclk[] =3D { ".plleth_gbe0", "et0_tx= clk" }; static const char * const smux2_gbe1_rxclk[] =3D { ".plleth_gbe1", "et1_rx= clk" }; static const char * const smux2_gbe1_txclk[] =3D { ".plleth_gbe1", "et1_tx= clk" }; +static const char * const smux2_xspi_clk0[] =3D { ".pllcm33_div3", ".pllcm= 33_div4" }; +static const char * const smux2_xspi_clk1[] =3D { ".smux2_xspi_clk0", ".pl= lcm33_div5" }; =20 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst =3D { /* External Clock Inputs */ @@ -116,10 +131,16 @@ static const struct cpg_core_clk r9a09g057_core_clks[= ] __initconst =3D { DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), =20 /* Internal Core Clocks */ + DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3), DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), + DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xs= pi_clk0), + DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xs= pi_clk1), + DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_= DIVCTL3, + dtable_2_16), =20 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), --=20 2.49.0