From nobody Wed Oct 8 22:35:11 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 656D72E765E; Tue, 24 Jun 2025 14:33:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750775639; cv=none; b=hNJmF2+KudlO/3sPV3nEBOJD83eyAp0zU1gMmAjbJj5IL116Oi/fhGF2+LJO82TIWVHjM86lYMvfAAEoxTXmrc4jkLRvuxZhIU9fABkeMK3l8EEJuffPVjbUCxitpHWKCfndk9s5yHEbTnG9dZSkhIXakq15WcUT/s1F3DZU1Yo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750775639; c=relaxed/simple; bh=ji64ktf1VyZ4FuTl9hGewtqBHAwEVicidJKzYxHMYgw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CE6JZ71wVSEo4/wwI4QZToBTu5rSk3fiBbK5e30IJuBwZAy7cFxON8JzQ+Qz0nevZJmw9hIGFQzMkr2bge/cL9ERR7RhoN2hkeFAMAWPATafh3E2oxyDyCK0sFePRyPRDUWHmqxDAkiBVbPpKVi9khOHQ579UUFkY4Q1EjwceXk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=iG/j/fWD; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="iG/j/fWD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750775634; bh=ji64ktf1VyZ4FuTl9hGewtqBHAwEVicidJKzYxHMYgw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iG/j/fWDuQnrGtCdqdajU5N23Xogk0f72t5xmDnd8J2EanHay80UdFDtrNC1K7P+U mlMmeH+1Fo07QM2guP5ntqvGYW8RXSMvPrlGhzpoBAqhf3o4gctaCNkFZoNWd5tCIl G4s4UjWDBc7+7NL4B7hL6EVjh/tvzyrQrLy0AcunKP58iIcr6JXhhv0EQbHQYf7Mr1 1ArzTYPD+BOOPz/WEZbkDEJwjLfldD823cRLtJZjaggb38aI0B+pxuz5kWuDbPQYcS L5DtikxicS0QVGkdyEyujfY94jST5XaGzBewyBOEgjnMde4S3Lnv8nc4rEcenFGaZb 5V1QZ84DIl2Bg== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:d2c7:2075:2c3c:38e5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 6C0A617E1090; Tue, 24 Jun 2025 16:33:53 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao Subject: [PATCH v2 18/29] clk: mediatek: Add MT8196 adsp clock support Date: Tue, 24 Jun 2025 16:32:09 +0200 Message-Id: <20250624143220.244549-19-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250624143220.244549-1-laura.nao@collabora.com> References: <20250624143220.244549-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the MT8196 adsp clock controller, which provides clock gate control for Audio DSP. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao --- drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8196-adsp.c | 193 +++++++++++++++++++++++++ 3 files changed, 201 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8196-adsp.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index cd12e7ff3e12..d4c97f64b42a 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -1068,6 +1068,13 @@ config COMMON_CLK_MT8196 help This driver supports MediaTek MT8196 basic clocks. =20 +config COMMON_CLK_MT8196_ADSP + tristate "Clock driver for MediaTek MT8196 adsp" + depends on COMMON_CLK_MT8196 + default m + help + This driver supports MediaTek MT8196 adsp clocks + config COMMON_CLK_MT8196_PEXTPSYS tristate "Clock driver for MediaTek MT8196 pextpsys" depends on COMMON_CLK_MT8196 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 21e768f67283..6a34ee2f7855 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -163,6 +163,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) +=3D clk-mt8195-= wpe.o obj-$(CONFIG_COMMON_CLK_MT8196) +=3D clk-mt8196-apmixedsys.o clk-mt8196-to= pckgen.o \ clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \ clk-mt8196-peri_ao.o +obj-$(CONFIG_COMMON_CLK_MT8196_ADSP) +=3D clk-mt8196-adsp.o obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) +=3D clk-mt8196-pextp.o obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) +=3D clk-mt8196-ufs_ao.o obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365-apmixedsys.o clk-mt8365.o diff --git a/drivers/clk/mediatek/clk-mt8196-adsp.c b/drivers/clk/mediatek/= clk-mt8196-adsp.c new file mode 100644 index 000000000000..2c1852b77aa8 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8196-adsp.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Guangjie Song + * Copyright (c) 2025 Collabora Ltd. + * Laura Nao + */ +#include +#include +#include +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs afe0_cg_regs =3D { + .set_ofs =3D 0x0, + .clr_ofs =3D 0x0, + .sta_ofs =3D 0x0, +}; + +static const struct mtk_gate_regs afe1_cg_regs =3D { + .set_ofs =3D 0x10, + .clr_ofs =3D 0x10, + .sta_ofs =3D 0x10, +}; + +static const struct mtk_gate_regs afe2_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x4, +}; + +static const struct mtk_gate_regs afe3_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x8, +}; + +static const struct mtk_gate_regs afe4_cg_regs =3D { + .set_ofs =3D 0xc, + .clr_ofs =3D 0xc, + .sta_ofs =3D 0xc, +}; + +#define GATE_AFE0(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &afe0_cg_regs, \ + .shift =3D _shift, \ + .flags =3D CLK_OPS_PARENT_ENABLE | \ + CLK_IGNORE_UNUSED, \ + .ops =3D &mtk_clk_gate_ops_no_setclr, \ + } + +#define GATE_AFE1(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &afe1_cg_regs, \ + .shift =3D _shift, \ + .flags =3D CLK_OPS_PARENT_ENABLE | \ + CLK_IGNORE_UNUSED, \ + .ops =3D &mtk_clk_gate_ops_no_setclr, \ + } + +#define GATE_AFE2(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &afe2_cg_regs, \ + .shift =3D _shift, \ + .flags =3D CLK_OPS_PARENT_ENABLE | \ + CLK_IGNORE_UNUSED, \ + .ops =3D &mtk_clk_gate_ops_no_setclr, \ + } + +#define GATE_AFE3(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &afe3_cg_regs, \ + .shift =3D _shift, \ + .flags =3D CLK_OPS_PARENT_ENABLE | \ + CLK_IGNORE_UNUSED, \ + .ops =3D &mtk_clk_gate_ops_no_setclr, \ + } + +#define GATE_AFE4(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &afe4_cg_regs, \ + .shift =3D _shift, \ + .flags =3D CLK_OPS_PARENT_ENABLE | \ + CLK_IGNORE_UNUSED, \ + .ops =3D &mtk_clk_gate_ops_no_setclr, \ + } + +static const struct mtk_gate afe_clks[] =3D { + /* AFE0 */ + GATE_AFE0(CLK_AFE_PCM1, "afe_pcm1", "clk26m", 13), + GATE_AFE0(CLK_AFE_PCM0, "afe_pcm0", "clk26m", 14), + GATE_AFE0(CLK_AFE_CM2, "afe_cm2", "clk26m", 16), + GATE_AFE0(CLK_AFE_CM1, "afe_cm1", "clk26m", 17), + GATE_AFE0(CLK_AFE_CM0, "afe_cm0", "clk26m", 18), + GATE_AFE0(CLK_AFE_STF, "afe_stf", "clk26m", 19), + GATE_AFE0(CLK_AFE_HW_GAIN23, "afe_hw_gain23", "clk26m", 20), + GATE_AFE0(CLK_AFE_HW_GAIN01, "afe_hw_gain01", "clk26m", 21), + GATE_AFE0(CLK_AFE_FM_I2S, "afe_fm_i2s", "clk26m", 24), + GATE_AFE0(CLK_AFE_MTKAIFV4, "afe_mtkaifv4", "clk26m", 25), + /* AFE1 */ + GATE_AFE1(CLK_AFE_AUDIO_HOPPING, "afe_audio_hopping_ck", "clk26m", 0), + GATE_AFE1(CLK_AFE_AUDIO_F26M, "afe_audio_f26m_ck", "clk26m", 1), + GATE_AFE1(CLK_AFE_APLL1, "afe_apll1_ck", "aud_1", 2), + GATE_AFE1(CLK_AFE_APLL2, "afe_apll2_ck", "aud_2", 3), + GATE_AFE1(CLK_AFE_H208M, "afe_h208m_ck", "vlp_audio_h", 4), + GATE_AFE1(CLK_AFE_APLL_TUNER2, "afe_apll_tuner2", "vlp_aud_engen2", 12), + GATE_AFE1(CLK_AFE_APLL_TUNER1, "afe_apll_tuner1", "vlp_aud_engen1", 13), + /* AFE2 */ + GATE_AFE2(CLK_AFE_UL2_ADC_HIRES_TML, "afe_ul2_aht", "vlp_audio_h", 12), + GATE_AFE2(CLK_AFE_UL2_ADC_HIRES, "afe_ul2_adc_hires", "vlp_audio_h", 13), + GATE_AFE2(CLK_AFE_UL2_TML, "afe_ul2_tml", "clk26m", 14), + GATE_AFE2(CLK_AFE_UL2_ADC, "afe_ul2_adc", "clk26m", 15), + GATE_AFE2(CLK_AFE_UL1_ADC_HIRES_TML, "afe_ul1_aht", "vlp_audio_h", 16), + GATE_AFE2(CLK_AFE_UL1_ADC_HIRES, "afe_ul1_adc_hires", "vlp_audio_h", 17), + GATE_AFE2(CLK_AFE_UL1_TML, "afe_ul1_tml", "clk26m", 18), + GATE_AFE2(CLK_AFE_UL1_ADC, "afe_ul1_adc", "clk26m", 19), + GATE_AFE2(CLK_AFE_UL0_ADC_HIRES_TML, "afe_ul0_aht", "vlp_audio_h", 20), + GATE_AFE2(CLK_AFE_UL0_ADC_HIRES, "afe_ul0_adc_hires", "vlp_audio_h", 21), + GATE_AFE2(CLK_AFE_UL0_TML, "afe_ul0_tml", "clk26m", 22), + GATE_AFE2(CLK_AFE_UL0_ADC, "afe_ul0_adc", "clk26m", 23), + /* AFE3 */ + GATE_AFE3(CLK_AFE_ETDM_IN6, "afe_etdm_in6", "clk26m", 7), + GATE_AFE3(CLK_AFE_ETDM_IN5, "afe_etdm_in5", "clk26m", 8), + GATE_AFE3(CLK_AFE_ETDM_IN4, "afe_etdm_in4", "clk26m", 9), + GATE_AFE3(CLK_AFE_ETDM_IN3, "afe_etdm_in3", "clk26m", 10), + GATE_AFE3(CLK_AFE_ETDM_IN2, "afe_etdm_in2", "clk26m", 11), + GATE_AFE3(CLK_AFE_ETDM_IN1, "afe_etdm_in1", "clk26m", 12), + GATE_AFE3(CLK_AFE_ETDM_IN0, "afe_etdm_in0", "clk26m", 13), + GATE_AFE3(CLK_AFE_ETDM_OUT6, "afe_etdm_out6", "clk26m", 15), + GATE_AFE3(CLK_AFE_ETDM_OUT5, "afe_etdm_out5", "clk26m", 16), + GATE_AFE3(CLK_AFE_ETDM_OUT4, "afe_etdm_out4", "clk26m", 17), + GATE_AFE3(CLK_AFE_ETDM_OUT3, "afe_etdm_out3", "clk26m", 18), + GATE_AFE3(CLK_AFE_ETDM_OUT2, "afe_etdm_out2", "clk26m", 19), + GATE_AFE3(CLK_AFE_ETDM_OUT1, "afe_etdm_out1", "clk26m", 20), + GATE_AFE3(CLK_AFE_ETDM_OUT0, "afe_etdm_out0", "clk26m", 21), + GATE_AFE3(CLK_AFE_TDM_OUT, "afe_tdm_out", "aud_1", 24), + /* AFE4 */ + GATE_AFE4(CLK_AFE_GENERAL15_ASRC, "afe_general15_asrc", "clk26m", 9), + GATE_AFE4(CLK_AFE_GENERAL14_ASRC, "afe_general14_asrc", "clk26m", 10), + GATE_AFE4(CLK_AFE_GENERAL13_ASRC, "afe_general13_asrc", "clk26m", 11), + GATE_AFE4(CLK_AFE_GENERAL12_ASRC, "afe_general12_asrc", "clk26m", 12), + GATE_AFE4(CLK_AFE_GENERAL11_ASRC, "afe_general11_asrc", "clk26m", 13), + GATE_AFE4(CLK_AFE_GENERAL10_ASRC, "afe_general10_asrc", "clk26m", 14), + GATE_AFE4(CLK_AFE_GENERAL9_ASRC, "afe_general9_asrc", "clk26m", 15), + GATE_AFE4(CLK_AFE_GENERAL8_ASRC, "afe_general8_asrc", "clk26m", 16), + GATE_AFE4(CLK_AFE_GENERAL7_ASRC, "afe_general7_asrc", "clk26m", 17), + GATE_AFE4(CLK_AFE_GENERAL6_ASRC, "afe_general6_asrc", "clk26m", 18), + GATE_AFE4(CLK_AFE_GENERAL5_ASRC, "afe_general5_asrc", "clk26m", 19), + GATE_AFE4(CLK_AFE_GENERAL4_ASRC, "afe_general4_asrc", "clk26m", 20), + GATE_AFE4(CLK_AFE_GENERAL3_ASRC, "afe_general3_asrc", "clk26m", 21), + GATE_AFE4(CLK_AFE_GENERAL2_ASRC, "afe_general2_asrc", "clk26m", 22), + GATE_AFE4(CLK_AFE_GENERAL1_ASRC, "afe_general1_asrc", "clk26m", 23), + GATE_AFE4(CLK_AFE_GENERAL0_ASRC, "afe_general0_asrc", "clk26m", 24), + GATE_AFE4(CLK_AFE_CONNSYS_I2S_ASRC, "afe_connsys_i2s_asrc", "clk26m", 25), +}; + +static const struct mtk_clk_desc afe_mcd =3D { + .clks =3D afe_clks, + .num_clks =3D ARRAY_SIZE(afe_clks), + .need_runtime_pm =3D true, +}; + +static const struct of_device_id of_match_clk_mt8196_adsp[] =3D { + { .compatible =3D "mediatek,mt8196-adsp", .data =3D &afe_mcd }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8196_adsp_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8196-adsp", + .of_match_table =3D of_match_clk_mt8196_adsp, + }, +}; +module_platform_driver(clk_mt8196_adsp_drv); + +MODULE_DESCRIPTION("MediaTek MT8196 AudioDSP clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.39.5