From nobody Wed Oct 8 20:55:25 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B9D31E4A9 for ; Tue, 24 Jun 2025 11:32:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750764755; cv=none; b=maqRPVuayOMKmjssicsb8htKzvLL1im6qN4xKJLVECWPzYBHZe80xSEXlFb6HJQpiOLGemk5IG432894VUt4vRT04fS2P6D9tAGtksx7CtJ11qvKaEElY6xX4sdyUrzdjZDqfP8fvntecJx41bDiuv6DV62j9zK0q7X0qa1a9Is= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750764755; c=relaxed/simple; bh=YjsSnZC24Kub1Mxl3I4TTuRSc2vRsTnTW31HJ1TbpB0=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=fvTUAKDPpHocMkSjgULh/Gsw0B6xXnsVv2e5+FDjcwfXj27MjuC9trynqN7AzyytisZ/l7MyGIdPmwhisx+oVQpCHnDUhTdoaF8g9vmE3KoTiI8dafKJdOMGZ0uKQoDuteMf86yH1H9iJt/tGAmmV+YnwIHBXA0ZMW9Mn6blaOE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Gq40pf+S; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Gq40pf+S" X-UUID: e70394c250ee11f0b33aeb1e7f16c2b6-20250624 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=nqHVGMxhDg52YSCi1jgl7ccHJpCWVWC3C9YGgQGOt9A=; b=Gq40pf+SfwLUvv9DiX3g+fwWPt6caPt6bBMiwRseDJBIzc9jWlOz9bZtaP3qfSwo/HlYOLrfzOdc9sfppRN4Y7dC40//bhrcjaosr0sFgNYlKQnY9O+BPRFPTOz+RW6Rg3uPU3gUYV47caj8iH7V9wIRffY53MTAeAmmL4mTA9k=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.2,REQID:a362b9e9-1171-44f7-8900-a212da373129,IP:0,UR L:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-30 X-CID-META: VersionHash:9eb4ff7,CLOUDID:a131955f-2aa0-4c76-8faa-804d844c7164,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0|50,EDM:2,IP:nil ,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES: 1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: e70394c250ee11f0b33aeb1e7f16c2b6-20250624 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 402374836; Tue, 24 Jun 2025 19:32:25 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Tue, 24 Jun 2025 19:32:23 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Tue, 24 Jun 2025 19:32:23 +0800 From: Jason-JH Lin To: Chun-Kuang Hu , AngeloGioacchino Del Regno , David Airlie CC: Philipp Zabel , Daniel Vetter , Matthias Brugger , Jason-JH Lin , Nancy Lin , Singo Chang , Paul-PL Chen , Yongqiang Niu , Zhenxing Qin , Xiandong Wang , Sirius Wang , Xavier Chang , Jarried Lin , Fei Shao , Chen-yu Tsai , , , , Subject: [PATCH v2] drm/mediatek: Add wait_event_timeout when disabling plane Date: Tue, 24 Jun 2025 19:31:41 +0800 Message-ID: <20250624113223.443274-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Our hardware registers are set through GCE, not by the CPU. DRM might assume the hardware is disabled immediately after calling atomic_disable() of drm_plane, but it is only truly disabled after the GCE IRQ is triggered. Additionally, the cursor plane in DRM uses async_commit, so DRM will not wait for vblank and will free the buffer immediately after calling atomic_disable(). To prevent the framebuffer from being freed before the layer disable settings are configured into the hardware, which can cause an IOMMU fault error, a wait_event_timeout has been added to wait for the ddp_cmdq_cb() callback,indicating that the GCE IRQ has been triggered. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Jason-JH Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_crtc.c | 31 ++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_crtc.h | 1 + drivers/gpu/drm/mediatek/mtk_plane.c | 5 +++++ 3 files changed, 37 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 8f6fba4217ec..0c856cc679de 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -719,6 +719,37 @@ int mtk_crtc_plane_check(struct drm_crtc *crtc, struct= drm_plane *plane, return 0; } =20 +void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane) +{ + struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); + struct mtk_plane_state *plane_state =3D to_mtk_plane_state(plane->state); + int i; + + /* no need to wait for disabling the plane by CPU */ + if (!mtk_crtc->cmdq_client.chan) + return; + + if (!mtk_crtc->enabled) + return; + + /* set pending plane state to disabled */ + for (i =3D 0; i < mtk_crtc->layer_nr; i++) { + struct drm_plane *mtk_plane =3D &mtk_crtc->planes[i]; + struct mtk_plane_state *mtk_plane_state =3D to_mtk_plane_state(mtk_plane= ->state); + + if (mtk_plane->index =3D=3D plane->index) { + memcpy(mtk_plane_state, plane_state, sizeof(*plane_state)); + break; + } + } + mtk_crtc_update_config(mtk_crtc, false); + + /* wait for planes to be disabled by CMDQ */ + wait_event_timeout(mtk_crtc->cb_blocking_queue, + mtk_crtc->cmdq_vblank_cnt =3D=3D 0, + msecs_to_jiffies(500)); +} + void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, struct drm_atomic_state *state) { diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.h b/drivers/gpu/drm/mediatek= /mtk_crtc.h index 388e900b6f4d..828f109b83e7 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_crtc.h @@ -21,6 +21,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const uns= igned int *path, unsigned int num_conn_routes); int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, struct mtk_plane_state *state); +void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane= ); void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, struct drm_atomic_state *plane_state); struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc); diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 655106bbb76d..59edbe26f01e 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -285,9 +285,14 @@ static void mtk_plane_atomic_disable(struct drm_plane = *plane, struct drm_plane_state *new_state =3D drm_atomic_get_new_plane_state(stat= e, plane); struct mtk_plane_state *mtk_plane_state =3D to_mtk_plane_state(new_state); + struct drm_plane_state *old_state =3D drm_atomic_get_old_plane_state(stat= e, + plane); + mtk_plane_state->pending.enable =3D false; wmb(); /* Make sure the above parameter is set before update */ mtk_plane_state->pending.dirty =3D true; + + mtk_crtc_plane_disable(old_state->crtc, plane); } =20 static void mtk_plane_atomic_update(struct drm_plane *plane, --=20 2.43.0