From nobody Tue Dec 16 03:22:15 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41B423D3B8 for ; Tue, 24 Jun 2025 09:15:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750756529; cv=none; b=ogyVItr5OsCfFJVY/rWiuDgzsLi0sYpwj/Iu4jHsdguL5lNDsRZMCnC18aCKAl1IKRvNwelHx5BlDu7EnKy+qUUR5THyKx9fWXbqz/aLkM5gREXxYu1chnWEgFEgofdLrfnIycdhqa1pvYRPEloIPQfV8qRb/OslW1Eq/Z3he/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750756529; c=relaxed/simple; bh=w4DlBS740f36wje1cdOalN6Pq2yDbv+aMS8kLGs1coM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O5c9qfZ+F3lDgLBe02737XzTiCwOp7ZS7ltjyQBp2xAPwv3EIL2hvIB1Xg6tRAcFJgxeOgI5JfYVIl/3gTnySW6l756oA2ksLb9xtIJye6ZN2mBQyL8wmWfxgw7pStBa6K3HIXyClsy3hapqsrCELB9UwWmg31qP4zaxaZunP5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=aHZX/G3F; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="aHZX/G3F" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1750756526; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Jg05gLn4LYp6QB0cNwt5RW/tA0G9+DCBeUGxTXSbrQE=; b=aHZX/G3FxzCMQqbGT0+DbJ8+Lt1PWlhEjATYsvvTnkBxq+eOGaQ3tiWKn2OwJASr7f+7f6 AeZNqdhexmCE44RHaN0Vu6yhaFWZb67FEZEm+RLi7RYRj21kaAGdNwjtOQ8CjPJ4y96gwF fsroQiHJ8Ljl3b599QU1Klqdq8m9ReE= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-610-6R_CZHnePXm5C8zAnVxr9A-1; Tue, 24 Jun 2025 05:15:21 -0400 X-MC-Unique: 6R_CZHnePXm5C8zAnVxr9A-1 X-Mimecast-MFC-AGG-ID: 6R_CZHnePXm5C8zAnVxr9A_1750756519 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id D6D6B1809C97; Tue, 24 Jun 2025 09:15:17 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.224.209]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id EF4A618002B8; Tue, 24 Jun 2025 09:15:11 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v11 01/11] drm/panic: Add a private field to struct drm_scanout_buffer Date: Tue, 24 Jun 2025 11:01:10 +0200 Message-ID: <20250624091501.257661-2-jfalempe@redhat.com> In-Reply-To: <20250624091501.257661-1-jfalempe@redhat.com> References: <20250624091501.257661-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" This allows driver to set some private data in get_scanout_buffer(), and re-use them in set_pixel() callback. Signed-off-by: Jocelyn Falempe --- v10: * Added in v10, to avoid static variables include/drm/drm_panic.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/drm_panic.h b/include/drm/drm_panic.h index 310c88c4d336..ac0e46b73436 100644 --- a/include/drm/drm_panic.h +++ b/include/drm/drm_panic.h @@ -72,6 +72,12 @@ struct drm_scanout_buffer { void (*set_pixel)(struct drm_scanout_buffer *sb, unsigned int x, unsigned int y, u32 color); =20 + /** + * @private: private pointer that you can use in the callbacks + * set_pixel() + */ + void *private; + }; =20 #ifdef CONFIG_DRM_PANIC --=20 2.49.0 From nobody Tue Dec 16 03:22:15 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD18E27A103 for ; Tue, 24 Jun 2025 09:15:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" The vaddr of the fbdev framebuffer is private to the struct intel_fbdev, so this function is needed to access it for drm_panic. Also the struct i915_vma is different between i915 and xe, so it requires a few functions to access fbdev->vma->iomap. Signed-off-by: Jocelyn Falempe --- v2: * Add intel_fb_get_vaddr() and i915_vma_get_iomap() to build with Xe drive= r. =20 v4: * rename to get_map(), and return the struct iosys_map mapping. * implement the Xe variant. drivers/gpu/drm/i915/display/intel_fb_pin.c | 5 +++++ drivers/gpu/drm/i915/display/intel_fb_pin.h | 2 ++ drivers/gpu/drm/i915/display/intel_fbdev.c | 5 +++++ drivers/gpu/drm/i915/display/intel_fbdev.h | 6 +++++- drivers/gpu/drm/i915/i915_vma.h | 5 +++++ drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 +++++ 6 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/= i915/display/intel_fb_pin.c index fcc88e677e47..5a0151775a3a 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -334,3 +334,8 @@ void intel_plane_unpin_fb(struct intel_plane_state *old= _plane_state) intel_dpt_unpin_from_ggtt(fb->dpt_vm); } } + +void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map) +{ + iosys_map_set_vaddr_iomem(map, i915_vma_get_iomap(vma)); +} diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/= i915/display/intel_fb_pin.h index 01770dbba2e0..81ab79da1af7 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -12,6 +12,7 @@ struct drm_framebuffer; struct i915_vma; struct intel_plane_state; struct i915_gtt_view; +struct iosys_map; =20 struct i915_vma * intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, @@ -27,5 +28,6 @@ void intel_fb_unpin_vma(struct i915_vma *vma, unsigned lo= ng flags); int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state); void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); +void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map); =20 #endif diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i= 915/display/intel_fbdev.c index 2dc4029d71ed..7c4709d58aa3 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -512,3 +512,8 @@ struct i915_vma *intel_fbdev_vma_pointer(struct intel_f= bdev *fbdev) { return fbdev ? fbdev->vma : NULL; } + +void intel_fbdev_get_map(struct intel_fbdev *fbdev, struct iosys_map *map) +{ + intel_fb_get_map(fbdev->vma, map); +} diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h b/drivers/gpu/drm/i= 915/display/intel_fbdev.h index a15e3e222a0c..150cc5f45bb3 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev.h @@ -13,6 +13,7 @@ struct drm_fb_helper_surface_size; struct intel_display; struct intel_fbdev; struct intel_framebuffer; +struct iosys_map; =20 #ifdef CONFIG_DRM_FBDEV_EMULATION int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, @@ -22,7 +23,7 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *= helper, void intel_fbdev_setup(struct intel_display *display); struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbde= v); struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev); - +void intel_fbdev_get_map(struct intel_fbdev *fbdev, struct iosys_map *map); #else #define INTEL_FBDEV_DRIVER_OPS \ .fbdev_probe =3D NULL @@ -39,6 +40,9 @@ static inline struct i915_vma *intel_fbdev_vma_pointer(st= ruct intel_fbdev *fbdev return NULL; } =20 +static inline void intel_fbdev_get_map(struct intel_fbdev *fbdev, struct i= osys_map *map) +{ +} #endif =20 #endif /* __INTEL_FBDEV_H__ */ diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vm= a.h index 6a6be8048aa8..4ae610927fa7 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -353,6 +353,11 @@ static inline bool i915_node_color_differs(const struc= t drm_mm_node *node, return drm_mm_node_allocated(node) && node->color !=3D color; } =20 +static inline void __iomem *i915_vma_get_iomap(struct i915_vma *vma) +{ + return READ_ONCE(vma->iomap); +} + /** * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the apert= ure * @vma: VMA to iomap diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/di= splay/xe_fb_pin.c index 6b362695d6b6..45122822b051 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -457,3 +457,8 @@ u64 intel_dpt_offset(struct i915_vma *dpt_vma) { return 0; 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Tue, 24 Jun 2025 09:15:30 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.224.209]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 9233F180045C; Tue, 24 Jun 2025 09:15:24 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v11 03/11] drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes Date: Tue, 24 Jun 2025 11:01:12 +0200 Message-ID: <20250624091501.257661-4-jfalempe@redhat.com> In-Reply-To: <20250624091501.257661-1-jfalempe@redhat.com> References: <20250624091501.257661-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. This assumes that the alignment restriction is always smaller in linear than in tiled. It also assumes that the linear framebuffer size is always smaller than the tiled. Signed-off-by: Jocelyn Falempe --- v7: * Reword commit message about alignment/size when disabling tiling (Ville = Syrj=C3=A4l=C3=A4) drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i9= 15/display/i9xx_plane.c index ac84558006c7..e7e35fd4bdc3 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -905,6 +905,27 @@ static const struct drm_plane_funcs i8xx_plane_funcs = =3D { .format_mod_supported_async =3D intel_plane_format_mod_supported_async, }; =20 +static void i9xx_disable_tiling(struct intel_plane *plane) +{ + struct intel_display *display =3D to_intel_display(plane); + enum i9xx_plane_id i9xx_plane =3D plane->i9xx_plane; + u32 dspcntr; + u32 reg; + + dspcntr =3D intel_de_read_fw(display, DSPCNTR(display, i9xx_plane)); + dspcntr &=3D ~DISP_TILED; + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); + + if (DISPLAY_VER(display) >=3D 4) { + reg =3D intel_de_read_fw(display, DSPSURF(display, i9xx_plane)); + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg); + + } else { + reg =3D intel_de_read_fw(display, DSPADDR(display, i9xx_plane)); + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg); + } +} + struct intel_plane * intel_primary_plane_create(struct intel_display *display, enum pipe pipe) { @@ -1047,6 +1068,8 @@ intel_primary_plane_create(struct intel_display *disp= lay, enum pipe pipe) } } =20 + plane->disable_tiling =3D i9xx_disable_tiling; + modifiers =3D intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILIN= G_X); =20 if (DISPLAY_VER(display) >=3D 5 || display->platform.g4x) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/g= pu/drm/i915/display/intel_display_types.h index 30c7315fc25e..6cd8eb26f858 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1521,6 +1521,8 @@ struct intel_plane { bool async_flip); void (*enable_flip_done)(struct intel_plane *plane); void (*disable_flip_done)(struct intel_plane *plane); + /* For drm_panic */ + void (*disable_tiling)(struct intel_plane *plane); }; =20 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state= , base) --=20 2.49.0 From nobody Tue Dec 16 03:22:15 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A422C279DDC for ; Tue, 24 Jun 2025 09:15:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750756546; cv=none; b=Ar+1YcmJD+Viaj11D49BlylJuthwkFWCKHjvVcgc407vXnhKP6f871rGfGx/xAUTc07u8D/UT+xJzSazIfO3D51s+S0zQfZSHW4lOUrvpFr5MSDt4AC0E4BnzDEsWhztAQAUnvzpr0eITX4qW2CFoyJudkMajf6FVnfGLicy5s8= ARC-Message-Signature: i=1; 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Tue, 24 Jun 2025 09:15:36 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.224.209]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 380A5180045C; Tue, 24 Jun 2025 09:15:30 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v11 04/11] drm/i915/display: Add a disable_tiling() for skl planes Date: Tue, 24 Jun 2025 11:01:13 +0200 Message-ID: <20250624091501.257661-5-jfalempe@redhat.com> In-Reply-To: <20250624091501.257661-1-jfalempe@redhat.com> References: <20250624091501.257661-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. This assumes that the alignment restriction is always smaller in linear than in tiled. It also assumes that the linear framebuffer size is always smaller than the tiled. Signed-off-by: Jocelyn Falempe --- v7: * Reword commit message about alignment/size when disabling tiling (Ville = Syrj=C3=A4l=C3=A4) .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index 68f18f18bacd..1ba04f1b3ec0 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2791,6 +2791,25 @@ static u8 tgl_plane_caps(struct intel_display *displ= ay, return caps; } =20 +static void skl_disable_tiling(struct intel_plane *plane) +{ + struct intel_plane_state *state =3D to_intel_plane_state(plane->base.stat= e); + struct intel_display *display =3D to_intel_display(plane); + u32 stride =3D state->view.color_plane[0].scanout_stride / 64; + u32 plane_ctl; + + plane_ctl =3D intel_de_read(display, PLANE_CTL(plane->pipe, plane->id)); + plane_ctl &=3D ~PLANE_CTL_TILED_MASK; + + intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), + PLANE_STRIDE_(stride)); + + intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl); + + intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id), + skl_plane_surf(state, 0)); +} + struct intel_plane * skl_universal_plane_create(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) @@ -2837,6 +2856,7 @@ skl_universal_plane_create(struct intel_display *disp= lay, plane->max_height =3D skl_plane_max_height; plane->min_cdclk =3D skl_plane_min_cdclk; } + plane->disable_tiling =3D skl_disable_tiling; =20 if (DISPLAY_VER(display) >=3D 13) plane->max_stride =3D adl_plane_max_stride; --=20 2.49.0 From nobody Tue Dec 16 03:22:15 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F4A0279DDF for ; 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Tue, 24 Jun 2025 05:15:45 -0400 X-MC-Unique: YXZb2hYLOyyBuq3I5bWDhA-1 X-Mimecast-MFC-AGG-ID: YXZb2hYLOyyBuq3I5bWDhA_1750756543 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 0D0C81955F44; Tue, 24 Jun 2025 09:15:43 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.224.209]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 6605A180045C; Tue, 24 Jun 2025 09:15:37 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v11 05/11] drm/ttm: Add ttm_bo_kmap_try_from_panic() Date: Tue, 24 Jun 2025 11:01:14 +0200 Message-ID: <20250624091501.257661-6-jfalempe@redhat.com> In-Reply-To: <20250624091501.257661-1-jfalempe@redhat.com> References: <20250624091501.257661-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 If the ttm bo is backed by pages, then it's possible to safely kmap one page at a time, using kmap_try_from_panic(). Unfortunately there is no way to do the same with ioremap, so it only supports the kmap case. This is needed for proper drm_panic support with xe driver. Signed-off-by: Jocelyn Falempe Reviewed-by: Christian K=C3=B6nig --- v8: * Added in v8 v9: * Fix comment in ttm_bo_kmap_try_from_panic(), this can *only* be called from the panic handler (Christian K=C3=B6nig) drivers/gpu/drm/ttm/ttm_bo_util.c | 27 +++++++++++++++++++++++++++ include/drm/ttm/ttm_bo.h | 1 + 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo= _util.c index b9a772b26fa1..ad95e8b9852b 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -381,6 +381,33 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *b= o, return (!map->virtual) ? -ENOMEM : 0; } =20 +/** + * + * ttm_bo_kmap_try_from_panic + * + * @bo: The buffer object + * @page: The page to map + * + * Sets up a kernel virtual mapping using kmap_local_page_try_from_panic(). + * This should only be called from the panic handler, if you make sure the= bo + * is the one being displayed, so is properly allocated, and protected. + * + * Returns the vaddr, that you can use to write to the bo, and that you sh= ould + * pass to kunmap_local() when you're done with this page, or NULL if the = bo + * is in iomem. + */ +void *ttm_bo_kmap_try_from_panic(struct ttm_buffer_object *bo, unsigned lo= ng page) +{ + if (page + 1 > PFN_UP(bo->resource->size)) + return NULL; + + if (!bo->resource->bus.is_iomem && bo->ttm->pages && bo->ttm->pages[page]) + return kmap_local_page_try_from_panic(bo->ttm->pages[page]); + + return NULL; +} +EXPORT_SYMBOL(ttm_bo_kmap_try_from_panic); + /** * ttm_bo_kmap * diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 8ad6e2713625..5332ee74d95b 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -401,6 +401,7 @@ int ttm_bo_init_validate(struct ttm_device *bdev, struc= t ttm_buffer_object *bo, int ttm_bo_kmap(struct ttm_buffer_object *bo, unsigned long start_page, unsigned long num_pages, struct ttm_bo_kmap_obj *map); void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map); +void *ttm_bo_kmap_try_from_panic(struct ttm_buffer_object *bo, unsigned lo= ng page); int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map); void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map); int ttm_bo_mmap_obj(struct vm_area_struct *vma, struct ttm_buffer_object *= bo); --=20 2.49.0 From nobody Tue Dec 16 03:22:15 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1EC027AC3E for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Encapsulate the struct intel_framebuffer into an xe_framebuffer or i915_framebuffer, and allow to add specific fields for each variant for the panic use-case. This is particularly needed to have a struct xe_res_cursor available to support drm panic on discrete GPU. Signed-off-by: Jocelyn Falempe --- v11: * Added in v11 drivers/gpu/drm/i915/display/i9xx_plane.c | 3 ++- drivers/gpu/drm/i915/display/intel_bo.c | 6 +++++ drivers/gpu/drm/i915/display/intel_bo.h | 2 ++ drivers/gpu/drm/i915/display/intel_fb.c | 2 +- .../drm/i915/display/skl_universal_plane.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 ++ drivers/gpu/drm/i915/gem/i915_gem_pages.c | 22 +++++++++++++++++ drivers/gpu/drm/xe/display/intel_bo.c | 24 +++++++++++++++++++ 8 files changed, 60 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i9= 15/display/i9xx_plane.c index e7e35fd4bdc3..f291ced989dc 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -15,6 +15,7 @@ #include "i9xx_plane.h" #include "i9xx_plane_regs.h" #include "intel_atomic.h" +#include "intel_bo.h" #include "intel_de.h" #include "intel_display_irq.h" #include "intel_display_regs.h" @@ -1174,7 +1175,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, =20 drm_WARN_ON(display->drm, pipe !=3D crtc->pipe); =20 - intel_fb =3D kzalloc(sizeof(*intel_fb), GFP_KERNEL); + intel_fb =3D intel_bo_alloc_framebuffer(); if (!intel_fb) { drm_dbg_kms(display->drm, "failed to alloc fb\n"); return; diff --git a/drivers/gpu/drm/i915/display/intel_bo.c b/drivers/gpu/drm/i915= /display/intel_bo.c index fbd16d7b58d9..bcf2eded7469 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.c +++ b/drivers/gpu/drm/i915/display/intel_bo.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: MIT /* Copyright =C2=A9 2024 Intel Corporation */ =20 +#include "display/intel_display_types.h" #include "gem/i915_gem_mman.h" #include "gem/i915_gem_object.h" #include "gem/i915_gem_object_frontbuffer.h" @@ -57,3 +58,8 @@ void intel_bo_describe(struct seq_file *m, struct drm_gem= _object *obj) { i915_debugfs_describe_obj(m, to_intel_bo(obj)); } + +struct intel_framebuffer *intel_bo_alloc_framebuffer(void) +{ + return i915_gem_object_alloc_framebuffer(); +} diff --git a/drivers/gpu/drm/i915/display/intel_bo.h b/drivers/gpu/drm/i915= /display/intel_bo.h index ea7a2253aaa5..315a81768c73 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.h +++ b/drivers/gpu/drm/i915/display/intel_bo.h @@ -7,6 +7,7 @@ #include =20 struct drm_gem_object; +struct intel_framebuffer; struct seq_file; struct vm_area_struct; =20 @@ -23,5 +24,6 @@ struct intel_frontbuffer *intel_bo_set_frontbuffer(struct= drm_gem_object *obj, struct intel_frontbuffer *front); =20 void intel_bo_describe(struct seq_file *m, struct drm_gem_object *obj); +struct intel_framebuffer *intel_bo_alloc_framebuffer(void); =20 #endif /* __INTEL_BO__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915= /display/intel_fb.c index 763b36c4de10..6158031821fd 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -2346,7 +2346,7 @@ intel_framebuffer_create(struct drm_gem_object *obj, struct intel_framebuffer *intel_fb; int ret; =20 - intel_fb =3D kzalloc(sizeof(*intel_fb), GFP_KERNEL); + intel_fb =3D intel_bo_alloc_framebuffer(); if (!intel_fb) return ERR_PTR(-ENOMEM); =20 diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index 1ba04f1b3ec0..cbd0521a201c 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -3029,7 +3029,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, return; } =20 - intel_fb =3D kzalloc(sizeof(*intel_fb), GFP_KERNEL); + intel_fb =3D intel_bo_alloc_framebuffer(); if (!intel_fb) { drm_dbg_kms(display->drm, "failed to alloc fb\n"); return; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i= 915/gem/i915_gem_object.h index c34f41605b46..364941444a0a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -17,6 +17,7 @@ #include "i915_vma_types.h" =20 enum intel_region_id; +struct intel_framebuffer; =20 #define obj_to_i915(obj__) to_i915((obj__)->base.dev) =20 @@ -691,6 +692,7 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object = *obj) int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj); int i915_gem_object_truncate(struct drm_i915_gem_object *obj); =20 +struct intel_framebuffer *i915_gem_object_alloc_framebuffer(void); /** * i915_gem_object_pin_map - return a contiguous mapping of the entire obj= ect * @obj: the object to map into kernel address space diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i9= 15/gem/i915_gem_pages.c index 7f83f8bdc8fb..10b84970f17f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -6,6 +6,7 @@ #include #include =20 +#include "display/intel_display_types.h" #include "gt/intel_gt.h" #include "gt/intel_tlb.h" =20 @@ -354,6 +355,27 @@ static void *i915_gem_object_map_pfn(struct drm_i915_g= em_object *obj, return vaddr ?: ERR_PTR(-ENOMEM); } =20 +struct i915_panic_data { + struct page **pages; + int page; + void *vaddr; +}; + +struct i915_framebuffer { + struct intel_framebuffer base; + struct i915_panic_data panic; +}; + +struct intel_framebuffer *i915_gem_object_alloc_framebuffer(void) +{ + struct i915_framebuffer *i915_fb; + + i915_fb =3D kzalloc(sizeof(*i915_fb), GFP_KERNEL); + if (i915_fb) + return &i915_fb->base; + return NULL; +} + /* get, pin, and map the pages of the object into kernel space */ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, enum i915_map_type type) diff --git a/drivers/gpu/drm/xe/display/intel_bo.c b/drivers/gpu/drm/xe/dis= play/intel_bo.c index 27437c22bd70..926fcd9c86e1 100644 --- a/drivers/gpu/drm/xe/display/intel_bo.c +++ b/drivers/gpu/drm/xe/display/intel_bo.c @@ -3,6 +3,8 @@ =20 #include =20 +#include "intel_display_types.h" + #include "xe_bo.h" #include "intel_bo.h" =20 @@ -59,3 +61,25 @@ void intel_bo_describe(struct seq_file *m, struct drm_ge= m_object *obj) { /* FIXME */ } + +struct xe_panic_data { + struct page **pages; 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Tue, 24 Jun 2025 09:15:55 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.224.209]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id B2C4D18002B8; Tue, 24 Jun 2025 09:15:49 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v11 07/11] drm/i915: Add intel_bo_panic_setup() and intel_bo_panic_finish() Date: Tue, 24 Jun 2025 11:01:16 +0200 Message-ID: <20250624091501.257661-8-jfalempe@redhat.com> In-Reply-To: <20250624091501.257661-1-jfalempe@redhat.com> References: <20250624091501.257661-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Implement both functions for i915 and xe, they prepare the work for drm_panic support. They both use kmap_try_from_panic(), and map one page at a time, to write the panic screen on the framebuffer. Signed-off-by: Jocelyn Falempe --- v5: * Use iosys_map for intel_bo_panic_map(). v7: * Return int for i915_gem_object_panic_map() (Ville Syrj=C3=A4l=C3=A4) v8: * Complete rewrite, to use kmap_try_from_panic() which is safe to call from a panic handler. v9: * Fix missing kfree() for i915_panic_pages in i915_gem_object_panic_finish= () Also change i915_panic_pages allocation to kmalloc, as kvmalloc is not safe to call from the panic handler. v10: * Replace static variables with new fields in struct intel_framebuffer (Maarten Lankhorst) * Add error handling if i915_gem_object_panic_pages() returns NULL * Declare struct drm_scanout_buffer instead of including in intel_bo.h v11: * Use struct i915_framebuffer and xe_framebuffer drivers/gpu/drm/i915/display/intel_bo.c | 11 +++ drivers/gpu/drm/i915/display/intel_bo.h | 3 + drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 + drivers/gpu/drm/i915/gem/i915_gem_pages.c | 106 +++++++++++++++++++++ drivers/gpu/drm/xe/display/intel_bo.c | 64 +++++++++++++ 5 files changed, 188 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bo.c b/drivers/gpu/drm/i915= /display/intel_bo.c index bcf2eded7469..65d64f79a4bd 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.c +++ b/drivers/gpu/drm/i915/display/intel_bo.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: MIT /* Copyright =C2=A9 2024 Intel Corporation */ =20 +#include #include "display/intel_display_types.h" #include "gem/i915_gem_mman.h" #include "gem/i915_gem_object.h" @@ -63,3 +64,13 @@ struct intel_framebuffer *intel_bo_alloc_framebuffer(voi= d) { return i915_gem_object_alloc_framebuffer(); } + +int intel_bo_panic_setup(struct drm_scanout_buffer *sb) +{ + return i915_gem_object_panic_setup(sb); +} + +void intel_bo_panic_finish(struct intel_framebuffer *fb) +{ + return i915_gem_object_panic_finish(fb); +} diff --git a/drivers/gpu/drm/i915/display/intel_bo.h b/drivers/gpu/drm/i915= /display/intel_bo.h index 315a81768c73..97087a64d23b 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.h +++ b/drivers/gpu/drm/i915/display/intel_bo.h @@ -7,6 +7,7 @@ #include =20 struct drm_gem_object; +struct drm_scanout_buffer; struct intel_framebuffer; struct seq_file; struct vm_area_struct; @@ -25,5 +26,7 @@ struct intel_frontbuffer *intel_bo_set_frontbuffer(struct= drm_gem_object *obj, =20 void intel_bo_describe(struct seq_file *m, struct drm_gem_object *obj); struct intel_framebuffer *intel_bo_alloc_framebuffer(void); +int intel_bo_panic_setup(struct drm_scanout_buffer *sb); +void intel_bo_panic_finish(struct intel_framebuffer *fb); =20 #endif /* __INTEL_BO__ */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i= 915/gem/i915_gem_object.h index 364941444a0a..565f8fa330db 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -16,6 +16,7 @@ #include "i915_gem_ww.h" #include "i915_vma_types.h" =20 +struct drm_scanout_buffer; enum intel_region_id; struct intel_framebuffer; =20 @@ -693,6 +694,9 @@ int __i915_gem_object_put_pages(struct drm_i915_gem_obj= ect *obj); int i915_gem_object_truncate(struct drm_i915_gem_object *obj); =20 struct intel_framebuffer *i915_gem_object_alloc_framebuffer(void); +int i915_gem_object_panic_setup(struct drm_scanout_buffer *sb); +void i915_gem_object_panic_finish(struct intel_framebuffer *fb); + /** * i915_gem_object_pin_map - return a contiguous mapping of the entire obj= ect * @obj: the object to map into kernel address space diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i9= 15/gem/i915_gem_pages.c index 10b84970f17f..91c7549e6ff2 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -4,8 +4,10 @@ */ =20 #include +#include #include =20 +#include "display/intel_fb.h" #include "display/intel_display_types.h" #include "gt/intel_gt.h" #include "gt/intel_tlb.h" @@ -366,6 +368,67 @@ struct i915_framebuffer { struct i915_panic_data panic; }; =20 +static inline struct i915_panic_data *to_i915_panic_data(struct intel_fram= ebuffer *fb) +{ + return &container_of_const(fb, struct i915_framebuffer, base)->panic; +} + +static void i915_panic_kunmap(struct i915_panic_data *panic) +{ + if (panic->vaddr) { + drm_clflush_virt_range(panic->vaddr, PAGE_SIZE); + kunmap_local(panic->vaddr); + panic->vaddr =3D NULL; + } +} + +static struct page **i915_gem_object_panic_pages(struct drm_i915_gem_objec= t *obj) +{ + unsigned long n_pages =3D obj->base.size >> PAGE_SHIFT, i; + struct page *page; + struct page **pages; + struct sgt_iter iter; + + /* For a 3840x2160 32 bits Framebuffer, this should require ~64K */ + pages =3D kmalloc_array(n_pages, sizeof(*pages), GFP_ATOMIC); + if (!pages) + return NULL; + + i =3D 0; + for_each_sgt_page(page, iter, obj->mm.pages) + pages[i++] =3D page; + return pages; +} + +/* + * The scanout buffer pages are not mapped, so for each pixel, + * use kmap_local_page_try_from_panic() to map the page, and write the pix= el. + * Try to keep the map from the previous pixel, to avoid too much map/unma= p. + */ +static void i915_gem_object_panic_page_set_pixel(struct drm_scanout_buffer= *sb, unsigned int x, + unsigned int y, u32 color) +{ + unsigned int new_page; + unsigned int offset; + struct intel_framebuffer *fb =3D (struct intel_framebuffer *)sb->private; + struct i915_panic_data *panic =3D to_i915_panic_data(fb); + + offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; + + new_page =3D offset >> PAGE_SHIFT; + offset =3D offset % PAGE_SIZE; + if (new_page !=3D panic->page) { + i915_panic_kunmap(panic); + panic->page =3D new_page; + panic->vaddr =3D + kmap_local_page_try_from_panic(panic->pages[panic->page]); + } + if (panic->vaddr) { + u32 *pix =3D panic->vaddr + offset; + *pix =3D color; + } +} + struct intel_framebuffer *i915_gem_object_alloc_framebuffer(void) { struct i915_framebuffer *i915_fb; @@ -376,6 +439,49 @@ struct intel_framebuffer *i915_gem_object_alloc_frameb= uffer(void) return NULL; } =20 +/* + * Setup the gem framebuffer for drm_panic access. + * Use current vaddr if it exists, or setup a list of pages. + * pfn is not supported yet. + */ +int i915_gem_object_panic_setup(struct drm_scanout_buffer *sb) +{ + enum i915_map_type has_type; + struct intel_framebuffer *fb =3D (struct intel_framebuffer *)sb->private; + struct i915_panic_data *panic =3D to_i915_panic_data(fb); + struct drm_i915_gem_object *obj =3D to_intel_bo(intel_fb_bo(&fb->base)); + void *ptr; + + ptr =3D page_unpack_bits(obj->mm.mapping, &has_type); + if (ptr) { + if (i915_gem_object_has_iomem(obj)) + iosys_map_set_vaddr_iomem(&sb->map[0], (void __iomem *)ptr); + else + iosys_map_set_vaddr(&sb->map[0], ptr); + + return 0; + } + if (i915_gem_object_has_struct_page(obj)) { + panic->pages =3D i915_gem_object_panic_pages(obj); + if (!panic->pages) + return -ENOMEM; + panic->page =3D -1; + sb->set_pixel =3D i915_gem_object_panic_page_set_pixel; + return 0; + } + return -EOPNOTSUPP; +} + +void i915_gem_object_panic_finish(struct intel_framebuffer *fb) +{ + struct i915_panic_data *panic =3D to_i915_panic_data(fb); + + i915_panic_kunmap(panic); + panic->page =3D -1; + kfree(panic->pages); + panic->pages =3D NULL; +} + /* get, pin, and map the pages of the object into kernel space */ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, enum i915_map_type type) diff --git a/drivers/gpu/drm/xe/display/intel_bo.c b/drivers/gpu/drm/xe/dis= play/intel_bo.c index 926fcd9c86e1..bbb504f8e242 100644 --- a/drivers/gpu/drm/xe/display/intel_bo.c +++ b/drivers/gpu/drm/xe/display/intel_bo.c @@ -1,8 +1,11 @@ // SPDX-License-Identifier: MIT /* Copyright =C2=A9 2024 Intel Corporation */ =20 +#include #include +#include =20 +#include "intel_fb.h" #include "intel_display_types.h" =20 #include "xe_bo.h" @@ -73,6 +76,50 @@ struct xe_framebuffer { struct xe_panic_data panic; }; =20 +static inline struct xe_panic_data *to_xe_panic_data(struct intel_framebuf= fer *fb) +{ + return &container_of_const(fb, struct xe_framebuffer, base)->panic; +} + +static void xe_panic_kunmap(struct xe_panic_data *panic) +{ + if (panic->vaddr) { + drm_clflush_virt_range(panic->vaddr, PAGE_SIZE); + kunmap_local(panic->vaddr); + panic->vaddr =3D NULL; + } +} + +/* + * The scanout buffer pages are not mapped, so for each pixel, + * use kmap_local_page_try_from_panic() to map the page, and write the pix= el. + * Try to keep the map from the previous pixel, to avoid too much map/unma= p. + */ +static void xe_panic_page_set_pixel(struct drm_scanout_buffer *sb, unsigne= d int x, + unsigned int y, u32 color) +{ + struct intel_framebuffer *fb =3D (struct intel_framebuffer *)sb->private; + struct xe_panic_data *panic =3D to_xe_panic_data(fb); + struct xe_bo *bo =3D gem_to_xe_bo(intel_fb_bo(&fb->base)); + unsigned int new_page; + unsigned int offset; + + offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; + + new_page =3D offset >> PAGE_SHIFT; + offset =3D offset % PAGE_SIZE; + if (new_page !=3D panic->page) { + xe_panic_kunmap(panic); + panic->page =3D new_page; + panic->vaddr =3D ttm_bo_kmap_try_from_panic(&bo->ttm, + panic->page); + } + if (panic->vaddr) { + u32 *pix =3D panic->vaddr + offset; + *pix =3D color; + } +} + struct intel_framebuffer *intel_bo_alloc_framebuffer(void) { struct xe_framebuffer *xe_fb; @@ -83,3 +130,20 @@ struct intel_framebuffer *intel_bo_alloc_framebuffer(vo= id) return NULL; } =20 +int intel_bo_panic_setup(struct drm_scanout_buffer *sb) +{ + struct intel_framebuffer *fb =3D (struct intel_framebuffer *)sb->private; + struct xe_panic_data *panic =3D to_xe_panic_data(fb); + + panic->page =3D -1; + sb->set_pixel =3D xe_panic_page_set_pixel; + return 0; +} + +void intel_bo_panic_finish(struct intel_framebuffer *fb) +{ + struct xe_panic_data *panic =3D to_xe_panic_data(fb); + + xe_panic_kunmap(panic); + panic->page =3D -1; +} --=20 2.49.0 From nobody Tue Dec 16 03:22:15 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6E9D279DDD for ; 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Tue, 24 Jun 2025 05:16:07 -0400 X-MC-Unique: z4lwXWfFNRuYjKBUkxBzAw-1 X-Mimecast-MFC-AGG-ID: z4lwXWfFNRuYjKBUkxBzAw_1750756561 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 70E8D195609F; Tue, 24 Jun 2025 09:16:01 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.224.209]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id D4AA7180045B; Tue, 24 Jun 2025 09:15:55 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v11 08/11] drm/i915/display: Add drm_panic support Date: Tue, 24 Jun 2025 11:01:17 +0200 Message-ID: <20250624091501.257661-9-jfalempe@redhat.com> In-Reply-To: <20250624091501.257661-1-jfalempe@redhat.com> References: <20250624091501.257661-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" This adds drm_panic support for a wide range of Intel GPU. I've tested it only on 4 laptops, Haswell (with 128MB of eDRAM), Comet Lake, Raptor Lake, and Lunar Lake. For hardware using DPT, it's not possible to disable tiling, as you will need to reconfigure the way the GPU is accessing the framebuffer, so this will be handled by the following patches. Signed-off-by: Jocelyn Falempe --- v4: * Add support for Xe driver. =20 v6: * Use struct intel_display instead of drm_i915_private for intel_atomic_pl= ane.c =20 v7: * Fix mismatch {} in intel_panic_flush() (Jani Nikula) v8: * Use intel_bo_panic_setup() and intel_bo_panic_finish(). =20 v10: * Use struct intel_framebuffer to store the panic variables (Maarten Lankh= orst) drivers/gpu/drm/i915/display/intel_plane.c | 83 +++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i= 915/display/intel_plane.c index eae926d998ff..5b889335c4b4 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -33,18 +33,22 @@ =20 #include #include +#include =20 #include #include +#include #include #include #include #include +#include =20 #include "gem/i915_gem_object.h" #include "i915_scheduler_types.h" #include "i915_vma.h" #include "i9xx_plane_regs.h" +#include "intel_bo.h" #include "intel_cdclk.h" #include "intel_cursor.h" #include "intel_display_rps.h" @@ -52,6 +56,7 @@ #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" +#include "intel_fbdev.h" #include "intel_plane.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -1267,14 +1272,90 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_plane_unpin_fb(old_plane_state); } =20 +static void intel_panic_flush(struct drm_plane *plane) +{ + struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); + struct intel_plane *iplane =3D to_intel_plane(plane); + struct intel_display *display =3D to_intel_display(iplane); + struct drm_framebuffer *fb =3D plane_state->hw.fb; + struct intel_framebuffer *intel_fb =3D to_intel_framebuffer(fb); + + intel_bo_panic_finish(intel_fb); + + /* Flush the cache and don't disable tiling if it's the fbdev framebuffer= .*/ + if (intel_fb =3D=3D intel_fbdev_framebuffer(display->fbdev.fbdev)) { + struct iosys_map map; + + intel_fbdev_get_map(display->fbdev.fbdev, &map); + drm_clflush_virt_range(map.vaddr, fb->pitches[0] * fb->height); + return; + } + + if (fb->modifier && iplane->disable_tiling) + iplane->disable_tiling(iplane); +} + +static int intel_get_scanout_buffer(struct drm_plane *plane, + struct drm_scanout_buffer *sb) +{ + struct intel_plane_state *plane_state; + struct drm_gem_object *obj; + struct drm_framebuffer *fb; + struct intel_framebuffer *intel_fb; + struct intel_display *display =3D to_intel_display(plane->dev); + + if (!plane->state || !plane->state->fb || !plane->state->visible) + return -ENODEV; + + plane_state =3D to_intel_plane_state(plane->state); + fb =3D plane_state->hw.fb; + intel_fb =3D to_intel_framebuffer(fb); + + obj =3D intel_fb_bo(fb); + if (!obj) + return -ENODEV; + + if (intel_fb =3D=3D intel_fbdev_framebuffer(display->fbdev.fbdev)) { + intel_fbdev_get_map(display->fbdev.fbdev, &sb->map[0]); + } else { + int ret; + /* Can't disable tiling if DPT is in use */ + if (intel_fb_uses_dpt(fb)) + return -EOPNOTSUPP; + sb->private =3D intel_fb; + ret =3D intel_bo_panic_setup(sb); + if (ret) + return ret; + } + sb->width =3D fb->width; + sb->height =3D fb->height; + /* Use the generic linear format, because tiling, RC, CCS, CC + * will be disabled in disable_tiling() + */ + sb->format =3D drm_format_info(fb->format->format); + sb->pitch[0] =3D fb->pitches[0]; + + return 0; +} + static const struct drm_plane_helper_funcs intel_plane_helper_funcs =3D { .prepare_fb =3D intel_prepare_plane_fb, .cleanup_fb =3D intel_cleanup_plane_fb, }; =20 +static const struct drm_plane_helper_funcs intel_primary_plane_helper_func= s =3D { + .prepare_fb =3D intel_prepare_plane_fb, + .cleanup_fb =3D intel_cleanup_plane_fb, + .get_scanout_buffer =3D intel_get_scanout_buffer, + .panic_flush =3D intel_panic_flush, +}; + void intel_plane_helper_add(struct intel_plane *plane) { - drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); + if (plane->base.type =3D=3D DRM_PLANE_TYPE_PRIMARY) + drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs); + else + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); } =20 void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_pla= ne_state, --=20 2.49.0 From nobody Tue Dec 16 03:22:15 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D2F927AC59 for ; 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charset="utf-8" On Alder Lake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements Y-Tiling support, to still be able to draw the panic screen. Signed-off-by: Jocelyn Falempe --- v8: * Pass the tiling function to intel_bo_panic_setup() v10: * Use the struct intel_framebuffer to store the tiling function .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_plane.c | 64 ++++++++++++++++++- .../drm/i915/display/skl_universal_plane.c | 15 +++-- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 16 ++++- drivers/gpu/drm/xe/display/intel_bo.c | 5 +- 5 files changed, 94 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/g= pu/drm/i915/display/intel_display_types.h index 6cd8eb26f858..a67ca33ac57a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -146,6 +146,8 @@ struct intel_framebuffer { =20 unsigned int min_alignment; unsigned int vtd_guard; + + unsigned int (*panic_tiling)(unsigned int x, unsigned int y, unsigned int= width); }; =20 enum intel_hotplug_state { diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i= 915/display/intel_plane.c index 5b889335c4b4..5bdfe1cbbb7b 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -1272,6 +1272,32 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_plane_unpin_fb(old_plane_state); } =20 +/* Handle Y-tiling, only if DPT is enabled (otherwise disabling tiling is = easier) + * All DPT hardware have 128-bytes width tiling, so Y-tile dimension is 32= x32 + * pixels for 32bits pixels. + */ +#define YTILE_WIDTH 32 +#define YTILE_HEIGHT 32 +#define YTILE_SIZE (YTILE_WIDTH * YTILE_HEIGHT * 4) + +static unsigned int intel_ytile_get_offset(unsigned int width, unsigned in= t x, unsigned int y) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks =3D DIV_ROUND_UP(width, 32); + + /* Block offset */ + offset =3D ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * Y= TILE_SIZE; + + x =3D x % YTILE_WIDTH; + y =3D y % YTILE_HEIGHT; + + /* bit order inside a block is x4 x3 x2 y4 y3 y2 y1 y0 x1 x0 */ + swizzle =3D (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5); + offset +=3D swizzle * 4; + return offset; +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); @@ -1295,6 +1321,35 @@ static void intel_panic_flush(struct drm_plane *plan= e) iplane->disable_tiling(iplane); } =20 +static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int= width, + unsigned int x, + unsigned int y) +{ + switch (fb_modifier) { + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + return intel_ytile_get_offset; + case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: + case I915_FORMAT_MOD_4_TILED_BMG_CCS: + case I915_FORMAT_MOD_4_TILED_LNL_CCS: + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Yf_TILED: + case I915_FORMAT_MOD_Yf_TILED_CCS: + default: + /* Not supported yet */ + return NULL; + } +} + static int intel_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb) { @@ -1320,8 +1375,13 @@ static int intel_get_scanout_buffer(struct drm_plane= *plane, } else { int ret; /* Can't disable tiling if DPT is in use */ - if (intel_fb_uses_dpt(fb)) - return -EOPNOTSUPP; + if (intel_fb_uses_dpt(fb)) { + if (fb->format->cpp[0] !=3D 4) + return -EOPNOTSUPP; + intel_fb->panic_tiling =3D intel_get_tiling_func(fb->modifier); + if (!intel_fb->panic_tiling) + return -EOPNOTSUPP; + } sb->private =3D intel_fb; ret =3D intel_bo_panic_setup(sb); if (ret) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index cbd0521a201c..e20972ddfa09 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2795,15 +2795,22 @@ static void skl_disable_tiling(struct intel_plane *= plane) { struct intel_plane_state *state =3D to_intel_plane_state(plane->base.stat= e); struct intel_display *display =3D to_intel_display(plane); - u32 stride =3D state->view.color_plane[0].scanout_stride / 64; + const struct drm_framebuffer *fb =3D state->hw.fb; u32 plane_ctl; =20 plane_ctl =3D intel_de_read(display, PLANE_CTL(plane->pipe, plane->id)); - plane_ctl &=3D ~PLANE_CTL_TILED_MASK; =20 - intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), - PLANE_STRIDE_(stride)); + if (intel_fb_uses_dpt(fb)) { + /* if DPT is enabled, keep tiling, but disable compression */ + plane_ctl &=3D ~PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; + } else { + /* if DPT is not supported, disable tiling, and update stride */ + u32 stride =3D state->view.color_plane[0].scanout_stride / 64; =20 + plane_ctl &=3D ~PLANE_CTL_TILED_MASK; + intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), + PLANE_STRIDE_(stride)); + } intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl); =20 intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id), diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i9= 15/gem/i915_gem_pages.c index 91c7549e6ff2..c16a57160b26 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -400,6 +400,15 @@ static struct page **i915_gem_object_panic_pages(struc= t drm_i915_gem_object *obj return pages; } =20 +static void i915_gem_object_panic_map_set_pixel(struct drm_scanout_buffer = *sb, unsigned int x, + unsigned int y, u32 color) +{ + struct intel_framebuffer *fb =3D (struct intel_framebuffer *)sb->private; + unsigned int offset =3D fb->panic_tiling(sb->width, x, y); + + iosys_map_wr(&sb->map[0], offset, u32, color); +} + /* * The scanout buffer pages are not mapped, so for each pixel, * use kmap_local_page_try_from_panic() to map the page, and write the pix= el. @@ -413,7 +422,10 @@ static void i915_gem_object_panic_page_set_pixel(struc= t drm_scanout_buffer *sb, struct intel_framebuffer *fb =3D (struct intel_framebuffer *)sb->private; struct i915_panic_data *panic =3D to_i915_panic_data(fb); =20 - offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; + if (fb->panic_tiling) + offset =3D fb->panic_tiling(sb->width, x, y); + else + offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; =20 new_page =3D offset >> PAGE_SHIFT; offset =3D offset % PAGE_SIZE; @@ -459,6 +471,8 @@ int i915_gem_object_panic_setup(struct drm_scanout_buff= er *sb) else iosys_map_set_vaddr(&sb->map[0], ptr); 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charset="utf-8" On Alder Lake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements 4-Tiling support, to still be able to draw the panic screen. Signed-off-by: Jocelyn Falempe --- drivers/gpu/drm/i915/display/intel_plane.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i= 915/display/intel_plane.c index 5bdfe1cbbb7b..f6b6704f77a1 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -1298,6 +1298,25 @@ static unsigned int intel_ytile_get_offset(unsigned = int width, unsigned int x, u return offset; } =20 +static unsigned int intel_4tile_get_offset(unsigned int width, unsigned in= t x, unsigned int y) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks =3D DIV_ROUND_UP(width, 32); + + /* Block offset */ + offset =3D ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * Y= TILE_SIZE; + + x =3D x % YTILE_WIDTH; + y =3D y % YTILE_HEIGHT; + + /* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */ + swizzle =3D (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 | + ((x & 0x10) << 3) | ((y & 0x18) << 5); + offset +=3D swizzle * 4; + return offset; +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); @@ -1341,6 +1360,7 @@ static unsigned int (*intel_get_tiling_func(u64 fb_mo= difier))(unsigned int width case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_BMG_CCS: case I915_FORMAT_MOD_4_TILED_LNL_CCS: + return intel_4tile_get_offset; case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Yf_TILED: case I915_FORMAT_MOD_Yf_TILED_CCS: --=20 2.49.0 From nobody Tue Dec 16 03:22:15 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2090127AC3D for ; Tue, 24 Jun 2025 09:16:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; 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Tue, 24 Jun 2025 09:16:20 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.224.209]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 679E218002B8; Tue, 24 Jun 2025 09:16:14 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v11 11/11] drm/i915/psr: Add intel_psr2_panic_force_full_update Date: Tue, 24 Jun 2025 11:01:20 +0200 Message-ID: <20250624091501.257661-12-jfalempe@redhat.com> In-Reply-To: <20250624091501.257661-1-jfalempe@redhat.com> References: <20250624091501.257661-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" When the panic handler is called, configure the psr to send the full framebuffer to the monitor, otherwise the panic screen is only partially visible. Signed-off-by: Jocelyn Falempe --- v8: * Added in v8 drivers/gpu/drm/i915/display/intel_plane.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_psr.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 ++ 3 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i= 915/display/intel_plane.c index f6b6704f77a1..cea27de26fca 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -58,6 +58,7 @@ #include "intel_fb_pin.h" #include "intel_fbdev.h" #include "intel_plane.h" +#include "intel_psr.h" #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_watermark.h" @@ -1320,6 +1321,7 @@ static unsigned int intel_4tile_get_offset(unsigned i= nt width, unsigned int x, u static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); + struct intel_crtc_state *crtc_state =3D to_intel_crtc_state(plane->state-= >crtc->state); struct intel_plane *iplane =3D to_intel_plane(plane); struct intel_display *display =3D to_intel_display(iplane); struct drm_framebuffer *fb =3D plane_state->hw.fb; @@ -1327,6 +1329,11 @@ static void intel_panic_flush(struct drm_plane *plan= e) =20 intel_bo_panic_finish(intel_fb); =20 + if (crtc_state->enable_psr2_sel_fetch) { + /* Force a full update for psr2 */ + intel_psr2_panic_force_full_update(display, crtc_state); + } + /* Flush the cache and don't disable tiling if it's the fbdev framebuffer= .*/ if (intel_fb =3D=3D intel_fbdev_framebuffer(display->fbdev.fbdev)) { struct iosys_map map; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i91= 5/display/intel_psr.c index 8bee2f592ae7..73bdc54d7831 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2889,6 +2889,26 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_= state *state, return 0; } =20 +void intel_psr2_panic_force_full_update(struct intel_display *display, + struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); + enum transcoder cpu_transcoder =3D crtc_state->cpu_transcoder; + u32 val =3D man_trk_ctl_enable_bit_get(display); + + /* SF partial frame enable has to be set even on full update */ + val |=3D man_trk_ctl_partial_frame_bit_get(display); + val |=3D man_trk_ctl_continuos_full_frame(display); + + /* Directly write the register */ + intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val= ); + + if (!crtc_state->enable_psr2_su_region_et) + return; + + intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); +} + void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i91= 5/display/intel_psr.h index 0cf53184f13f..9b061a22361f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -57,6 +57,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state= *state, struct intel_crtc *crtc); void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); +void intel_psr2_panic_force_full_update(struct intel_display *display, + struct intel_crtc_state *crtc_state); void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *cr= tc_state); --=20 2.49.0