From nobody Wed Oct 8 23:07:08 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8E332580D1; Tue, 24 Jun 2025 08:26:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750753603; cv=none; b=gPuifzIsJGvdkFX1DGtMbTCb1C+BUqUMg9fwtaTBl+p90orbMNAFLTHV6F+zhpsgtmOo5douEwy5QiDgFOM7IG5yFLDDUAsqowpApNAk8+dZWwrxA6PGNIPN1HWOrFx9O9k/ZCcXXvwgBiL3k4yAmTQYTdjrNgRpvwIvEjRRLy0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750753603; c=relaxed/simple; bh=pB6TeHVvGW/lzTRG9TVHTLZMxp/beOWTtzRN2s2zK5c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MsGZ3YV0uC7X8v7sPv3f0hU2xKlsmotK/OMrRYJV8fynhzilAGy/iWVUFXa8osDhdtcw4YrrBEewXD2SbuUcZl/IS6YYPTzn149lf45u4QcwVZrX+0cw/0DX6m4U8J8V2typssp1myGHqtNS41P++HFufRJLOwwtgKz8MryGc0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=En39445K; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="En39445K" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55O8QWcs1109074; Tue, 24 Jun 2025 03:26:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750753592; bh=0qhBswGbMNvWeYkOf/T6ZsXPUsq70ZJr1FxaO+nhZus=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=En39445KDBwj46er6sRdmKv8GSsXSiTcVdQRj5bfsCvSnH5N4lmUYvUw10+JCNl54 jhzkVOF5eC+B2hNFzFK7I3vv7hoSw/HZr9ZB/NwNIXJXCmiAfcXtfASp/2ynqEZ2Bj 8nb8a7tx3276jus5cdJimfpZD/Stw4BO1qSXoLQo= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55O8QW1R1551313 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 24 Jun 2025 03:26:32 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 24 Jun 2025 03:26:31 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 24 Jun 2025 03:26:31 -0500 Received: from localhost (jayesh-hp-z2-tower-g5-workstation.dhcp.ti.com [172.24.227.214]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55O8QUJG1448073; Tue, 24 Jun 2025 03:26:30 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , Subject: [PATCH v2 6/7] arm64: dts: ti: k3-j721s2-common-proc-board: Enable DisplayPort-1 Date: Tue, 24 Jun 2025 13:56:18 +0530 Message-ID: <20250624082619.324851-7-j-choudhary@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624082619.324851-1-j-choudhary@ti.com> References: <20250624082619.324851-1-j-choudhary@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Enable DSI display for J721S2 EVM. Add the endpoint nodes to describe connection from: DSS =3D> DSI Bridge =3D> DSI to eDP bridge =3D> DisplayPort-1 Set status for all required nodes for DisplayPort-1 as 'okay'. Signed-off-by: Jayesh Choudhary --- .../dts/ti/k3-j721s2-common-proc-board.dts | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 793d50344fad..efe857a50bb1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -93,6 +93,29 @@ vdd_sd_dv: gpio-regulator-TLV71033 { <3300000 0x1>; }; =20 + dp1_pwr_3v3: regulator-dp1-prw { + compatible =3D "regulator-fixed"; + regulator-name =3D "dp1-pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */ + enable-active-high; + regulator-always-on; + }; + + dp1: connector-dp1 { + compatible =3D "dp-connector"; + label =3D "DP1"; + type =3D "full-size"; + dp-pwr-supply =3D <&dp1_pwr_3v3>; + + port { + dp1_connector_in: endpoint { + remote-endpoint =3D <&dp1_out>; + }; + }; + }; + transceiver1: can-phy1 { compatible =3D "ti,tcan1043"; #phy-cells =3D <0>; @@ -563,3 +586,69 @@ &main_mcan5 { pinctrl-0 =3D <&main_mcan5_pins_default>; phys =3D <&transceiver4>; }; + +&dss { + /* + * DSS on J721S2-EVM supports DP on VP0 and DSI on VP2. + * These clock assignments are chosen to enable the following outputs: + * VP0 - DisplayPort SST + * VP2 - DSI + */ + status =3D "okay"; + assigned-clocks =3D <&k3_clks 158 2>, + <&k3_clks 158 14>; + assigned-clock-parents =3D <&k3_clks 158 3>, + <&k3_clks 158 16>; +}; + +&dss_ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + dpi2_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg =3D <0>; + dsi0_out: endpoint { + remote-endpoint =3D <&dp1_in>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpi2_out>; + }; + }; +}; + +&dsi_edp_bridge_ports { + port@0 { + reg =3D <0>; + dp1_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + dp1_out: endpoint { + remote-endpoint =3D <&dp1_connector_in>; + }; + }; +}; + +&dphy_tx0 { + status =3D "okay"; +}; + +&dsi0 { + status =3D "okay"; +}; --=20 2.34.1