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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:14 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 07/10] coresight: tmc: add prepare/unprepare functions for byte-cntr Date: Tue, 24 Jun 2025 14:04:35 +0800 Message-Id: <20250624060438.7469-8-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfX8ZROFmVE6r8D D20MAp4tpqNV3NN0Wy3EtBNj+Xo+0vLkgiyOaOgr0/gYqnVEtoQ0npSpaSd2nuADnftkJg40XEF 4ua0apbD4O+6gOs9OWDgMyUbIiBmqM5LURHKCjrhEklU6fGB+a4mIoNcBANOLteLSWuW5DconPh m+ayZP9GHcoFWp/0oLieDMS/98ecIuYnSB/RhP8Sz0fnVKB8eaAgAREyNcTNBiNZevY5UKoMrUP V3hvWYaidwtcKBWG+Tq2DBZgYkSF1nuQ9Vc1lTF/D4EJabGCfEEUplZEj4808uCB2UO1uB7RK9Y c3TKz6HHuEigWNWaVcB62wNnI27Bn8PdSuPmhcJ3OSQJanKo4UHvpTyAgwYlQHhl2Z7p4wTv1Yk szgndbsrv8D5zk+aYPaOxiRW1V7UkMlk/FlIUUmCVldKjE1b2Wpxwz8lQHqYCOu2Kj5MekpG X-Proofpoint-ORIG-GUID: ozN6YcCRPw7jvGm162_8_4yyAxjjzkwm X-Proofpoint-GUID: ozN6YcCRPw7jvGm162_8_4yyAxjjzkwm X-Authority-Analysis: v=2.4 cv=A8BsP7WG c=1 sm=1 tr=0 ts=685a4023 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=xC7plfDI9GgKYcT3xssA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=799 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 suspectscore=0 mlxscore=0 clxscore=1015 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Content-Type: text/plain; charset="utf-8" Prepare for byte-cntr reading. An additional sysfs_buf is required to receive trace data, as byte-cntr always reads from the deactivated and filled sysfs_buf. The unprepare function releases the additional deactivated sysfs_buf allocated during the prepare phase. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 38 ++++++++- .../hwtracing/coresight/coresight-tmc-etr.c | 79 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 8 ++ 3 files changed, 121 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 8531bac79211..40605310240d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -229,7 +229,11 @@ static int tmc_prepare_crashdata(struct tmc_drvdata *d= rvdata) =20 static int tmc_read_prepare(struct tmc_drvdata *drvdata) { - int ret =3D 0; + struct coresight_device *helper =3D coresight_get_helper(drvdata->csdev, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); + struct ctcu_byte_cntr *byte_cntr_data =3D NULL; + struct ctcu_drvdata *ctcu_drvdata =3D NULL; + int port, ret =3D 0; =20 switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: @@ -237,7 +241,18 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdat= a) ret =3D tmc_read_prepare_etb(drvdata); break; case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_prepare_etr(drvdata); + if (helper) { + port =3D coresight_get_port_helper(drvdata->csdev, helper); + if (port >=3D 0) { + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + } + } + + if (byte_cntr_data && byte_cntr_data->thresh_val) + ret =3D tmc_read_prepare_byte_cntr(drvdata, byte_cntr_data); + else + ret =3D tmc_read_prepare_etr(drvdata); break; default: ret =3D -EINVAL; @@ -251,7 +266,11 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdat= a) =20 static int tmc_read_unprepare(struct tmc_drvdata *drvdata) { - int ret =3D 0; + struct coresight_device *helper =3D coresight_get_helper(drvdata->csdev, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); + struct ctcu_byte_cntr *byte_cntr_data =3D NULL; + struct ctcu_drvdata *ctcu_drvdata =3D NULL; + int port, ret =3D 0; =20 switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: @@ -259,7 +278,18 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvd= ata) ret =3D tmc_read_unprepare_etb(drvdata); break; case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_unprepare_etr(drvdata); + if (helper) { + port =3D coresight_get_port_helper(drvdata->csdev, helper); + if (port >=3D 0) { + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + } + } + + if (byte_cntr_data && byte_cntr_data->thresh_val) + ret =3D tmc_read_unprepare_byte_cntr(drvdata, byte_cntr_data); + else + ret =3D tmc_read_unprepare_etr(drvdata); break; default: ret =3D -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 4609df80ae38..2b73bd8074bb 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -2032,6 +2032,85 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvda= ta) return 0; } =20 +int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + unsigned long flags; + int ret =3D 0; + + /* config types are set a boot time and never change */ + if (WARN_ON_ONCE(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) + return -EINVAL; + + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_SYSFS) + return -EINVAL; + + /* + * The threshold value must not exceed the buffer size. + * A margin should be maintained between the two values to account + * for the time gap between the interrupt and buffer switching. + */ + if (byte_cntr_data->thresh_val + SZ_16K >=3D drvdata->size) { + dev_err(&drvdata->csdev->dev, "The threshold value is too large\n"); + return -EINVAL; + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (byte_cntr_data->reading) { + ret =3D -EBUSY; + goto out_unlock; + } + + byte_cntr_data->reading =3D true; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + /* Insert current sysfs_buf into the list */ + ret =3D tmc_create_etr_buf_node(drvdata, drvdata->sysfs_buf); + if (!ret) { + /* + * Add one more sysfs_buf for byte-cntr function, byte-cntr always reads + * the data from the buffer which has been synced. Switch the buffer when + * the used buffer is nearly full. The used buffer will be synced and ma= de + * available for reading before switch. + */ + ret =3D tmc_create_etr_buf_node(drvdata, NULL); + if (ret) { + dev_err(&drvdata->csdev->dev, "Failed to create etr_buf_node\n"); + tmc_delete_etr_buf_node(drvdata); + byte_cntr_data->reading =3D false; + goto out; + } + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + atomic_set(&byte_cntr_data->irq_cnt, 0); + enable_irq(byte_cntr_data->byte_cntr_irq); + enable_irq_wake(byte_cntr_data->byte_cntr_irq); + byte_cntr_data->total_size =3D 0; + byte_cntr_data->irq_num =3D 0; + +out_unlock: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + +out: + return ret; +} + +int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct device *dev =3D &drvdata->csdev->dev; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + disable_irq_wake(byte_cntr_data->byte_cntr_irq); + disable_irq(byte_cntr_data->byte_cntr_irq); + byte_cntr_data->reading =3D false; + tmc_delete_etr_buf_node(drvdata); + dev_dbg(dev, "send data total size:%llu bytes, irq_cnt:%d\n", + byte_cntr_data->total_size, byte_cntr_data->irq_num); + + return 0; +} + static const char *const buf_modes_str[] =3D { [ETR_MODE_FLAT] =3D "flat", [ETR_MODE_ETR_SG] =3D "tmc-sg", diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index f6b05639aeca..f95df0a34ad6 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -14,6 +14,8 @@ #include #include =20 +#include "coresight-ctcu.h" + #define TMC_RSZ 0x004 #define TMC_STS 0x00c #define TMC_RRD 0x010 @@ -357,6 +359,12 @@ extern const struct coresight_ops tmc_etr_cs_ops; ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, char **bufpp); =20 +/* Byte-cntr functions */ +int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data); +int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data); + =20 #define TMC_REG_PAIR(name, lo_off, hi_off) \ static inline u64 \ --=20 2.34.1