From nobody Wed Oct 8 22:33:20 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30A61238C2A for ; Tue, 24 Jun 2025 06:04:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745092; cv=none; b=J9lRDbUkRRLdkLYekcgvOL7F3VP8pJKgTFAYxZZDdNZa05XiM6CHcdvyvhyAXy/L8vew7rs1tSfZGLUS8qulzbq5sJ9Kst+ImeOup6PY8tgSdeRkiqXdr6yCjW3jy3CKYKZAjA/NFm+J69+ZfP+lUVRFaPjHT/tExPpJxv3+xxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745092; c=relaxed/simple; bh=n3EaXaaNhWYWmkdCOUG9x+pdcHBoegUPElZCXFPVc0k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FNcRYvJ/OQkWRjLWvF3h3EOpMzV0NsIQf9HPHdWJ6beY1e4rCcq4xh9WtUH4uJd0mFPqCaxcQKCEJg8ijlnBhyA8qElA0s6R7JhHLi9VLxtC2HGaKI65tZj4H+vSdx+/EOZaiWK4gGnKJaikTiSKSeIKOqi74QDy2TODB8E+Jy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=TyhHVy5r; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="TyhHVy5r" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NKljU5013198 for ; Tue, 24 Jun 2025 06:04:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=SXDZmqpfj9O i17S+KvFoTK0GaAZ2Kfc438E97avizmc=; b=TyhHVy5rcxyPvLe/sRdeKCTKrzN qRApGnsNnaQf/VpGRLGJ3oUoWTW+DYHp6U+l7V+Flfx2eHPBQ55pPZdfAbgoz+ud Cohw3Ebp+ORsQebZD3culedijJ6er9q8F+7JV2D3CRQn4O1ohiLNMF1UNGPqCe5H voC96rCJa4PRb3fs8iQ8vuHG+65M5Gp2fMhBRoUlqZFyumsyejebSdevU9w8oYkY nrZwPo9z3zo56l7832wQh9ZNZc78zZwBR+w02RRij6k4m+A3xEsYEGHvg6+AdeLt X6Etjs3m4sL5Be+WF8r9PkwwqeDS8ZI0AZCjCYiPcsQoY7iWQruZjlNzX/g== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47fbm1sfbf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:04:49 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2356ce66d7cso64060255ad.1 for ; Mon, 23 Jun 2025 23:04:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745089; x=1751349889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SXDZmqpfj9Oi17S+KvFoTK0GaAZ2Kfc438E97avizmc=; b=MuUu4gTJIkzPZpxSOietyBGvwClEFp/K/2kxQ/CuQzCBWYH4WPy7m82Rz581U96lwn sNsK3/+6Espljwcr8ETw3Ao1CNProowNnRW1F6lKFDFZ47ctSnDEO1Jrlp1cO+9GQtW6 GCsxzhxsN9got38MThp0mEBHJhxmULBbD6O3PDNyqO+l038QXBwk7Wxe4trm+cEreImi G1DWKkOXzmOtwDWCwyYgjG6VyKY0k4+EeTdqcYwrEf8OIm0hUOiajI1uI9qhLnpOgyzP RbQc/rLxG9hk7xQyzxl9Vwz3rqYLpvsDvEwj0w+bujMuD52DaJnEMg7ZjDi8w2duoWtO 5AzA== X-Forwarded-Encrypted: i=1; AJvYcCWdJyaUnfkjRoqRpUuKu0bEbwcWhqTNfwvoSiCX/fvVRXSNUqSwITy85ePLqtB9ayfsWQ6VZQ33thjLn0o=@vger.kernel.org X-Gm-Message-State: AOJu0YzNgWPeAB1/KghGnHNbKtZ8VNQI1e6rokWH2hsjCqYv6BfM6hVc F1xaOXeKlSqRFaM6CrmT+Fd8itUs08+7KH68EMg+7yEWpAwNHpm1GN59rwIeKqmD+MiHySfEmmB MsjNoRAEJU/kYowEiEkk+uU+lniWurE8/Shlo0hOaRICq7N+ewh2QBkQW+DBjvPUY8EY= X-Gm-Gg: ASbGncupE75bHYptBn7hUqH4K/JVTGxEeToK2E2DhSeQggw6hnmXz0zfqXBa6CxU5Ys RJaHCfMV9vZPtxYKo8BYIki8HNae19ASh9j8vXSh8oRH1XXkDXXhRqyKUMVYUjiXhfMtoUMmepa nl+QuWaEJ7SFySgUPCKV77r76913cv13yVmJyGAUhPBrUiqzQjAxpiSgUToX9j8f5e7/cEh5NnD Nic+An50RUU7z5Z1pt7u8p6U+hzxgxunMvf5DGrpu7GYjdwYrHGc520Ps7k4dzUAuOuFvcyfJ33 PedZ96zrlSTlykgDGdLDyW6EnzRGQUwG0nPHJjA7DgWNDqivU7K7aYmj6L2tHDQo24uy7h9at9P HEg== X-Received: by 2002:a17:903:18e:b0:234:9094:3fb1 with SMTP id d9443c01a7336-237d9a7321dmr269831005ad.35.1750745088743; Mon, 23 Jun 2025 23:04:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGHGFVEgHMh2e65wgJoSytM+YbUXaFUdaLymaIwIAsqFFbJ5e27Dt9FJEOhG05p9+rpg/ktWw== X-Received: by 2002:a17:903:18e:b0:234:9094:3fb1 with SMTP id d9443c01a7336-237d9a7321dmr269830575ad.35.1750745088368; Mon, 23 Jun 2025 23:04:48 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:04:47 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 01/10] coresight: core: Refactoring ctcu_get_active_port and make it generic Date: Tue, 24 Jun 2025 14:04:29 +0800 Message-Id: <20250624060438.7469-2-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=YYu95xRf c=1 sm=1 tr=0 ts=685a4001 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=UMME_An3wchvczm7DuYA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: f9CsWN7kqW20JKiw8HuXlOzMYZSLo57e X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MCBTYWx0ZWRfX758tkh7J3Wo+ 86+GuA7wMN8rI96xvq0uJRfEI3nIUPr+l3Mv5YbIl3xUwhnI4jZGBS+mBF4rz+RJXm3VNwTsEgx /ZRChL9ozJuSV3qdlsXcXZ/PFZbWKZQ41v4r4SFkgF6tZ0woNHsw588iVmITKEI+YJ66vWRHU1r ZnuN6U9jK34tWZ9cOUfQEego13bINMLBoPtH5J3kPhsqM65iQ/wsk06MPdhitgW3FEEAFefVLOo Xrx98nrqTokJcqRiUnTSyEeQxFq6TUfWrPohOaqMrgzIvRwb5ERQAgFR4I5N8M5Aihyk//GlM01 CWkEC2krw8a6sfJeo+MPzpwX1ne92sfNv9AuZB+NwZLGCQYHRxq+/KmsdocLlsNWuphkFl/Jg64 25fhjAIzIGs0eceCupzkDSvQNgBokeeGGt89fJh8g5KKpDB0OlTNl/VDFMYS9TEi+msFRKJv X-Proofpoint-ORIG-GUID: f9CsWN7kqW20JKiw8HuXlOzMYZSLo57e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 clxscore=1011 mlxscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240050 Content-Type: text/plain; charset="utf-8" Remove ctcu_get_active_port from CTCU module and add it to the core framework. The port number is crucial for the CTCU device to identify which ETR it serves. With the port number we can correctly get required parameters of the CTCU device in TMC module. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 24 +++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 19 +-------------- drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 3 files changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index fa758cc21827..8aad2823e28a 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -579,6 +579,30 @@ struct coresight_device *coresight_get_sink(struct cor= esight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); =20 +/** + * coresight_get_port_helper: get the in-port number of the helper device + * that is connected to the csdev. + * + * @csdev: csdev of the device that is connected to helper. + * @helper: csdev of the helper device. + * + * Return: port number upson success or -EINVAL for fail. + */ +int coresight_get_port_helper(struct coresight_device *csdev, + struct coresight_device *helper) +{ + struct coresight_platform_data *pdata =3D helper->pdata; + int i; + + for (i =3D 0; i < pdata->nr_inconns; ++i) { + if (pdata->in_conns[i]->src_dev =3D=3D csdev) + return pdata->in_conns[i]->dest_port; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(coresight_get_port_helper); + u32 coresight_get_sink_id(struct coresight_device *csdev) { if (!csdev->ea) diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index c6bafc96db96..28ea4a216345 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -118,23 +118,6 @@ static int __ctcu_set_etr_traceid(struct coresight_dev= ice *csdev, u8 traceid, in return 0; } =20 -/* - * Searching the sink device from helper's view in case there are multiple= helper devices - * connected to the sink device. - */ -static int ctcu_get_active_port(struct coresight_device *sink, struct core= sight_device *helper) -{ - struct coresight_platform_data *pdata =3D helper->pdata; - int i; - - for (i =3D 0; i < pdata->nr_inconns; ++i) { - if (pdata->in_conns[i]->src_dev =3D=3D sink) - return pdata->in_conns[i]->dest_port; - } - - return -EINVAL; -} - static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct cor= esight_path *path, bool enable) { @@ -147,7 +130,7 @@ static int ctcu_set_etr_traceid(struct coresight_device= *csdev, struct coresight return -EINVAL; } =20 - port_num =3D ctcu_get_active_port(sink, csdev); + port_num =3D coresight_get_port_helper(sink, csdev); if (port_num < 0) return -EINVAL; =20 diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 33e22b1ba043..07a5f03de81d 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -156,6 +156,8 @@ void coresight_remove_links(struct coresight_device *or= ig, u32 coresight_get_sink_id(struct coresight_device *csdev); void coresight_path_assign_trace_id(struct coresight_path *path, enum cs_mode mode); +int coresight_get_port_helper(struct coresight_device *csdev, + struct coresight_device *helper); =20 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) int etm_readl_cp14(u32 off, unsigned int *val); --=20 2.34.1 From nobody Wed Oct 8 22:33:20 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A3EE19AD48 for ; Tue, 24 Jun 2025 06:04:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745097; cv=none; b=jhFk9jFhgwZMzldTeA/Iiw9dc02ELelA8+0pVbVPpdRmJOSCvQh+74H9TvpZrkDeCmxUpTtLobj9IBX7EQuPdq4ahcz7NIm5Ygg8b71K6E7NAHiv+hnlgPcFr3F1rf3/kCaliqdn0vtir0WXhtwVxJEcaZ52MrpRPn1DmAUk2BE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745097; c=relaxed/simple; bh=klaYK/ndNGf2Zd+yYu/jis1akITo3BCwGWiGHVFp7+s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KVNZs8SEYtIBjYCQFwMN5vHYGMKS2XB9+XVNlA9hVft1+LLVBzMgIi0efhyrDl9bJxTBpHxcxKriWuKtHnkmaLSkfN0rybKDz1kYxIT2wZV+YZQT+AalyUHJCZzjASNf+78fzSx8lODU3CdA+4sC707upmScWEf+nrlS2fO7Uww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=iiNcGhzM; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="iiNcGhzM" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NKlJVS014676 for ; Tue, 24 Jun 2025 06:04:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=NEd0bdzHNq+ BYGf2pvWM9XNZngsnetWAYruQNmk3PFE=; b=iiNcGhzMZ8TS0FOfsVcLD+w+QEb bYnUIlEVPMnkQer7sJIXA/g4O3nAMq+vRVN2LfghQvBn0D+V0Zj3E7t+jsD5L3Pw Mv5mgFPXD2sGGEYcySuu1SIo+WIk6O5FyOftob7y+yc3XIoIV/wtGWETsrbF+iH9 +fQOKeRD03d8SAngv2gMGTikDy92vbeX9NCe+oSRtNLTI+DXgdKPRVk7UppuKmuQ 7/u9PFP2g9Qs6gkrw9JKlvS4fWiDKIC0l6JlyRZHjXwZhQQN/yhtGv8cshH7zQGP CAYMjFSfK4Fxh7Q0ILpchN5fcp/L0YqnQU+ckd0afAfRKS/Mk47OLq0PsWw== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47f2rpu5pj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:04:55 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-b1ffc678adfso46024a12.0 for ; Mon, 23 Jun 2025 23:04:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745094; x=1751349894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NEd0bdzHNq+BYGf2pvWM9XNZngsnetWAYruQNmk3PFE=; b=AwdULegpbcZ3OVDTWBYLqWQIFPPTUlr+8DiiKAEgH6ulAxOvQU9DxNy8Qttt/ZKRpO u15jDM5JdUwMFG6OkP0poEiRwx41hF4748S7ruVn/xCinPp77riPUI/gxzexQFE5RI+A poEbqq8QGR/nEt+hxZXQ5O86ZFXqA9QGtsDrwnDA3VeOabpJij/HlZXCYzV8azWTjFEc GGGLeeUOdTWg6Uy+KmZs8XYfqkgQjskl8lOiR6iTPhYRFy1qBIqqHs+THAD9AnLw8ivQ VIMPieEebVFIcgT+W6JwLp1VCFtm0yvvpkg0XC9u1hiFA3uxwwUQJU3v4tnAFMDjBfCB jcpg== X-Forwarded-Encrypted: i=1; AJvYcCU9ZQuF3w8LTwKoAiLxXaKhRXvvpj4NK1+0kI5wkCQTR+ErYU8LfWJ6CmKiqxiCVOSn4uKz3cQG99j9ydI=@vger.kernel.org X-Gm-Message-State: AOJu0YwW/vMyPdymuwxBn42rPcS5SIlaZP02CAYq/JSZVS1TD88QhNfT eqtibV8qxDQoRPVsPu2e1wrzvb48FiPOu/N4NdaP0OEQ8HFvn2bgk04NmXkFkgDd8KLMOXY2lhQ BKsOeHEUpNr+JxslyM757DMf34dT5q7mQrW94AnuWemeq66sZ/wwiS1Rhqp5sz9tBpdeTCScyLF 8= X-Gm-Gg: ASbGncuUzxYkl8tqXStEqw1Budy59maOfYm14l/dPwbuo6Nl111iEdNxsPQ+lwM5Ep9 EE4u/q+2pB8gqcJ3BtOq11Garii4hGKuytQBbGpNsljw+kfDlGW9IxHuxmX916vLoftOOzffwgJ eWTVn+8k6a+nxAT3Nw5M18MsiIhY/t2tTHxCgFtRtZeX8awsh1uxL/Zv3R8K8HKHrfeBw4o1uXv W3x24VSzETqieZcvPDkdjVxuZDqVRjJO+Q8IooBm2ovGGExvmKsCwhJwYBMdRd+6haf0fM+Bz5R BDN8u/ryvXqUmgrMldPnkVjMqfB2N/tNsHd5fQ+n9Idv8Mtp/I2eVUomUJkoWPdDL+jkTqpkAye 69w== X-Received: by 2002:a17:903:2a85:b0:235:eb8d:7fff with SMTP id d9443c01a7336-237d986d5f7mr223071205ad.28.1750745093720; Mon, 23 Jun 2025 23:04:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHoXzDNPCywsWid/86csyo6/oaM8zIDmOlMe4ad7FzFQmavchj+MmL8XVQyf1Oz3B2TnpP03w== X-Received: by 2002:a17:903:2a85:b0:235:eb8d:7fff with SMTP id d9443c01a7336-237d986d5f7mr223070365ad.28.1750745092828; Mon, 23 Jun 2025 23:04:52 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:04:52 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 02/10] coresight: core: add a new API to retrieve the helper device Date: Tue, 24 Jun 2025 14:04:30 +0800 Message-Id: <20250624060438.7469-3-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=NdDm13D4 c=1 sm=1 tr=0 ts=685a4007 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=Bv2r1u00ER1ubdDhqu4A:9 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MCBTYWx0ZWRfX9tC0IDmx9iG/ 4Y+NhhkuKR4EiV2+rkLKAQDWCxpCsKiPPLtuIJPKtxnof6JvPHjwMTQB3GJ+BhcTkpqordXSOvC rga1wepksaAkE1s3JZ7q9QPJndgS7UUnwBQQTkRYy4NGOIgbplZ/y5sYB9d6jElBo81yV7MIAxS nafz2I92ow60izTxiRuK+x/w9hA3ZD/a/kHCx5nm92wCd9IgPgo0OdjRYl30KQx3AfHT8xShw5K 1ll92jf4m7lldkOfrOsDQyNCNExjjKQx4Sel9+UEtlY7CjRKDZ2GE8YSo9noLCn1P0s2OU2r8Me Vyi5W3XmtcYqWNJDyGKjkQsiPFWjVUY5wMppLTBZ41ETfyPx/VPn+QyUj2UAVViFKDjEaAgk8zw 9jGS3NedLPoIQfD0O93TF5fukWriPBbklnf9lTBQALR4oFG3unC5AKrH1eHBm1KXpFRQMKn4 X-Proofpoint-ORIG-GUID: CJEB4nLQEUQ4Av-EyUr4fHIDx33JLoat X-Proofpoint-GUID: CJEB4nLQEUQ4Av-EyUr4fHIDx33JLoat X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240050 Content-Type: text/plain; charset="utf-8" Retrieving the helper device of the specific coresight device based on its helper_subtype because a single coresight device may has multiple types of the helper devices. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 30 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 2 files changed, 32 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 8aad2823e28a..c785f8e86777 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -579,6 +579,36 @@ struct coresight_device *coresight_get_sink(struct cor= esight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); =20 +/** + * coresight_get_helper: find the helper device of the assigned csdev. + * + * @csdev: The csdev the helper device is conntected to. + * @type: helper_subtype of the expected helper device. + * + * Retrieve the helper device for the specific csdev based on its + * helper_subtype. + * + * Return: the helper's csdev upon success or NULL for fail. + */ +struct coresight_device *coresight_get_helper(struct coresight_device *csd= ev, + int type) +{ + int i; + struct coresight_device *helper; + + for (i =3D 0; i < csdev->pdata->nr_outconns; ++i) { + helper =3D csdev->pdata->out_conns[i]->dest_dev; + if (!helper || !coresight_is_helper(helper)) + continue; + + if (helper->subtype.helper_subtype =3D=3D type) + return helper; + } + + return NULL; +} +EXPORT_SYMBOL_GPL(coresight_get_helper); + /** * coresight_get_port_helper: get the in-port number of the helper device * that is connected to the csdev. diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 07a5f03de81d..5b912eb60401 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -158,6 +158,8 @@ void coresight_path_assign_trace_id(struct coresight_pa= th *path, enum cs_mode mode); int coresight_get_port_helper(struct coresight_device *csdev, struct coresight_device *helper); +struct coresight_device *coresight_get_helper(struct coresight_device *csd= ev, + int type); =20 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) int etm_readl_cp14(u32 off, unsigned int *val); --=20 2.34.1 From nobody Wed Oct 8 22:33:20 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D140235360 for ; Tue, 24 Jun 2025 06:05:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745102; cv=none; b=kJI9yT19omyx/yNrc4Z4wM33xPsJ97iCXLx31ugTiTkP165BFgX9+2mv9hCr3udU35Ru7C6aGpnU5KzSb5d4Iq/4quBhKWVYYbhy5SK9PMGa4wWhWkP74VxUDZGmFjMH5VWMTNja21ud6uTZ2yQoccOTCCKNg5Qjygq0C6Yi70Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745102; c=relaxed/simple; bh=/g0/ZP4wHtHkgn87d1qyuSHaHZRS6iAOtiw3E5bQBKQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MIU8WoMTsOKGbqzOnKYF6xJGFybTrUwsM7pBMNgtZCCdW6TLS7Zda9BFueh9RqYDt6I3kzzlPhmKNeUEInlP4o3e1rblHOYiy6h80ovEzHk1owhi9KQ6NsCr8iC1aDfjK6m6+B+ZVuKjx05qQ9mbBkwsNrjQ7WiWYLz4vMrPs+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nqBAxHyD; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nqBAxHyD" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NKlXjB021092 for ; Tue, 24 Jun 2025 06:04:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=0SmpNFp+B8v w9+MbCCEs5ee5DB9AM9lfQmDfPKr7t7U=; b=nqBAxHyDFBaUQe7lELFAaV1X57k iE3MPmBjSgHZOhVws0HedSNThOc94RrczqMNOIuhdwd7kagpGwcFwAHH7vGMcAih NC2JxpwX2Y8fpw+gUeLtSb5XckodLvlB4xd6BDvA7vccfbnYSS+W4O8r4kg7Jbnx AQqB0DULZBJja8EvHvxM50WMpurVsl4kFY9zDW8vnGcf0aQ/ScFMnwjqFAsT/IfT D9Uy1qzGcN/HEgta/a8i3DCYRzTDG2wpwjXR0Pjx+DOJ50eb6TmFhL3vJ4s5y5S5 bWL36NN2nF5fIgw5O5SEZ881FFrG+PE5UgxxcUrXHL3jcnjfrxqUez2eYyg== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47fdfws55b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:04:58 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2356ce66d7cso64064785ad.1 for ; Mon, 23 Jun 2025 23:04:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745098; x=1751349898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0SmpNFp+B8vw9+MbCCEs5ee5DB9AM9lfQmDfPKr7t7U=; b=sdLdEKffssoI9EkogtR7AHT+EuSCN85+JL5s1Bg9rQCT5VNP7bxjD48HB/kuZrDupa sXn73mmuozutQQJsSH8hpTWy1csXgqvYW0C/XzRREg+qJEDXoaSIaGA4p7MuNguLH/1s A/gIVR15rf/tJZvmm/B6spS9nYHKiwrCbOO+U5D1kbe94CZfugtLrrOzvcJQ9Z+omT6j 5M5FAPigKQzzEmuQUrhBW+O9mMhOCJkyFDlyWXTksu1g9FUcakSzwRWo6bHpAYWWl7g6 WFBjmqz8e5+eiaAg7afvYQYsrW5lwYvIZJ7JUiQbNJvJefVmOQee765u/NqT35Yac5VO 0anw== X-Forwarded-Encrypted: i=1; AJvYcCUO7dRQwexPcKZQDV7qBMlHwDUIC1rc8DFqhxfNg9Pn3zF6pTaeMkvGcHYSkm/jhCHlKOQkbTDuLLTJ428=@vger.kernel.org X-Gm-Message-State: AOJu0Yy0epO20q0ujOoT6Na4DkgoOfIhodcBxnsNwyIECnKo5RPAHq4s x2PMLatzNPXFwlsEZ/IcZKeIZMmRf/oDWHSRNjZ5YoLSKav9DRwacPiPkJUmVEY3WyDVMur8vau nQZVBCHVeQNAaptyR93a0LbHP3TynpocfzolyJ/R/oNPJGz+Ipa31zYm6WOlPa/aoJRU= X-Gm-Gg: ASbGncsLjU5SY1EFEabn6bqC5W1/+U6vuDzn9Mz+xEVCDpLpC+KCkg4kOA+146C5qo8 Yg9aHdSVsLjEjbDH/ILP4q7PN6khHUGuIYPWoD6cs3itD6SIxLPJKC+D2CVCrW6EsrpcbnnFTUn 7ziVTJd8BWnkgcVjECR9OzdYMGLfMYb0+RteairnrhAYF9ry4+/sAFiUMqjoqztcJt2Jnt3gatR AtBXkGSVsSmk3kE/dkyFa1y5TcwXmwBU0Rvz4hftqApnVsSz9ctp5IEmn08IJXai4sDivCqIQCw D8rfhy4q38liZMsvNhDGG94vbdViUIAJvNB89Z/HW+DAkRCjKo8kalzQhU2fDpFCxxjWpgRUcim wMw== X-Received: by 2002:a17:902:ce0c:b0:235:15f5:cc30 with SMTP id d9443c01a7336-237d97d1abamr276912195ad.16.1750745097815; Mon, 23 Jun 2025 23:04:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHkSv1e6yZscpoifQQotP3Hcj8oMsbM5jLX5umPQVB1S7t8NeSUBaboum0YltNjUtaGRZQVxQ== X-Received: by 2002:a17:902:ce0c:b0:235:15f5:cc30 with SMTP id d9443c01a7336-237d97d1abamr276911685ad.16.1750745097450; Mon, 23 Jun 2025 23:04:57 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:04:56 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com, Krzysztof Kozlowski Subject: [PATCH v3 03/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Date: Tue, 24 Jun 2025 14:04:31 +0800 Message-Id: <20250624060438.7469-4-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: WaZsPnjqIpog2Tb1twsY0qn5v8Sr4fuQ X-Proofpoint-ORIG-GUID: WaZsPnjqIpog2Tb1twsY0qn5v8Sr4fuQ X-Authority-Analysis: v=2.4 cv=MtZS63ae c=1 sm=1 tr=0 ts=685a400b cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=gSyxy6DGYGa4b6s9XCEA:9 a=GvdueXVYPmCkWapjIL-Q:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MCBTYWx0ZWRfXx3GiHTp1UfdC yJVLqHWgcglZkeqvQ6hlshEVJu2Xqe7+IhRnx62qOevPYyswI8ZIVdkJEbFjO/fCCJzcdJ0WiIr fbACA9ly4LqIFuMPth/JoS5pjxYyjaHsNJOeRbQRwiSwoiFXdpdiGlpUTZdnfp8xacM/GJGD2pa tKSelwgxcZaYr+e2EXdku01TMUEN6VZ73qziuPcUN/Zn1DlLjBNQ3yrqpvM/FIuO9DedMA/Wg/e zL/PtmH9uoIGBOsSbDsqNBcBXAn5atgyrh7I2pyUZP70+0pfB4w2CdNZFp4y8v+CqIveaV2VUqQ xbXxiSBulki8YKq9gVWDROj8ZvkgrOuSJW5LP2ODZmV1Cr1TNxgL+S9i3kOijklpP/JxgL/fl0O qxgjmpWNeAg+HagAPElcGJIoS0Ofd/WjCQkx5UXEKQdjCh0OuA6/7Fmv4vTmhXk7ndzh1syg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240050 Content-Type: text/plain; charset="utf-8" Add an interrupt property to CTCU device. The interrupt will be triggered when the data size in the ETR buffer exceeds the threshold of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Acked-by: Krzysztof Kozlowski Signed-off-by: Jie Gan --- .../bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 843b52eaf872..ea05ad8f3dd3 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -39,6 +39,16 @@ properties: items: - const: apb =20 + interrupts: + items: + - description: Byte cntr interrupt for etr0 + - description: Byte cntr interrupt for etr1 + + interrupt-names: + items: + - const: etr0 + - const: etr1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -56,6 +66,8 @@ additionalProperties: false =20 examples: - | + #include + ctcu@1001000 { compatible =3D "qcom,sa8775p-ctcu"; reg =3D <0x1001000 0x1000>; @@ -63,6 +75,11 @@ examples: clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + interrupt-names =3D "etr0", + "etr1"; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1 From nobody Wed Oct 8 22:33:20 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E33C12512D1 for ; Tue, 24 Jun 2025 06:05:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745127; cv=none; b=DLZySJnG918quB+nvE3ys8faPnwnzZ1TuCh8ggCx4THOrHBAY9BfHLNI6lpt0r3v95yCjmibHsmHXSztNLLSZgYKEvnQWhtCgm4weYPg6zIrhkNtP5J8z0e1qDQs5WZ7zubym1gDBd7xnnfw2RhNkBi0fZ5/t6E2k+FcH0Ejnyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745127; c=relaxed/simple; bh=5BDyaO5qvoRI7D777OJH6jFF7abSY0MdP8gEMlwIo9Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FbMgFgKnQkZOQweUhlrsbkJfR1WzKgJrSQjm8gPJ5MUGsxy46sIFYiX58lxJw5lLI7FDfvr62j61i+ONnELhBPWutxP8GmpJ12HCco+p5eCuTz35fDCLgBi0zOSNs78NHGVpVcQZgpN4YhbTQksjan/rDZgyg1+a3Kwa4fwWm+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=dY8gmoSE; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="dY8gmoSE" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NHfEdj027585 for ; Tue, 24 Jun 2025 06:05:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=vu6hBGxLrwD FVrFDynAIBc/y5Yse2mQL+Dt9IjSV5yw=; b=dY8gmoSEjVPCcvR65pBpTf/OuAJ +JG2twjVGhJEdu5odXO/1faTkht76Jt5gKnyyz3LUBEbhl14KbKBWs6t+Tq/4gXv Vq0BPYhT8LggvD8o4er41IQ8IxrZ/JDnodVBxsEuiHEsKSDzR8UnEf6pNW6XAX2U iI35DsjD7cRcsfdCo3T2AjouD2jlCsd+otO/KB2Nf9clYK5vDwMq5Jd5Ptw1GKJl PADjn0rRVX2vRMItzP88i6IO2rSjOAzDmIsGhTnD/9IpvKZbeOAWw2386ZYLC1kU 5NWpi/bBni/q+aQ9AgUTzjYovXM6FvvhDDaFivil92SZm+KKsDT8Vj35oUw== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47fbhqhedb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:05:23 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-b2c36d3f884so3674806a12.2 for ; Mon, 23 Jun 2025 23:05:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745103; x=1751349903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vu6hBGxLrwDFVrFDynAIBc/y5Yse2mQL+Dt9IjSV5yw=; b=A64LPm2f5VY93nymBqeIH/sLX8njDqztfMIkHlaIswXoAxvDqU8MnddH11XAY7xWV6 PcWYOt3c0oJBQXqACNGwnVlzti6tpnhB2phnyXfdkt7Xwi70R9AKW4Do6Q/1kT0ltxzQ PUG2bPctUPZ6j/SL1ypaDaOl9uJjvyXXyL83j/4/mL8+QitKrDCfunCrPCRkBUaVDs0f Erd0VMWzWUapbSoMSH7IqErXnf28przNoegkntP0TAZ53vI/+5dClJ1vsOnc92fuJxa2 tx0Pralh5xXhtz8xf/LFKUwLkDqFxFblEj5nMFxUr0+L0LgA2EjHqFqWWg0l7xWAfgLk 71Mw== X-Forwarded-Encrypted: i=1; AJvYcCX0JGmuJ7N/Lw+UhnmRuDLRqp0vJJvjJMhj3HB6hixjcVJnjAgKLYEXKida5HMpK1LacD5UUj+F0A9368U=@vger.kernel.org X-Gm-Message-State: AOJu0Yyf8toFnOy4YAQXsMjuOoVV0gNOqAhQsJTJmAPlXa6pLLpvVfr4 kaJpg9v2BuFO992hgDy/r9EHSmiVOU1No5VVfQhDBkgT1PI/6oYR23Ue2kofXjpduBaq0qOvMdD b+Dq0T++m6hiXn46fbp0jpwEx+nkBKX7whwGcdCqk5U4c3Oe8VfjvZxssxucAMKIe4j8= X-Gm-Gg: ASbGncuoVtX5AffJfck55/eJG8MtKluLi23Q54DSAvPrKPwZ2uJzu8V8xIruATLe21I DvrQr1KqZDapXueA3vsvacUkdLCRCI0w45AbCoWvi1HXrBbGfSPdXNC0Xg16CJYLJQVlcUrg/8Y lo9JlImPxfMjoN7z1tVljcbRDrYmHS6y4Zb0k/MMKNsozHWCJnwATIRBaG+wtiSax4XLkUE2ALU 6QogHBhwad0Ry5VuuAnkPsC51gkxTfzW/DW0nIGGQo9pBq8oKRkNMON7AUJR1ZS1W5pCgAS+7pE 3HKzr9AwHSdbfhW2Q4IpSUojffxYmlLTp2ukSxmMWNbAllOOtkaSSXYS5CAhQFmkFrpQNKnkIW3 UTw== X-Received: by 2002:a17:903:4b27:b0:235:2799:640 with SMTP id d9443c01a7336-237d98e293amr193960205ad.25.1750745102478; Mon, 23 Jun 2025 23:05:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHHL7qVghofXpChagjQNlaDHNoeTmUHcsijUqIAEB1ZERotQCk7LBIFy/KUJtYU7QECk+VUpQ== X-Received: by 2002:a17:903:4b27:b0:235:2799:640 with SMTP id d9443c01a7336-237d98e293amr193959945ad.25.1750745102015; Mon, 23 Jun 2025 23:05:02 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:01 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Date: Tue, 24 Jun 2025 14:04:32 +0800 Message-Id: <20250624060438.7469-5-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: kfpyPTA5XlWaqImgFU6j5uagIlwp0D82 X-Authority-Analysis: v=2.4 cv=Id+HWXqa c=1 sm=1 tr=0 ts=685a4023 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=VuEiWhZmLyiD4YjWg_QA:9 a=bFCP_H2QrGi7Okbo017w:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: kfpyPTA5XlWaqImgFU6j5uagIlwp0D82 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfX7vNF3sumIIZb 7z42cRTsuh6l3nguQHvay9MBWpybKArxL/Ze7ejxU1HBidig/JBnfgTr9ZdZOnS1ijXxMZs84iG fe1AaJ5OvuMhehWtrH8hIpxxSBs4QemJBgN5Aj30Kbb3QNewI9CifIGf4dMvMT9vk0FzDwvUJ9Q ZyxDqeokQwqRsj9hXF2TujgtPDKGKuoKQi//qPqrsxBEqW+viAsJ29PjI/UuwMlbwFdinZVAVxM 4ApavxvaYOo+HlKXJW5U6WaOnE1iiO1bpc4BCr0GzNiEXuiuRIufdnOaHMYLae4gI/fRkz0QwsZ kPyOH8a6Z1o8OWAPOq+mChO26Smjh9/81FRXvDNG3pai3v4EWX9SC/DYf7luCcrM+v050CnzWO8 WHfGfODJLd7pM87LJ4p3m6oj3OtcklclX0945Rpcy4HNcLVmQxyNTzaOik32N/LGE69Na43J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Content-Type: text/plain; charset="utf-8" The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the ETR buffer. Signed-off-by: Jie Gan --- .../testing/sysfs-bus-coresight-devices-ctcu | 5 + drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-ctcu-byte-cntr.c | 102 ++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 94 +++++++++++++++- drivers/hwtracing/coresight/coresight-ctcu.h | 52 ++++++++- 5 files changed, 249 insertions(+), 6 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-c= tcu create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-ctcu new file mode 100644 index 000000000000..e21f5bcb8097 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu @@ -0,0 +1,5 @@ +What: /sys/bus/coresight/devices//irq_val +Date: June 2025 +KernelVersion: 6.16 +Contact: Tingwei Zhang (QUIC) ; Jinlong = Mao (QUIC) ; Jie Gan +Description: (RW) Configure the IRQ value for byte-cntr register. diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index 4e7cc3c5bf99..3568d9768567 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -54,5 +54,5 @@ coresight-cti-y :=3D coresight-cti-core.o coresight-cti-p= latform.o \ obj-$(CONFIG_ULTRASOC_SMB) +=3D ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) +=3D coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) +=3D coresight-ctcu.o -coresight-ctcu-y :=3D coresight-ctcu-core.o +coresight-ctcu-y :=3D coresight-ctcu-core.o coresight-ctcu-byte-cntr.o obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) +=3D coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drive= rs/hwtracing/coresight/coresight-ctcu-byte-cntr.c new file mode 100644 index 000000000000..d3b6eb7a89fb --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +static irqreturn_t byte_cntr_handler(int irq, void *data) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D (struct ctcu_byte_cntr *)data; + + atomic_inc(&byte_cntr_data->irq_cnt); + wake_up(&byte_cntr_data->wq); + + byte_cntr_data->irq_num++; + + return IRQ_HANDLED; +} + +/* Start the byte-cntr function when the path is enabled. */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink) + return; + + port_num =3D coresight_get_port_helper(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + /* Don't start byte-cntr function when threshold is not set. */ + if (!byte_cntr_data->thresh_val || byte_cntr_data->enable) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D true; + byte_cntr_data->reading_buf =3D false; +} + +/* Stop the byte-cntr function when the path is disabled. */ +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink || coresight_get_mode(sink) =3D=3D CS_MODE_SYSFS) + return; + + port_num =3D coresight_get_port_helper(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D false; +} + +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int etr_num) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct device_node *nd =3D dev->of_node; + int byte_cntr_irq, ret, i; + + for (i =3D 0; i < etr_num; i++) { + byte_cntr_data =3D &drvdata->byte_cntr_data[i]; + byte_cntr_irq =3D of_irq_get_byname(nd, byte_cntr_data->irq_name); + if (byte_cntr_irq < 0) { + dev_err(dev, "Failed to get IRQ from DT for %s\n", + byte_cntr_data->irq_name); + continue; + } + + ret =3D devm_request_irq(dev, byte_cntr_irq, byte_cntr_handler, + IRQF_TRIGGER_RISING | IRQF_SHARED, + dev_name(dev), byte_cntr_data); + if (ret) { + dev_err(dev, "Failed to register IRQ for %s\n", + byte_cntr_data->irq_name); + continue; + } + + byte_cntr_data->byte_cntr_irq =3D byte_cntr_irq; + disable_irq(byte_cntr_data->byte_cntr_irq); + init_waitqueue_head(&byte_cntr_data->wq); + } +} diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index 28ea4a216345..721836d42523 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #include "coresight-ctcu.h" #include "coresight-priv.h" @@ -45,17 +46,23 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); =20 #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) #define CTCU_ATID_REG_SIZE 0x10 +#define CTCU_ETR0_IRQCTRL 0x6c +#define CTCU_ETR1_IRQCTRL 0x70 #define CTCU_ETR0_ATID0 0xf8 #define CTCU_ETR1_ATID0 0x108 =20 static const struct ctcu_etr_config sa8775p_etr_cfgs[] =3D { { - .atid_offset =3D CTCU_ETR0_ATID0, - .port_num =3D 0, + .atid_offset =3D CTCU_ETR0_ATID0, + .irq_ctrl_offset =3D CTCU_ETR0_IRQCTRL, + .irq_name =3D "etr0", + .port_num =3D 0, }, { - .atid_offset =3D CTCU_ETR1_ATID0, - .port_num =3D 1, + .atid_offset =3D CTCU_ETR1_ATID0, + .irq_ctrl_offset =3D CTCU_ETR1_IRQCTRL, + .irq_name =3D "etr1", + .port_num =3D 1, }, }; =20 @@ -64,6 +71,76 @@ static const struct ctcu_config sa8775p_cfgs =3D { .num_etr_config =3D ARRAY_SIZE(sa8775p_etr_cfgs), }; =20 +static void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u= 32 offset) +{ + CS_UNLOCK(drvdata->base); + ctcu_writel(drvdata, val, offset); + CS_LOCK(drvdata->base); +} + +static ssize_t irq_val_show(struct device *dev, struct device_attribute *a= ttr, + char *buf) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + int i, len =3D 0; + + for (i =3D 0; i < ETR_MAX_NUM; i++) { + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) + len +=3D scnprintf(buf + len, PAGE_SIZE - len, "%u ", + drvdata->byte_cntr_data[i].thresh_val); + } + + len +=3D scnprintf(buf + len, PAGE_SIZE - len, "\n"); + + return len; +} + +/* Program a valid value into IRQCTRL register will enable byte-cntr inter= rupt */ +static ssize_t irq_val_store(struct device *dev, struct device_attribute *= attr, + const char *buf, size_t size) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u32 thresh_vals[ETR_MAX_NUM] =3D { 0 }; + u32 irq_ctrl_offset; + int num, i; + + num =3D sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]); + if (num <=3D 0 || num > ETR_MAX_NUM) + return -EINVAL; + + /* Threshold 0 disables the interruption. */ + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); + for (i =3D 0; i < num; i++) { + /* A small threshold will result in a large number of interruptions */ + if (thresh_vals[i] && thresh_vals[i] < SZ_4K) + return -EINVAL; + + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) { + drvdata->byte_cntr_data[i].thresh_val =3D thresh_vals[i]; + irq_ctrl_offset =3D drvdata->byte_cntr_data[i].irq_ctrl_offset; + /* A one value for IRQCTRL register represents 8 bytes */ + ctcu_program_register(drvdata, thresh_vals[i] / 8, irq_ctrl_offset); + } + } + + return size; +} +static DEVICE_ATTR_RW(irq_val); + +static struct attribute *ctcu_attrs[] =3D { + &dev_attr_irq_val.attr, + NULL, +}; + +static struct attribute_group ctcu_attr_grp =3D { + .attrs =3D ctcu_attrs, +}; + +static const struct attribute_group *ctcu_attr_grps[] =3D { + &ctcu_attr_grp, + NULL, +}; + static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 r= eg_offset, u8 bit, bool enable) { @@ -143,6 +220,8 @@ static int ctcu_enable(struct coresight_device *csdev, = enum cs_mode mode, void * { struct coresight_path *path =3D (struct coresight_path *)data; =20 + ctcu_byte_cntr_start(csdev, path); + return ctcu_set_etr_traceid(csdev, path, true); } =20 @@ -150,6 +229,8 @@ static int ctcu_disable(struct coresight_device *csdev,= void *data) { struct coresight_path *path =3D (struct coresight_path *)data; =20 + ctcu_byte_cntr_stop(csdev, path); + return ctcu_set_etr_traceid(csdev, path, false); } =20 @@ -200,7 +281,11 @@ static int ctcu_probe(struct platform_device *pdev) for (i =3D 0; i < cfgs->num_etr_config; i++) { etr_cfg =3D &cfgs->etr_cfgs[i]; drvdata->atid_offset[i] =3D etr_cfg->atid_offset; + drvdata->byte_cntr_data[i].irq_name =3D etr_cfg->irq_name; + drvdata->byte_cntr_data[i].irq_ctrl_offset =3D + etr_cfg->irq_ctrl_offset; } + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); } } =20 @@ -212,6 +297,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.subtype.helper_subtype =3D CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; desc.pdata =3D pdata; desc.dev =3D dev; + desc.groups =3D ctcu_attr_grps; desc.ops =3D &ctcu_ops; desc.access =3D CSDEV_ACCESS_IOMEM(base); =20 diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtraci= ng/coresight/coresight-ctcu.h index e9594c38dd91..8ae93c75c8df 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu.h +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -5,19 +5,27 @@ =20 #ifndef _CORESIGHT_CTCU_H #define _CORESIGHT_CTCU_H + +#include #include "coresight-trace-id.h" =20 /* Maximum number of supported ETR devices for a single CTCU. */ #define ETR_MAX_NUM 2 =20 +#define BYTE_CNTR_TIMEOUT (5 * HZ) + /** * struct ctcu_etr_config * @atid_offset: offset to the ATID0 Register. - * @port_num: in-port number of CTCU device that connected to ETR. + * @port_num: in-port number of the CTCU device that connected to ETR. + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. + * @irq_name: IRQ name in dt node. */ struct ctcu_etr_config { const u32 atid_offset; const u32 port_num; + const u32 irq_ctrl_offset; + const char *irq_name; }; =20 struct ctcu_config { @@ -25,15 +33,57 @@ struct ctcu_config { int num_etr_config; }; =20 +/** + * struct ctcu_byte_cntr + * @enable: indicates that byte_cntr function is enabled or not. + * @reading: indicates that its byte-cntr reading. + * @reading_buf: indicates that byte-cntr is reading buffer. + * @thresh_val: threshold to trigger a interruption. + * @total_size: total size of transferred data. + * @byte_cntr_irq: IRQ number. + * @irq_cnt: IRQ count. + * @irq_num: number of the byte_cntr IRQ for one session. + * @wq: workqueue of reading ETR data. + * @read_work: work of reading ETR data. + * @spin_lock: spinlock of byte cntr data. + * the byte cntr is stopped. + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. + * @irq_name: IRQ name in DT. + */ +struct ctcu_byte_cntr { + bool enable; + bool reading; + bool reading_buf; + u32 thresh_val; + u64 total_size; + int byte_cntr_irq; + atomic_t irq_cnt; + int irq_num; + wait_queue_head_t wq; + struct work_struct read_work; + raw_spinlock_t spin_lock; + u32 irq_ctrl_offset; + const char *irq_name; +}; + struct ctcu_drvdata { void __iomem *base; struct clk *apb_clk; struct device *dev; struct coresight_device *csdev; + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; raw_spinlock_t spin_lock; u32 atid_offset[ETR_MAX_NUM]; /* refcnt for each traceid of each sink */ u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; }; =20 +/* Generic functions */ +int ctcu_get_active_port(struct coresight_device *sink, struct coresight_d= evice *helper); + +/* Byte-cntr functions */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path); +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path); +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int port_num); + #endif --=20 2.34.1 From nobody Wed Oct 8 22:33:20 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C476522FF35 for ; Tue, 24 Jun 2025 06:05:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745122; cv=none; b=MCHkZ+wwTfCB9/dh0WymbGdNmBCVUuuUf+y6IFhWVDfWuuog/V9DzN9et7TegB+MFiDTbF7WRBmM7VcR0WO8a3WUA2Lke42IwuByyyzfKm7i2MKr5KSiRXitarOsbwD8yhjQPEbenrQKUnBf4/MvhHHfPfD5OQ8ve6lPFDeHv88= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745122; c=relaxed/simple; bh=NXbdrziIeuB5pcaSxjAzniV7Y1VF/HCxTAevsWleWaU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pVB4IeFgCmiOnA9Au/LyRWc8d26jnu0NOhPllcJxSpcRN47jmvOcHL5+S5aeKwTltToSXMCCax3TCzBCYl5i06mR+Sg/BZASwDC10hmIqxxZwDip+ezHeeXvZG5kW11URrwLeln++DLbVitj9m6MOeV/Wu+2SxdmeiMJkFCFlbw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=A1Bqo/Tq; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="A1Bqo/Tq" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NKlXjD021092 for ; Tue, 24 Jun 2025 06:05:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=pon7MrhUMFa eGhGyVgauqCCEFXCkk5I04yNnyLGhKTc=; b=A1Bqo/Tqq9UBD9AlarPJzaoD2Ne KU/qTD72PJzjaINh1EPSAlkXyd0OF+rUqA3Sw8/2qHpbVOuz78ZjNobRnXR5RtMc bJ0v/Jb4NaJ2jLzCM4ixTLyFe3E8XyRM6Wje0b5U83B6hJSERDt6xRdwRTVY6yTB C3Ip8CgEw3NNaVd+1Cd/GzVreZdFFK1Oj2PPbvIOrfasK9WuBY7GGVc1votFZj4E nyYaPI7BPSrRSGYkTzb5ITseMz4WL2520mB/bkntpfEu+icGMAMBk3dZ7qkrPq4R p+GBsiI6h60gG6QVfFAEDZMZUxRsuf1vi9UqeW3fBJSy4vDJ06xchJEwATA== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47fdfws56f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:05:18 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-235e7550f7bso463805ad.3 for ; Mon, 23 Jun 2025 23:05:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745107; x=1751349907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pon7MrhUMFaeGhGyVgauqCCEFXCkk5I04yNnyLGhKTc=; b=RsFx6O9Nwx6bcQiuAI2wdshg5v9q0bwRdl6UQKeDAnx+chZSvUvyRp+fbvgRD9rXiF 8+58+0p4rpzLJ5Vkg1cb71GCJ8fKcItrHD3xXXshi7F/mEbK4NNkrURAQGLhYcm3vd+L 0Cmv2wEwFy3Te1CeGrdmkB+BFwL2eDF2uObYkjl/7Har3MszdH6Q6GQXOIWUsnB5lnyk v0cArfj6hUl2gtby9ngqMJu6Ov+C91MtwjFXID7sCXcj0O56pNgCxp0Ib/hUeDbP8H4D eR4UYg9DhWN6ZCJF4ZpSEVLNKG9HLcJWtiiLE1bq528fQ4+JHYqioc6Y4K65yOgGSawG yjXQ== X-Forwarded-Encrypted: i=1; AJvYcCUGSu0kezIZQirvi57CwL/DJXnGGKZTZK8To1VSBVM6x2bWgk6re94kWLwYfxRzFKN0haENLEQwB/LPxF4=@vger.kernel.org X-Gm-Message-State: AOJu0YzInOFPVEjxmtyPXKi/jlH126L/bFHPCZbqFMJMcAWLza3w818e 9NoJiOKOKAbN9ah0+MCsqRz0AHSieTUTraE9mnRJOD48tBUrf5GNWOcYnI8+wpBEXIZ3tuy9uzX Ieh1GHTM7AnICXk7stXj5eKzw8fxce91ONFF1Snuvkhc1pXXs6eM4LcApLNU7JDm9yj0= X-Gm-Gg: ASbGnct5ovomrorL1EYStIOfd0M4hObxduRqtuTKMpqNx8u9BrdDVn+nq+BIHzvMU/z MzcgRZcnZUugQTFiQC30XDIBNXi+pIE5ooSOqi7rUJnIfSP8QoNm3m7v7R2qTptg+rIzHaXJMJT acvunNDaaGu+qlpFip1mliGZt2tBHhgHzVL3h0sLoYEjIVRQON1Pmfx/W0p/oYJwoV2RK6XmKNR t6ngaCTZOrK6/pidUedAQV0AKf8lra8o6fU+B7ligaDhnv/0J/yJs8YrFa4WDiICcUbyyF2Qhct COiN3L7D3eq5a11CBrEQLKMP8ICX7Oq/nByXO5u3U1uaLqB3QKn2jgh4o4nhPLSefP7Ry0mDGlM pwA== X-Received: by 2002:a17:902:da8c:b0:234:986c:66f9 with SMTP id d9443c01a7336-237d983d37fmr250600065ad.22.1750745106921; Mon, 23 Jun 2025 23:05:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEyxi/2L5RpxT7jQrCkp0XQD4t5nbonOAsYnD3NIf9AfeQ4K63zfMYh1t30n1bwNRgtIh/QhQ== X-Received: by 2002:a17:902:da8c:b0:234:986c:66f9 with SMTP id d9443c01a7336-237d983d37fmr250599855ad.22.1750745106562; Mon, 23 Jun 2025 23:05:06 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:05 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 05/10] coresight: tmc: add etr_buf_list to store allocated etr_buf Date: Tue, 24 Jun 2025 14:04:33 +0800 Message-Id: <20250624060438.7469-6-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: KOc85cD2pE6lMPvLR3885Orck1ozfTLf X-Proofpoint-ORIG-GUID: KOc85cD2pE6lMPvLR3885Orck1ozfTLf X-Authority-Analysis: v=2.4 cv=MtZS63ae c=1 sm=1 tr=0 ts=685a401e cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=ORm1qb0EFYpRwVLUulEA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfXzo3FEdvQbDkL MnYH0HQs1U+0LHbUl1bGbJlzF6l1qvZHa1VRdTPdstD4B07d4nBJApPKTwGuvbfQa3nu3GQMHsB cu4Cbkd3FFsPN7xYIe8lWiNbbaww3XjGrLLrGbeC4KIFHxfpzL4zoHozv3S3LWy2HSaZg+U9Db6 y9kyFEYCbYJv42BWrzaVaPFXFX/XRgimFrOTOIuvk/TXRZKNyN6CS0uTXR5iCVOPaw5W6pa03nQ z0DmI0WDTHBVtkFOKSXgyhF+XsM6o+JuES1skbEM0KImAiNbu/G6E4sJhNG234d8EoHvt2ldKn3 mnsL7TIqF2Arf+5N5hKVbcYwdKXCNk2kfI5rh5C3yNwbA5ZzCd0rLK5k65jOlaS0KVufC9tuO/a dWjlTKLN0NN7YsLooNiBFuPS7lBGLINbB0WnUFiTST1iZ4KCHM8CjpQ6kOMkOeyfqGjonbn/ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Content-Type: text/plain; charset="utf-8" Add a list to store allocated etr_buf. The byte-cntr functionality requires two etr_buf to receive trace data. The active etr_buf collects the trace data from source device, while the byte-cntr reading function accesses the deactivated etr_buf after is has been filled and synced, transferring data to the userspace. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tmc.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 88afb16bb6be..8531bac79211 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -840,6 +840,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D &etr_devs; + INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: desc.groups =3D coresight_etf_groups; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 6541a27a018e..f6b05639aeca 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -208,6 +208,21 @@ struct tmc_resrv_buf { s64 len; }; =20 +/** + * @sysfs_buf: Allocated sysfs_buf. + * @is_free: Indicates whether the buffer is free to choose. + * @reading: Indicates whether the buffer is reading. + * @pos: Position of the buffer. + * @node: Node in etr_buf_list. + */ +struct etr_buf_node { + struct etr_buf *sysfs_buf; + bool is_free; + bool reading; + loff_t pos; + struct list_head node; +}; + /** * struct tmc_drvdata - specifics associated to an TMC component * @pclk: APB clock if present, otherwise NULL @@ -242,6 +257,8 @@ struct tmc_resrv_buf { * (after crash) by default. * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. + * @etr_buf_list: List that is used to manage allocated etr_buf. + * @reading_node: Available buffer for byte-cntr reading. */ struct tmc_drvdata { struct clk *pclk; @@ -271,6 +288,8 @@ struct tmc_drvdata { struct etr_buf *perf_buf; struct tmc_resrv_buf resrv_buf; struct tmc_resrv_buf crash_mdata; + struct list_head etr_buf_list; + struct etr_buf_node *reading_node; }; =20 struct etr_buf_operations { --=20 2.34.1 From nobody Wed Oct 8 22:33:20 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F28162550C2 for ; Tue, 24 Jun 2025 06:05:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745130; cv=none; b=PaSdKRxbHQRfrQD37UnPxqnFxwVlOXJQFFujXUUdJWSWcXfhjt4RjKk3QKh3VoTgmrgJygehpW5HlzWxkiK+ITcXAOa7ByUR0NhfGMMtank3kpJU9i7Plnho2ls5++EOnKG31iHNKeyzIg18v1o2cZTOfeQxYsBncfyg/Gu2M3Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745130; c=relaxed/simple; bh=KepZY8zi4khOQ+LkoB9ldagpD9linYgqNDUu7qBt0Ug=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FXAa3FyTfv1tDm+zwZrtXNy4JOVwXW0GEr/WXjNbu0a3PA9Y/mexICBHXVDFJuIFHnMx/yclibAnakuPIOE2d14ckWcUXXPuroMzw1gGIc5EcNTA6hRcGcVbWcaZE0DE0cYO1cG/CJkQ4PNxTs5Pn65fZo1CLZ7N8ziEQw66x/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Y2Io+6Kl; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Y2Io+6Kl" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NNxWxR017387 for ; Tue, 24 Jun 2025 06:05:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=gbtexVl8cn7 s6dLp3Pk/zhJx463eI0itM2/mzeX7Ixo=; b=Y2Io+6KlVtGgDnl8eTkmBjbzuiD vusDMEAoAl/dEprcwBUvXhP1l1zht8LOP3KcxwxSRVOXEVSGgUoBtjE1FOkSiTzJ XOxU5gyGVt5lLG6i/1UjVPLcYra480HMDUzd+DLUkgjngUQSP5ruWibU6pOAgqMj H/rsq0JBoTafxJL3EMumuOlnP897x2xWj3ozSmHxNb8NkC3VOlOZCpR7X9TJml2H mtFF489O8ebMCwkzgOz9bNXKHIFW5bYFqlS++4ZloxpvNiA5AkELs2/hM9EP4U8L GnDwG4JKAemJvjfZh9Ick/w9clactHXhGjV6TtSHa+8piM1M1tj829pk6mg== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47f3bgb0dv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:05:27 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-b2eb60594e8so3312973a12.1 for ; Mon, 23 Jun 2025 23:05:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745111; x=1751349911; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gbtexVl8cn7s6dLp3Pk/zhJx463eI0itM2/mzeX7Ixo=; b=sKmKMYMZqqdU3OnJU7fhRKcFRzqN5pTs8Kg68Y9n4AlFeNsm6gYT09mqa+kKvDlOxJ TatIMO6GwD/z534/meGwJ7aJZDK4k4wUu03gHrcH3a9kVKZLSfL5UqVqCMxcCUK92ojA CW4Ri/BPVzFbepOAfWTFXaem5VviK1KpGaZDfURO3xGsatw0vPrFVhuyWNeXd09CFqEQ wF1h+LAlPAoM99vcg6Qznm5wIRyoicGjpNoJuEm0GHcmSGYj73DjCShoYRYMsN3oDFXY Ut+yNJ61mBg3YX8GUe5RY/pSOypVUrL+dChdl2V1vTFpx+cKOpHr+eF5E9W+nD8xAV0u wP4g== X-Forwarded-Encrypted: i=1; AJvYcCW3UbNYsfUx0snvvq+OuSSJ2FQ3q+6Y49QrLAs+Wg9JTCrL4DkvQPMEyP57nEXm3e77MI+L3eHoqKgLWnY=@vger.kernel.org X-Gm-Message-State: AOJu0Yzlw7dyfNDKNeeo1BWm0p9k5ti9RKzVkgXNjlNW0kljvUCe2inq aUnmVjE/JVIE96/pAM++bfy+IQZGEtbUCdGA18rt8xdhUT/iG4IXjY/R8Nb5xGvh0sN0rAL0ncH n4G4uKtJ8ZLTZJxsgZYjgE2t6/49OaPQ+zNy17fn3/KxeG8BhgH1HljrbtlncIYcVGZc= X-Gm-Gg: ASbGncvTtZQoQL/pZcNHSoy9SdKLVNj0Wrp66xUhY+zVSAj7VD1iAu6lT4BUeokpHzf ep1Vjr245vMUfUA/raaHQxdddG7njLKyKWC7aXI3NliWFlG2L+HUgdmj8aAYhb+kpPG/FuV9FlY uDiU5g+9aEA4+fASoxfkuZoqgHfW7SjPk6Ac3d2wblPg8mGTiFkx5wxQSQKOF/1hWbJN8Df1Sa3 dGQ8Pmm4aj0dqH26vg0Bh1TBd5C9IgCA6eeFDGHdWHGZPKCuMHktfvy8Im9nVRgC/wMk4hNeiws NyiYY+KQ+grX2xkBhWW/QfYUhOuETf+xVoCEZh6+cjhu3GaZi5rshnWsFvWhVk/L4TA4MywDIm0 Zhg== X-Received: by 2002:a17:903:1111:b0:235:880:cf70 with SMTP id d9443c01a7336-237d97f8c47mr201278775ad.14.1750745111416; Mon, 23 Jun 2025 23:05:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG/6alQ8oVUf4oBoB/kDRpinRzRgdoo/fUtBrPtywrip1OTrzz7TjJGaNQaFksnjaq2AYvlSg== X-Received: by 2002:a17:903:1111:b0:235:880:cf70 with SMTP id d9443c01a7336-237d97f8c47mr201278405ad.14.1750745111051; Mon, 23 Jun 2025 23:05:11 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:10 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 06/10] coresight: tmc: add create/delete functions for etr_buf_node Date: Tue, 24 Jun 2025 14:04:34 +0800 Message-Id: <20250624060438.7469-7-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: b1kJkaUh3QQu1Ly9SwwBXdTJH6UZYhEQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfXwBC99zu9hKEE pPsF4Tau6DEImO6E2vjbimYpoKJvKeOgRz38rl6WlRj5mGKctVoKWirO3kNPGyQHWl4mmdveK7o MW75/by+n4V57lEZgAy6lveHHk551Zxjv78qDUXsnAhi/CdMe19knARlcnl129yAm79010zPPzB H3v9I69S0LkdBzA8evHe+Eg3ysjIR1383z374NlZbc+OwqZv3DzHuX1eFdGcsIST9pa4QFmd62n NjJ9fva5KLwjmsSaAQEJl4ae9Y58yVnuCIV3mL0HHSKS5DkXPhxM9ywtb/a+vDv0jdlbxP7uK5t g19X40yw8gFXcV3lj6/BocR3mZk9CNxyUvNGtZxuinFpNlTEqP6Tj0P5CkNlpccACGUpNPZEIO7 v+7qOQe9WxQ8Y2ta7Kzsvg2Nf53sQ/cj0kEbkD4u1P43JqCTIkqRCk+xWviJoxh8y4+Uoxam X-Authority-Analysis: v=2.4 cv=L4kdQ/T8 c=1 sm=1 tr=0 ts=685a4027 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=k3jFKW3szlTOC2bxmxAA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: b1kJkaUh3QQu1Ly9SwwBXdTJH6UZYhEQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Content-Type: text/plain; charset="utf-8" Create and insert or remove the etr_buf_node to/from the etr_buf_list. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-etr.c | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index b07fcdb3fe1a..4609df80ae38 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1909,6 +1909,55 @@ const struct coresight_ops tmc_etr_cs_ops =3D { .panic_ops =3D &tmc_etr_sync_ops, }; =20 +static void tmc_delete_etr_buf_node(struct tmc_drvdata *drvdata) +{ + struct etr_buf_node *nd, *next; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + if (nd->sysfs_buf =3D=3D drvdata->sysfs_buf) { + list_del(&nd->node); + kfree(nd); + } else { + /* Free allocated buffers which are not utilized by ETR */ + list_del(&nd->node); + tmc_free_etr_buf(nd->sysfs_buf); + nd->sysfs_buf =3D NULL; + kfree(nd); + } + } +} + +static int tmc_create_etr_buf_node(struct tmc_drvdata *drvdata, struct etr= _buf *alloc_buf) +{ + struct etr_buf_node *sysfs_buf_node; + struct etr_buf *sysfs_buf; + + if (!alloc_buf) { + sysfs_buf =3D tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0= ), NULL); + if (IS_ERR(sysfs_buf)) + return PTR_ERR(sysfs_buf); + } else { + sysfs_buf =3D alloc_buf; + } + + sysfs_buf_node =3D kzalloc(sizeof(struct etr_buf_node), GFP_KERNEL); + if (IS_ERR(sysfs_buf_node)) { + if (!alloc_buf) + tmc_free_etr_buf(sysfs_buf); + return PTR_ERR(sysfs_buf_node); + } + + sysfs_buf_node->sysfs_buf =3D sysfs_buf; + sysfs_buf_node->reading =3D false; + if (!alloc_buf) + sysfs_buf_node->is_free =3D true; + else + sysfs_buf_node->is_free =3D false; + list_add(&sysfs_buf_node->node, &drvdata->etr_buf_list); + + return 0; +} + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret =3D 0; --=20 2.34.1 From nobody Wed Oct 8 22:33:20 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0B422441B4 for ; Tue, 24 Jun 2025 06:05:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745126; cv=none; b=AJv5ziLWKdT3eA18P/gsugphi9Of8qKdxNtLyAFkAilELD4IyGFsS9ZQ48lF+ioJ74O/SCNbI64M1vz+nNx0aQeUCiH9Np+cfav6QVL1SEovdneFxudJFNoUrGIQKZzcTY1uk6HQXwzihYcMFAIEtJF+LSORsZei0c9U6GP+Q3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745126; c=relaxed/simple; bh=gbGSvUxtrQfj4wK9v01MzbTUWNeRHpvRuORydIUDJO8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=h7iX5Cy895pG+UpP8YvJS3Lmq9f7JiKpndAGsAds5XXBMf8ArLeBbmUfftTCCdYIYRfpXsLWW3xxzrepdFsaWsWm3kklrBH6P/2XHHAF2NecZD3Oto/aDnIk7HawFUcLLDJV2QlbHFVgcDv3kA8mVD/zQdNo0+i6z1PT1znqKXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ejweXddL; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ejweXddL" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NJ3Tve020978 for ; Tue, 24 Jun 2025 06:05:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=ViTNhJOtGjt 6lfMBtp1FlF2uEsyGJpyKBN1SPAXTMJ4=; b=ejweXddLN4cdGC90vxtxRWcRdLx RMM4f7qzZoQeV/H0MekdTNVpiYLf5SGw91kKougV3ZclEhoJ/gBJd8a8MssJINSN XbnSn8Xb+eR7OmOa4JHrv8hcoZfxKo+CqkAKYc/v2IPe4FutOPFHkjtQn/fbptUT 1GhyjgUf830Bsyvelj+dw3K5/z+fe8M7VI2drwGZS928OdUbeZZWSvvaoGVu+lAG H2Q4yvvKWtbaLvt9YwdsO9Wot6yTOED0mZUpS5nopIFpwpcWj+a/AoSJWj5niwsK 1f24fhNecJ6FIOUdMLF0/jRoXlOeIpMOhb968JBO9owi1cIWXwDYlrLq6Vw== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47f4b3tv5a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:05:22 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-235196dfc50so48262385ad.1 for ; Mon, 23 Jun 2025 23:05:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745116; x=1751349916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ViTNhJOtGjt6lfMBtp1FlF2uEsyGJpyKBN1SPAXTMJ4=; b=hJniZwaF8m5bjWRri3DiYK/W6oajSajIBPfMa33r9IQxz3UhJCc9+mreoxyrBuY0h2 QZngkbhDLTJn6Z2WWjana79QdJCosbuXvyFQlufoeCu1Su4WKDOqwmVLQCjoWCr5kvOc wolgXY8iyholFmkZ4A6MtN2IGbK4ajJ38ACzqnB2RqmYglcrmQzcUcLa1U0K7+RtbrhR utgDCT5P8E74PEdtyFolwgoCnd2+gF0MJ//Cqu+BA4FFd40OkiDIbdGlDBnj4TJOddIx RQPm5sdIa+XhtPGxspBRrDM9zUF6QmmhnGaTtHF/e/A139GdYUB7+SJwngQVqR9tifxi hQFA== X-Forwarded-Encrypted: i=1; AJvYcCUcGKBnWnSYXx2VD7EEmsxhubiA0/7q1ad4flGvDtWsXBd5VXXmNKf3u8DbXv0Fa+hP7rXElLvwht4tPEI=@vger.kernel.org X-Gm-Message-State: AOJu0YwmD4UFcIL6k1jPlyp8V0Ly8iZH4d3JTuPLf59slC6kE8msOUmy QzHsYyfix01jsSLhPbtU+PP5pgF8NoD/N+eh7hIir5MpQ7TJOpXQ4PgXPGTEwGXKazPo0GTwreT rEBmDbL/lMEmVAVVUgcQl47bL1Ugru1RW4sDBjBbl9GNl/iSSH5RY3QNgIuHS/yoxFTo= X-Gm-Gg: ASbGnctXzFgQL2bpg1fFpAH8skg+BmHZLJ0L3niqgJwQ/Wi2r05HhsmOo/evBCqlb1I Imkbu/Ts4A2Q+00MwaoAdd75ZuFupv9b2STbQctePRs3IjqrLLarh/uK0cdyBCJSGAtHaI4AuYd t2QspGaaaBbu8Q5jNdHN+MKzhIAEnlTSfkkd1uWUQkBC1qIevJ6imOiv6QayabGsflL6cvMKa5x UfQPfiK0/a7nrULpQV0/2e7ov/UsHD5hl6XilixZpcIUcDF7zsCscp9dLILuSdO+0QlmeUF8LYi o8z5aQ72X2/HYSgsRQsyJLtHKQkxeZFpo4KXM5F/hEVaHAdXm2+0ln4cKVKNREaM0UePjyagAdo KpA== X-Received: by 2002:a17:902:da8d:b0:231:e413:986c with SMTP id d9443c01a7336-2380245eabbmr32408715ad.11.1750745115990; Mon, 23 Jun 2025 23:05:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHqWPFCk1vGIK6OC6QmCXLMh+OHz10tmlUnDaYKRcbgjljEq4H6EvG36i6gTOPY5fL0FezOsw== X-Received: by 2002:a17:902:da8d:b0:231:e413:986c with SMTP id d9443c01a7336-2380245eabbmr32408275ad.11.1750745115520; Mon, 23 Jun 2025 23:05:15 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:14 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 07/10] coresight: tmc: add prepare/unprepare functions for byte-cntr Date: Tue, 24 Jun 2025 14:04:35 +0800 Message-Id: <20250624060438.7469-8-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfX8ZROFmVE6r8D D20MAp4tpqNV3NN0Wy3EtBNj+Xo+0vLkgiyOaOgr0/gYqnVEtoQ0npSpaSd2nuADnftkJg40XEF 4ua0apbD4O+6gOs9OWDgMyUbIiBmqM5LURHKCjrhEklU6fGB+a4mIoNcBANOLteLSWuW5DconPh m+ayZP9GHcoFWp/0oLieDMS/98ecIuYnSB/RhP8Sz0fnVKB8eaAgAREyNcTNBiNZevY5UKoMrUP V3hvWYaidwtcKBWG+Tq2DBZgYkSF1nuQ9Vc1lTF/D4EJabGCfEEUplZEj4808uCB2UO1uB7RK9Y c3TKz6HHuEigWNWaVcB62wNnI27Bn8PdSuPmhcJ3OSQJanKo4UHvpTyAgwYlQHhl2Z7p4wTv1Yk szgndbsrv8D5zk+aYPaOxiRW1V7UkMlk/FlIUUmCVldKjE1b2Wpxwz8lQHqYCOu2Kj5MekpG X-Proofpoint-ORIG-GUID: ozN6YcCRPw7jvGm162_8_4yyAxjjzkwm X-Proofpoint-GUID: ozN6YcCRPw7jvGm162_8_4yyAxjjzkwm X-Authority-Analysis: v=2.4 cv=A8BsP7WG c=1 sm=1 tr=0 ts=685a4023 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=xC7plfDI9GgKYcT3xssA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=799 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 suspectscore=0 mlxscore=0 clxscore=1015 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Content-Type: text/plain; charset="utf-8" Prepare for byte-cntr reading. An additional sysfs_buf is required to receive trace data, as byte-cntr always reads from the deactivated and filled sysfs_buf. The unprepare function releases the additional deactivated sysfs_buf allocated during the prepare phase. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 38 ++++++++- .../hwtracing/coresight/coresight-tmc-etr.c | 79 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 8 ++ 3 files changed, 121 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 8531bac79211..40605310240d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -229,7 +229,11 @@ static int tmc_prepare_crashdata(struct tmc_drvdata *d= rvdata) =20 static int tmc_read_prepare(struct tmc_drvdata *drvdata) { - int ret =3D 0; + struct coresight_device *helper =3D coresight_get_helper(drvdata->csdev, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); + struct ctcu_byte_cntr *byte_cntr_data =3D NULL; + struct ctcu_drvdata *ctcu_drvdata =3D NULL; + int port, ret =3D 0; =20 switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: @@ -237,7 +241,18 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdat= a) ret =3D tmc_read_prepare_etb(drvdata); break; case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_prepare_etr(drvdata); + if (helper) { + port =3D coresight_get_port_helper(drvdata->csdev, helper); + if (port >=3D 0) { + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + } + } + + if (byte_cntr_data && byte_cntr_data->thresh_val) + ret =3D tmc_read_prepare_byte_cntr(drvdata, byte_cntr_data); + else + ret =3D tmc_read_prepare_etr(drvdata); break; default: ret =3D -EINVAL; @@ -251,7 +266,11 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdat= a) =20 static int tmc_read_unprepare(struct tmc_drvdata *drvdata) { - int ret =3D 0; + struct coresight_device *helper =3D coresight_get_helper(drvdata->csdev, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); + struct ctcu_byte_cntr *byte_cntr_data =3D NULL; + struct ctcu_drvdata *ctcu_drvdata =3D NULL; + int port, ret =3D 0; =20 switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: @@ -259,7 +278,18 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvd= ata) ret =3D tmc_read_unprepare_etb(drvdata); break; case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_unprepare_etr(drvdata); + if (helper) { + port =3D coresight_get_port_helper(drvdata->csdev, helper); + if (port >=3D 0) { + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + } + } + + if (byte_cntr_data && byte_cntr_data->thresh_val) + ret =3D tmc_read_unprepare_byte_cntr(drvdata, byte_cntr_data); + else + ret =3D tmc_read_unprepare_etr(drvdata); break; default: ret =3D -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 4609df80ae38..2b73bd8074bb 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -2032,6 +2032,85 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvda= ta) return 0; } =20 +int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + unsigned long flags; + int ret =3D 0; + + /* config types are set a boot time and never change */ + if (WARN_ON_ONCE(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) + return -EINVAL; + + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_SYSFS) + return -EINVAL; + + /* + * The threshold value must not exceed the buffer size. + * A margin should be maintained between the two values to account + * for the time gap between the interrupt and buffer switching. + */ + if (byte_cntr_data->thresh_val + SZ_16K >=3D drvdata->size) { + dev_err(&drvdata->csdev->dev, "The threshold value is too large\n"); + return -EINVAL; + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (byte_cntr_data->reading) { + ret =3D -EBUSY; + goto out_unlock; + } + + byte_cntr_data->reading =3D true; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + /* Insert current sysfs_buf into the list */ + ret =3D tmc_create_etr_buf_node(drvdata, drvdata->sysfs_buf); + if (!ret) { + /* + * Add one more sysfs_buf for byte-cntr function, byte-cntr always reads + * the data from the buffer which has been synced. Switch the buffer when + * the used buffer is nearly full. The used buffer will be synced and ma= de + * available for reading before switch. + */ + ret =3D tmc_create_etr_buf_node(drvdata, NULL); + if (ret) { + dev_err(&drvdata->csdev->dev, "Failed to create etr_buf_node\n"); + tmc_delete_etr_buf_node(drvdata); + byte_cntr_data->reading =3D false; + goto out; + } + } + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + atomic_set(&byte_cntr_data->irq_cnt, 0); + enable_irq(byte_cntr_data->byte_cntr_irq); + enable_irq_wake(byte_cntr_data->byte_cntr_irq); + byte_cntr_data->total_size =3D 0; + byte_cntr_data->irq_num =3D 0; + +out_unlock: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + +out: + return ret; +} + +int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct device *dev =3D &drvdata->csdev->dev; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + disable_irq_wake(byte_cntr_data->byte_cntr_irq); + disable_irq(byte_cntr_data->byte_cntr_irq); + byte_cntr_data->reading =3D false; + tmc_delete_etr_buf_node(drvdata); + dev_dbg(dev, "send data total size:%llu bytes, irq_cnt:%d\n", + byte_cntr_data->total_size, byte_cntr_data->irq_num); + + return 0; +} + static const char *const buf_modes_str[] =3D { [ETR_MODE_FLAT] =3D "flat", [ETR_MODE_ETR_SG] =3D "tmc-sg", diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index f6b05639aeca..f95df0a34ad6 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -14,6 +14,8 @@ #include #include =20 +#include "coresight-ctcu.h" + #define TMC_RSZ 0x004 #define TMC_STS 0x00c #define TMC_RRD 0x010 @@ -357,6 +359,12 @@ extern const struct coresight_ops tmc_etr_cs_ops; ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, char **bufpp); =20 +/* Byte-cntr functions */ +int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data); +int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data); + =20 #define TMC_REG_PAIR(name, lo_off, hi_off) \ static inline u64 \ --=20 2.34.1 From nobody Wed Oct 8 22:33:20 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A5FD242D9A for ; Tue, 24 Jun 2025 06:05:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745124; cv=none; b=tz/h5ybswINCimwcqNO8UoVtwRvT2Th9gmC1Z6lEd9KJWldbg+gzTENWFLsG3VZQv05mN61fLg7ASefWnuuyQOQDq68TlqwsF6VEsy6xipdQS0sT3LR6WYhvbMxQpUl+sQUilVFki4gB3NQu3NdqaRLhBEDs2eHtgWX9qv13SCo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745124; c=relaxed/simple; bh=d/N/TB61i7GeVIWGxfjbRQ9Z2F1vTqrm+bBemdmjw3Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GGCK7D0kDNc9SMxlgKBX/CuTL1kytiC63tP5CFIVeer2YVrb0XVVqHLE/30cZrbFjIamnW3TWXrOkWH4oVOHilZV/roXJQOkTL0hlrWga6ZRdruiVfsxXzV0MJOGNSXm9txaw09Md1R05rEYLKF/+2JyYTuS07VAFIqaRBZ1eCY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=FdU6f3Gj; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="FdU6f3Gj" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NHkHYi032470 for ; Tue, 24 Jun 2025 06:05:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=x07SNj1YXpj 6RfRQ48AeQgzrdGK/jYfZ/E/HEUOOxeI=; b=FdU6f3GjHRbFs8m3J6pr3YFOYam OchjWHIfYetew5iKxw86RrBnjvgD6LYTBIDRHxeMshXe3QX60V/KTOaxrJgMgwt4 76SWEZHMC8sv5BUVcPjB8fx5mOx/UuSPiIdbQQc3dL43jPGJs0fnUXcfkuFOaFCY raV8CAqeq9Q1iCkhY45zclLyO++C9IcyE7+Dir3uW3Yy0nkfTp90/fQiTS3CJquA de38y0LS9NyUXrrP/fH+rqfZXQdcmmnoIev8Lyqr+yhsNFQ5nfV5KatUf0Svj30l CmU/Pjp3fMGUUL+OgFOFLA1JY/rgxbhFmu638RgMNLDvPwS241Jp5bNO11Q== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47fbm1sfdx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:05:22 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2356ce55d33so1097995ad.0 for ; Mon, 23 Jun 2025 23:05:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745120; x=1751349920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x07SNj1YXpj6RfRQ48AeQgzrdGK/jYfZ/E/HEUOOxeI=; b=p7JX9pON8r+J5jMKQgJMssKpdk//0Bbr2Skwhs/0Wo8O4KeJ5ffbu5i1R0qX/6g4i2 K1ulwTw9CLLpBJ7Euqu1OrKuFUe5KKnQBnor1ZGibhq2qPEh49GsirKjDPix9sefSll6 o6UcfBx/GDfBJKZkcUnxe2JQzJQdq5EQpPRScMMFvb3rnK9Eht2bd6mwuG6RiHyFtVR4 INsONu2bjNXG08A4CSwtB+NF0hT+uTVNnLV6fplhzxdO0hy7GziDPTmhZfNFa2pLLwqw iewnYeNkLa6w++fl3xM2Q5qqstwfYkqPN4evJ/6aBLkAoKmPsYZUWBob1SP0m/8vRi2W 9JiQ== X-Forwarded-Encrypted: i=1; AJvYcCXb3dx1irMpOjDG+Zh2AtTnx9AyCMCnsaSnJk/fh5cgTga52iwYgEG0IyyuvlznBoistrzJIr/H46x2/kY=@vger.kernel.org X-Gm-Message-State: AOJu0Yxv8P+BGAZS2UjAMguUVxBgoFd79iqko6+SydWDeUv4pSg1+3rp gOhph3xkqr6n2lqse837esDt88rKC1v6zNf8RCFcedfukQECvcDt+sgru3V3vIl0Naxs/50E87M Frjx7BjcYSMalKht3KTKhDtBENrQkkkDqGjLX7fvmbbI+1TK/qJz2RJfNqXcZX+l/5+w= X-Gm-Gg: ASbGncugBOMDOMuuIRDDYwgqbd3whWdBgqmEaaYhaZhnzmVUqgKVRCCEyLBgLrWp4nO Fq1nAbD6cO7ArU5pcnGjseL+nfogTFEtt/SG5QYqkFVPUL+uDGgYembTpfGfRMZfrjfhLxUsNCx klpK67tbLZB0dT+SuCaQUpsLvIk03l/AVIID6g7P2yTEHfC/7qSmV9i28rz385UV2qhHN0UK7Q/ q4ztEmRjf9uZLYd7KXTcghG3IxPB3oNzfAK/nOoPHQlS+vts0mCGBAvDq+6C+/hT5eNIuy3WEqg Eb3HH7+2rBdGuUa1i2lZoH8htiZudtAfMlVey/pvtDmsUNG65hFpA8Uct1tNo5M7lnDY8iFNDgs 35A== X-Received: by 2002:a17:903:2d0:b0:234:8a16:d62b with SMTP id d9443c01a7336-237d970f9bamr253275995ad.12.1750745120409; Mon, 23 Jun 2025 23:05:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE97aOL/swaHhYhRTiIKSN86TTBXV1K7HhrE7lHhuqfmi5WW9OInNk27uiW+r30tmlu+zChDA== X-Received: by 2002:a17:903:2d0:b0:234:8a16:d62b with SMTP id d9443c01a7336-237d970f9bamr253275655ad.12.1750745120065; Mon, 23 Jun 2025 23:05:20 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:19 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 08/10] coresight: tmc: add a switch buffer function for byte-cntr Date: Tue, 24 Jun 2025 14:04:36 +0800 Message-Id: <20250624060438.7469-9-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=YYu95xRf c=1 sm=1 tr=0 ts=685a4022 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=wDWrKlMOwBuH9W2KgGoA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: C_aKqHczI9CxIsLqEmBcXg3xRuDmK9ra X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfX/cPaMpgM5+Qj bRYUBg01N4l7H+lxtmP+h00nmOUu1vL4hiBJcug8e4geRnfATAOiTPbdrywdQ30EE0qz4brlDGE NWO0Gmu/YU+CU+eRCxrV/4QvU2vFFgovNYQsKypG9gKl2/iJ9IoUTdmisK4s+9iIXTW6wUReAzl pZvdtu/aILDRP7o/G50ESFRPcgMv5BfdUgwNj5P7Dq1S6QQP/tELN+v6enL/xinMrb726sOlJqR FczAGIhG5xI1JdALmc5th70xdtjq5z27cP+Ci5HYf8NNEFMckn3cyxaAyN23+StZe3xEjXHHeE+ XT0iYFqYjpe3s3uewMhrIa5xTBg8bN4qS3iz/6luY4pFkQpzyCXZ8eC+9WvIcyoAm1Z+cynotfo a+Q3RKsfpp4myEbDSsibUzvKMbPSfyvznOtXld/MIb3RB0tkIAues2v2CquRSVUgy6yGuGDc X-Proofpoint-ORIG-GUID: C_aKqHczI9CxIsLqEmBcXg3xRuDmK9ra X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Content-Type: text/plain; charset="utf-8" Switching the sysfs_buf when current buffer is full or the timeout is triggered and resets rrp and rwp registers after switched the buffer. Disable the ETR device if it cannot find an available buffer to switch. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-etr.c | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 2b73bd8074bb..3e3e1b5e78ca 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1287,6 +1287,58 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(stru= ct coresight_device *csdev) return ret ? ERR_PTR(ret) : drvdata->sysfs_buf; } =20 +static bool tmc_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct etr_buf_node *nd, *next, *curr_node, *picked_node; + struct etr_buf *curr_buf =3D drvdata->sysfs_buf; + bool found_free_buf =3D false; + + if (WARN_ON(!drvdata || !byte_cntr_data)) + return found_free_buf; + + /* Stop the ETR before we start the switching process */ + if (coresight_get_mode(drvdata->csdev) =3D=3D CS_MODE_SYSFS) + __tmc_etr_disable_hw(drvdata); + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + /* curr_buf is free for next round */ + if (nd->sysfs_buf =3D=3D curr_buf) { + nd->is_free =3D true; + curr_node =3D nd; + } + + if (!found_free_buf && nd->is_free && nd->sysfs_buf !=3D curr_buf) { + if (nd->reading) + continue; + + picked_node =3D nd; + found_free_buf =3D true; + } + } + + if (found_free_buf) { + curr_node->reading =3D true; + curr_node->pos =3D 0; + drvdata->reading_node =3D curr_node; + drvdata->sysfs_buf =3D picked_node->sysfs_buf; + drvdata->etr_buf =3D picked_node->sysfs_buf; + picked_node->is_free =3D false; + /* Reset irq_cnt for next etr_buf */ + atomic_set(&byte_cntr_data->irq_cnt, 0); + /* Reset rrp and rwp when the system has switched the buffer*/ + CS_UNLOCK(drvdata->base); + tmc_write_rrp(drvdata, 0); + tmc_write_rwp(drvdata, 0); + CS_LOCK(drvdata->base); + /* Restart the ETR when we find a free buffer */ + if (coresight_get_mode(drvdata->csdev) =3D=3D CS_MODE_SYSFS) + __tmc_etr_enable_hw(drvdata); + } + + return found_free_buf; +} + static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) { int ret =3D 0; --=20 2.34.1 From nobody Wed Oct 8 22:33:20 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01BA92522B5 for ; Tue, 24 Jun 2025 06:05:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745128; cv=none; b=V1Hdh3c14pmGrWgF9oQ1P7Qd4azJTyDlgvp8nH82t+j3ZkJzXCr1ilas8vwbp74MyCnVJvIMo/YuQqn0dC7QHsjRKp+MilxEXE1gjZUIPj/ZAsJghhFSCSVdj7CaAAPJZUMeAR4qFYhyD7c//TL5TrRhnHUiPTFCDCS1Y2BvVl8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745128; c=relaxed/simple; bh=VBK9JtAr3FmFIut3GYFMz/furBThoh2UTUTxdAFQcD0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ghL+emf2tnNtXJExzXnHeHZr6kSkMbMO4GoVdBILZEpyaqdY3z8aQo6Lp8IZF12EnEvps8enp6DAe77u37hk+kLBmbSV3QiVj7PoVTiRpQ6/E+PdC/dyGbkBomVchYB8yAYwJWbRBwbPjH8RVbmf1ChQ4L7fRwC3JfphoSLjSm0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=i0c4z4eE; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="i0c4z4eE" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NI2iEc020784 for ; Tue, 24 Jun 2025 06:05:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=lDdOYdwFc4W UgEUqvI2QS/sAK9B8E5IgVNSudMM9Bh8=; b=i0c4z4eEl78Km1aLtMy5ImC4Sr4 SBbO/iWZPsABX7YYWZxjQAGNjmoi5P6NSVRaIa4c+NhlLjfDkvdwnkXaN4CJ/FOd 41dM0cDx91dOE4QG95OtiikmB+0Tzi2AF26Eu2/G8NlwGqbN4LuPzbGuC8KBO+JQ QlMdybB+cr/FvFhFoqRX2NDXlS2U7rtWErF1xtb0TbicLGDctlsiDcczsUplOB9X CfCVtZ6kURwyE/Y5wBOTyCP6xT+Rn+SAIYwn7J/cpr01bWHPqCPFP0Ru3TGVQg77 92Me4yw+n9Wg7z9z2WnNuCZtm/PoR98v3obKCh6ezschd7jYP4whKOo3oNg== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47f4b3tv5y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:05:26 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-315af08594fso2738116a91.2 for ; Mon, 23 Jun 2025 23:05:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745125; x=1751349925; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lDdOYdwFc4WUgEUqvI2QS/sAK9B8E5IgVNSudMM9Bh8=; b=BkTobluJyB92b0AenRxN9zeAMpBsxdxLaGyatiPGnXt+TSMt2SVv7xK+ZbSA9XeFHR D66OTbl7EY28fwQratLVVNV16gDFm/kC9cdmEkFifARRJn0N+fV18DwWBeW+IfPiuaZH 8l2wI1fO2NuFj3QU7zY4U5SIMDRZ26CHouvjKpzwt29THFf3YFHiaEIwfaGzizNlO9sP udILUzQ9DT3s1azrVwGv9tDayenEkg2ueS2i4P4s+frafDUUT2fExnPaUBEg15YitMeB rxHy7HnzgGXxYkJmJ8UFNj235CQe0iL+Roe9kac6KWrZeVYUKoamCruTvBFfraXYnaYT ayFA== X-Forwarded-Encrypted: i=1; AJvYcCW1VD1g+WHPByA9WC766W9hXe93+qlAFxhxHwJTA710BtVkl+/kWvHWo/ouSdYvZdzxVZuc4zjRVt8BlC8=@vger.kernel.org X-Gm-Message-State: AOJu0Yy/jG5swhiWYLqYMCJXm4PqrdPQiLCiiYudrsdFgd+5at+oOYbX ATPn0YoBV6iMvM9BOCNU6iIE+/qB53K+DjtBkdghGTirgd8zEGYiFuVTjj/wyC216aq0pi+EJrs DLweoMZhcT8pPCc/vFyJOxMraWK82Y8F0aVJ/+AY4QGcX2ZHG+Ere5TlSJimJnblYDUk= X-Gm-Gg: ASbGncvKLKQCIfeKEob/P6ITx1oXHCPH2urPVd7bO/d60uKEy32xsRYtD8Jxi+reDr7 M34iDcPbSkQDy4P/zJ05rsDGCyZDWx+v926Utd4LQpERSx62JiTB8JegZgs+zqjNrif+Yy5LFGF sj9fh4TbvaZtvAS3DhL/UEl9M4/QfxaEt4O4oysFZkZOs4t6Zir7+aZZfyKZAUbA1InLCNEwyLo eyIllydAP1iAHTfD1feSUctzi0J1XKYbhv64bkn99GC/1MmLeFIrucXMBqgDVsQ4TfqeWUMLfZ4 Xj5VrHZz+K3K9yZlcrqj2PMX1RJ/OZ/JACU6nNFmH7l4lHlCMEhYdadwyhqS0lBKloh1uGciYlH 9yA== X-Received: by 2002:a17:903:4b07:b0:234:8eeb:d834 with SMTP id d9443c01a7336-237d97fbc8fmr248546205ad.16.1750745125079; Mon, 23 Jun 2025 23:05:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFJSsLPuqK7+6S2VP4lZAltQqpakLws2gPXkMkL3c6Beh8EhGPZyr249GoBMsvm7A/2zAVDFQ== X-Received: by 2002:a17:903:4b07:b0:234:8eeb:d834 with SMTP id d9443c01a7336-237d97fbc8fmr248545765ad.16.1750745124642; Mon, 23 Jun 2025 23:05:24 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:23 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 09/10] coresight: tmc: add read function for byte-cntr Date: Tue, 24 Jun 2025 14:04:37 +0800 Message-Id: <20250624060438.7469-10-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfX/D/SupWG8Bt6 j+TC8J0uvo2DtatUZdtbU0xbqSZksaECfrWIM4VXGpe6IXcCkfewoAdUpdMBmb99oagcZk9LNnP Dn9BvZww0k+zkYAoC9z8w66YtSU71aPIPwTRZKhZfOUyzk0Jxi6W5rxtVTOOmJaUEEZlc/u5wtu bNFJIosqpH5b2gqfYGuP++6FRFJYG9CzVa5ip/vTjNMPQ5MFV+9AkBsr2QVERAZUD9iNmSMZ5S4 CKjnIXI+LGurNifdsgbtRHgqd+zEo0O0fYHWonA3d1JwECjuCxr6o6r375c14zTyAELbhDOS+0+ 2RGiv9gzOamNnFQvKZcmfq5HFbK6Vm0VvkpkS+ZsymVutSsU3PDAMj7HoSXm45XOrWBxpPSF+fJ f68rrowAL5hyIsr4lxxnvMbfP97MRnlGvqVlX7gPXdAzHAhmJwxa/XBGEMMOm2t65MFYE0Mq X-Proofpoint-ORIG-GUID: JL3BL4dW_ZveV5fbc6Jqb9ARxO8rfbd_ X-Proofpoint-GUID: JL3BL4dW_ZveV5fbc6Jqb9ARxO8rfbd_ X-Authority-Analysis: v=2.4 cv=A8BsP7WG c=1 sm=1 tr=0 ts=685a4026 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=56IJ4eEW6NAC_NOVRZQA:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 suspectscore=0 mlxscore=0 clxscore=1015 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Content-Type: text/plain; charset="utf-8" The byte-cntr read function always reads trace data from the deactivated and filled buffer which is already synced. The read function will fail when the ETR cannot find a available buffer to receive trace data. The read function terminates when the path is disabled or interrupted by a signal. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 31 ++++++- .../hwtracing/coresight/coresight-tmc-etr.c | 90 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 4 +- 3 files changed, 120 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 40605310240d..7b09cf060666 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -317,14 +317,18 @@ static int tmc_open(struct inode *inode, struct file = *file) return 0; } =20 -static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos= , size_t len, - char **bufpp) +static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data, + loff_t pos, size_t len, char **bufpp) { switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: case TMC_CONFIG_TYPE_ETF: return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); case TMC_CONFIG_TYPE_ETR: + if (byte_cntr_data && byte_cntr_data->thresh_val) + return tmc_byte_cntr_get_data(drvdata, byte_cntr_data, len, bufpp); + return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); } =20 @@ -338,7 +342,21 @@ static ssize_t tmc_read(struct file *file, char __user= *data, size_t len, ssize_t actual; struct tmc_drvdata *drvdata =3D container_of(file->private_data, struct tmc_drvdata, miscdev); - actual =3D tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); + struct coresight_device *helper =3D coresight_get_helper(drvdata->csdev, + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU); + struct ctcu_byte_cntr *byte_cntr_data =3D NULL; + struct ctcu_drvdata *ctcu_drvdata =3D NULL; + int port; + + if (helper) { + port =3D coresight_get_port_helper(drvdata->csdev, helper); + if (port >=3D 0) { + ctcu_drvdata =3D dev_get_drvdata(helper->dev.parent); + byte_cntr_data =3D &ctcu_drvdata->byte_cntr_data[port]; + } + } + + actual =3D tmc_get_sysfs_trace(drvdata, byte_cntr_data, *ppos, len, &bufp= ); if (actual <=3D 0) return 0; =20 @@ -348,7 +366,12 @@ static ssize_t tmc_read(struct file *file, char __user= *data, size_t len, return -EFAULT; } =20 - *ppos +=3D actual; + if (byte_cntr_data && byte_cntr_data->thresh_val) { + byte_cntr_data->total_size +=3D actual; + drvdata->reading_node->pos +=3D actual; + } else + *ppos +=3D actual; + dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); =20 return actual; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 3e3e1b5e78ca..8f53ecb12ad3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1163,6 +1163,10 @@ ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *= drvdata, ssize_t actual =3D len; struct etr_buf *etr_buf =3D drvdata->sysfs_buf; =20 + /* Reading the buf defind in buf_node if it exists*/ + if (drvdata->reading_node) + etr_buf =3D drvdata->reading_node->sysfs_buf; + if (pos + actual > etr_buf->len) actual =3D etr_buf->len - pos; if (actual <=3D 0) @@ -1339,6 +1343,92 @@ static bool tmc_byte_cntr_switch_buffer(struct tmc_d= rvdata *drvdata, return found_free_buf; } =20 +/* + * tmc_byte_cntr_get_data() - reads data from the deactived and filled buf= fer. + * The byte-cntr reading work reads data from the deactived and filled buf= fer. + * The read operation waits for a buffer to become available, either fille= d or + * upon timeout, and then reads trace data from the synced buffer. + */ +ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data, + size_t len, char **bufpp) +{ + size_t thresh_val =3D byte_cntr_data->thresh_val; + atomic_t *irq_cnt =3D &byte_cntr_data->irq_cnt; + struct etr_buf *sysfs_buf =3D drvdata->sysfs_buf; + struct device *dev =3D &drvdata->csdev->dev; + struct etr_buf_node *nd, *next; + ssize_t size =3D sysfs_buf->size; + ssize_t actual; + loff_t pos; + int ret; + +wait_buffer: + if (!byte_cntr_data->reading_buf) { + ret =3D wait_event_interruptible_timeout(byte_cntr_data->wq, + ((atomic_read(irq_cnt) + 1) * thresh_val >=3D size) || + !byte_cntr_data->enable, + BYTE_CNTR_TIMEOUT); + if (ret < 0) + return ret; + /* + * The current etr_buf is almost full or timeout is triggered, + * so switch the buffer and mark the switched buffer as reading. + */ + if (byte_cntr_data->enable) { + if (!tmc_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) { + dev_err(dev, "Switch buffer failed for byte-cntr\n"); + return -EINVAL; + } + + byte_cntr_data->reading_buf =3D true; + } else { + if (!drvdata->reading_node) { + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + if (nd->sysfs_buf =3D=3D sysfs_buf) { + nd->pos =3D 0; + drvdata->reading_node =3D nd; + break; + } + } + } + + pos =3D drvdata->reading_node->pos; + actual =3D tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); + if (actual > 0) + return actual; + + drvdata->reading_node =3D NULL; + + /* Exit byte-cntr reading */ + return -EINVAL; + } + } + + /* Check the status of current etr_buf*/ + if ((atomic_read(irq_cnt) + 1) * thresh_val >=3D size) + /* + * Unlikely to find a free buffer to switch, so just disable + * the ETR for a while. + */ + if (!tmc_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) + dev_info(dev, "No available buffer to store data, disable ETR\n"); + + pos =3D drvdata->reading_node->pos; + actual =3D tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); + if (actual =3D=3D 0) { + /* Reading work for marked buffer has finished, reset flags */ + drvdata->reading_node->reading =3D false; + byte_cntr_data->reading_buf =3D false; + drvdata->reading_node =3D NULL; + + /* Nothing in the buffer, wait for next buffer to be filled */ + goto wait_buffer; + } + + return actual; +} + static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) { int ret =3D 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index f95df0a34ad6..4136ec5ecaf7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -364,7 +364,9 @@ int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvd= ata, struct ctcu_byte_cntr *byte_cntr_data); int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata, struct ctcu_byte_cntr *byte_cntr_data); - +ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data, + size_t len, char **bufpp); =20 #define TMC_REG_PAIR(name, lo_off, hi_off) \ static inline u64 \ --=20 2.34.1 From nobody Wed Oct 8 22:33:20 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC5C62571AA for ; Tue, 24 Jun 2025 06:05:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745133; cv=none; b=YROQG0YPvBGG4gmizBHm4s61wkEk+eY5ASe//ADSFoTtHdMEcje7NXW1oxyK56vVUhgVQVDZF015hg/EGEvnuo1hPVMjHT3xNzMQ2v9ysnNx/sONB/1qSn5ZoDfQa7T8+iwxcFDnk3TaOTTxURfXD5cYuUBBVVBzQVWUjfiRZlk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750745133; c=relaxed/simple; bh=f30cw/8H4EXiyHfPv/hWpyXvXZsxpbdm/rrj/jZvh1Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pzQ/MSKSvJxyr0C8HynMd3HW/gWqp1ZgeUJ2acycVw0qAkY4T3k3E7XkR3HOZe+K6xtpgusN7xnUw+sI/IHRVnm+e3yn3fFSmaY5ihNgAZGzIoWtPlLxLXXXMhFfQ872mv7+5A5xhXEpCk1hI//MKW8qwP9ZrBWvf4Seaq67Wqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=AvNc3dEu; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="AvNc3dEu" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55NKm1X9015936 for ; Tue, 24 Jun 2025 06:05:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=k+EDEHFqKkj GqN2StGIjjiSlDJT77CrFI7R+bA+Neo0=; b=AvNc3dEu9OgdoCaoXkLzUHZ9gAj +LCOuG+Ek+3UbSK0O5HVWs3P7rPlKIuK06AzWOuJVuurAgScQlqx+6uwgqnbYwWk gMR4Xg0YvkJNPtddMgm3TeNbvjoXiH+14q2Uf6qbEqctSkKZmosPcQtH5SLj0drs O0LriF3PPIkkbALAq/zfaliTCFIhsVaP5e0rnXM1epymcQ0kSJY+c14kkr07XjdN DKHO1WLB9rjEng80kwup4oarH7sKQLacQRpFDuT6fNFiziY6DgeUIVyzU6dPqmiZ z0ykrvfoxoYX0De1qBYD9AqxSWXh+fFM+p5YoNHi1/57VuaGvimCWj0cppg== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47fbhqheex-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Jun 2025 06:05:30 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-235e3f93687so77587375ad.2 for ; Mon, 23 Jun 2025 23:05:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750745129; x=1751349929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k+EDEHFqKkjGqN2StGIjjiSlDJT77CrFI7R+bA+Neo0=; b=Ua6jtOC8Pqu1OBnQX77FZbl2eZoxK64ShHbYf3mqU9dfFbc3bQ/yWRIuM5A4ATd+Hh ian3qN9frHEQu0TTVb6uQy7gtTtGdXVMz41fC7p5ISAW6QElj0HW0w6BxTrhicQ6/JM/ E06qTqvZ17x+vdyAn/OMLJpstcCvkoVTy2k8EEDOVw0b4GQXa9MeF/u3IRgW7N8NpuQw x7YylokhSU6vXKeJm3YbYZvY6iNsPt1C4lJhCZ8HMn5Eh0aVHmneORCM/CNYZXFNRbHT 07hKktIlza90sDdwJvJiItFUdoV9HASDZy859tVIo2pfUVP8/RSHrzrtUQDJv1cQarx2 g2Ng== X-Forwarded-Encrypted: i=1; AJvYcCVB/URFR5jQmMYIPRbgbaWlGQ6zSlC/lHArHvt8jr9mT7pR2t4gT4pzezDIRKFcUSClJA+6Dujm3h7vH8Y=@vger.kernel.org X-Gm-Message-State: AOJu0Yxx3leEWG1m1Kp94wjFXvaMhOdFpxbLlPvfGtE66MXf7MsBQuTZ uIzAp/qe32JPC8iYtW/K7ZppzZ3ud+Uxq62lyIOqudUamQJjJtkFjc7CPsALrFL+bi5CWXk5Ra4 ZHYlF7G28K+YKA+osbNS2XUFrVMFa/8PrTZ0p1WAvuxRG/T8WKlld6S/aNfs1+dVStnQ= X-Gm-Gg: ASbGncsRyFf9e1dHUwtiDRSQ7O0LahfIpe3s/8TbTk7pMge69FjlOaIoaRpYMZZ84ZP Vc26UWAlkLqXnyLIYV4qwaYwoq3CSCa3R0d1q7XIUfh4Jmhn1UtYCFNlr58wUQcouf7DoEFH1zz 2b/dIKaqeoD3BXL99ywjlGR2zB5jFDowxPcmqTbc6lXbhfoQmSzoWEA/nca3z/xiaBReFAueTgz ZQy9t/NyyEVbDzkyJXwowbS6Xwy5rRM7IEiyKxrTqHBvx6dZBsgLMJlzmpKE+YkONApMlmZ3U/I 6CxiFNJdN3s4Tjtik0vu4pHxU+x7hiW2s+6kk0xf3SEm2OVDnt0epl3VZtcAfxBq+wkO4me80TZ wCw== X-Received: by 2002:a17:903:18e:b0:237:7802:da30 with SMTP id d9443c01a7336-237d9a74d4amr249676985ad.31.1750745129471; Mon, 23 Jun 2025 23:05:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE+8VGvDMCZ73CeV5AtTxJ9YBH3JlGYKE++/duwsSfivQtp9438F3OMf8ih+tv26WkZtIRFKw== X-Received: by 2002:a17:903:18e:b0:237:7802:da30 with SMTP id d9443c01a7336-237d9a74d4amr249676745ad.31.1750745129144; Mon, 23 Jun 2025 23:05:29 -0700 (PDT) Received: from jiegan.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:28 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com, Konrad Dybcio Subject: [PATCH v3 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Date: Tue, 24 Jun 2025 14:04:38 +0800 Message-Id: <20250624060438.7469-11-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: IYGVQw-Rxb4KXzaY8GBHRZXO1WkbRzmi X-Authority-Analysis: v=2.4 cv=Id+HWXqa c=1 sm=1 tr=0 ts=685a402a cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=gBkj9RZkAcI1HbXH1KoA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: IYGVQw-Rxb4KXzaY8GBHRZXO1WkbRzmi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfX059IL3vhlNeI e/Wo/ZaDQBhzOsODxrqrvLqpPjnCaXmr23u2vcMRBbfLmj25rdUJSc7DGhR5ujS/EcG8d/IP5xH cPOmYp5cYTTQ85J+a/6oK80qeRcapW7ndwQxXhU+LF6I1pfhSfxdz+Btd64Q/asrQj8JJnFP0YV /eMX680Xpx5BPbS/MoZRfcAEVqyoy3TBxRwpIAk2KkqlQYBIE9mVQ84iR86FvlZYBpyD0zSVO8j SltRCJie+A3XYOnOvXUafJS56U/s7HCpSUMRPdDE3nzdOVZdooNBBl+wbFBNb/+Ru6APhI8/wuO 9zFo+/+jd0MlgN80lzll6QgUF9oc+xZUWZtZwLKbtLLcqBXOC3z4h1Ordfhjc0F3wJOFvDdJOKl o4EcVn3Has69GK56Rd7QSVLLaDVcP3f/8ZocZvJY+x37bmxuwKpiX6EeXAjPkRjbaAIPLT1t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 mlxlogscore=819 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Content-Type: text/plain; charset="utf-8" Add interrupts to enable byte-cntr function for TMC ETR devices. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index fed34717460f..44da72cebcf4 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2762,6 +2762,11 @@ ctcu@4001000 { clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + interrupt-names =3D "etr0", + "etr1"; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1