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However, a number of MCA initialization tasks only need to be done once. Define a function to collect all 'global' init tasks and call this from the BSP only. Start with CPU features. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250415-wip-mca-updates-v3-7-8ffd9eb4aa56@am= d.com =20 v3->v4: * Change cpu_mca_init() to mca_bsp_init(). * Drop code comment. =20 v2->v3: * Add tags from Qiuxu and Tony. =20 v1->v2: * New in v2. arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/cpu/mce/amd.c | 3 --- arch/x86/kernel/cpu/mce/core.c | 28 +++++++++++++++++++++------- 4 files changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 3224f3862dc8..31e3cb550fb3 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -241,12 +241,14 @@ struct cper_ia_proc_ctx; =20 #ifdef CONFIG_X86_MCE int mcheck_init(void); +void mca_bsp_init(struct cpuinfo_x86 *c); void mcheck_cpu_init(struct cpuinfo_x86 *c); void mcheck_cpu_clear(struct cpuinfo_x86 *c); int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id); #else static inline int mcheck_init(void) { return 0; } +static inline void mca_bsp_init(struct cpuinfo_x86 *c) {} static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {} static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_= info, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 8feb8fd2957a..8a00faa1042a 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1771,6 +1771,7 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) setup_clear_cpu_cap(X86_FEATURE_LA57); =20 detect_nopl(); + mca_bsp_init(c); } =20 void __init init_cpu_devs(void) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 292109e46a94..25a24d0b9cf9 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -655,9 +655,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low =3D 0, high =3D 0, address =3D 0; int offset =3D -1; =20 - mce_flags.overflow_recov =3D cpu_feature_enabled(X86_FEATURE_OVERFLOW_REC= OV); - mce_flags.succor =3D cpu_feature_enabled(X86_FEATURE_SUCCOR); - mce_flags.smca =3D cpu_feature_enabled(X86_FEATURE_SMCA); mce_flags.amd_threshold =3D 1; =20 for (bank =3D 0; bank < this_cpu_read(mce_num_banks); ++bank) { diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index ebe3e98f7606..c55462e6af1c 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1837,13 +1837,6 @@ static void __mcheck_cpu_cap_init(void) this_cpu_write(mce_num_banks, b); =20 __mcheck_cpu_mce_banks_init(); - - /* Use accurate RIP reporting if available. */ - if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >=3D 9) - mca_cfg.rip_msr =3D MSR_IA32_MCG_EIP; - - if (cap & MCG_SER_P) - mca_cfg.ser =3D 1; } =20 static void __mcheck_cpu_init_generic(void) @@ -2243,6 +2236,27 @@ DEFINE_IDTENTRY_RAW(exc_machine_check) } #endif =20 +void mca_bsp_init(struct cpuinfo_x86 *c) +{ + u64 cap; + + if (!mce_available(c)) + return; + + mce_flags.overflow_recov =3D cpu_feature_enabled(X86_FEATURE_OVERFLOW_REC= OV); + mce_flags.succor =3D cpu_feature_enabled(X86_FEATURE_SUCCOR); + mce_flags.smca =3D cpu_feature_enabled(X86_FEATURE_SMCA); + + rdmsrq(MSR_IA32_MCG_CAP, cap); + + /* Use accurate RIP reporting if available. */ + if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >=3D 9) + mca_cfg.rip_msr =3D MSR_IA32_MCG_EIP; + + if (cap & MCG_SER_P) + mca_cfg.ser =3D 1; +} + /* * Called for each booted CPU to set up machine checks. * Must be called with preempt off: --=20 2.49.0