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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CEA.mail.protection.outlook.com (10.167.242.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8880.14 via Frontend Transport; Tue, 24 Jun 2025 14:16:37 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 24 Jun 2025 09:16:31 -0500 From: Yazen Ghannam Date: Tue, 24 Jun 2025 14:16:05 +0000 Subject: [PATCH v4 10/22] x86/mce: Remove __mcheck_cpu_init_early() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250624-wip-mca-updates-v4-10-236dd74f645f@amd.com> References: <20250624-wip-mca-updates-v4-0-236dd74f645f@amd.com> In-Reply-To: <20250624-wip-mca-updates-v4-0-236dd74f645f@amd.com> To: , Tony Luck , "Rafael J. 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Currently, __mcheck_cpu_init_early() is only used on AMD-based systems and additional code will be needed to support various system configurations. However, the current and future vendor-specific code should be done during vendor init. This keeps all the vendor code in a common location and simplifies the generic init flow. Move all the __mcheck_cpu_init_early() code into mce_amd_feature_init(). Also, move __mcheck_cpu_init_generic() after __mcheck_cpu_init_prepare_banks() so that MCA is enabled after the first MCA polling event. Additionally, this brings the MCA init flow closer to what is described in the x86 docs. The AMD PPRs say "The operating system must initialize the MCA_CONFIG registers prior to initialization of the MCA_CTL registers. The MCA_CTL registers must be initialized prior to enabling the error reporting banks in MCG_CTL". However, the Intel SDM "Machine-Check Initialization Pseudocode" says MCG_CTL first then MCi_CTL. But both agree that CR4.MCE should be set last. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam Reviewed-by: Nikolay Borisov --- Notes: Link: https://lore.kernel.org/r/20250415-wip-mca-updates-v3-6-8ffd9eb4aa56@am= d.com =20 v3->v4: * No change. =20 v2->v3: * Update commit message. * Add tags from Qiuxu and Tony. =20 v1->v2: * New in v2, but based on old patch (see link). * Changed cpu_has() to cpu_feature_enabled(). arch/x86/kernel/cpu/mce/amd.c | 4 ++++ arch/x86/kernel/cpu/mce/core.c | 20 +++----------------- 2 files changed, 7 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 5d351ec863cd..292109e46a94 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -655,6 +655,10 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low =3D 0, high =3D 0, address =3D 0; int offset =3D -1; =20 + mce_flags.overflow_recov =3D cpu_feature_enabled(X86_FEATURE_OVERFLOW_REC= OV); + mce_flags.succor =3D cpu_feature_enabled(X86_FEATURE_SUCCOR); + mce_flags.smca =3D cpu_feature_enabled(X86_FEATURE_SMCA); + mce_flags.amd_threshold =3D 1; =20 for (bank =3D 0; bank < this_cpu_read(mce_num_banks); ++bank) { if (mce_flags.smca) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 486cddefaa7a..ebe3e98f7606 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2034,19 +2034,6 @@ static bool __mcheck_cpu_ancient_init(struct cpuinfo= _x86 *c) return false; } =20 -/* - * Init basic CPU features needed for early decoding of MCEs. - */ -static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) -{ - if (c->x86_vendor =3D=3D X86_VENDOR_AMD || c->x86_vendor =3D=3D X86_VENDO= R_HYGON) { - mce_flags.overflow_recov =3D !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); - mce_flags.succor =3D !!cpu_has(c, X86_FEATURE_SUCCOR); - mce_flags.smca =3D !!cpu_has(c, X86_FEATURE_SMCA); - mce_flags.amd_threshold =3D 1; - } -} - static void mce_centaur_feature_init(struct cpuinfo_x86 *c) { struct mca_config *cfg =3D &mca_cfg; @@ -2286,10 +2273,9 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) =20 mca_cfg.initialized =3D 1; =20 - __mcheck_cpu_init_early(c); - __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(c); __mcheck_cpu_init_prepare_banks(); + __mcheck_cpu_init_generic(); __mcheck_cpu_setup_timer(); } =20 @@ -2455,9 +2441,9 @@ static void mce_syscore_shutdown(void) */ static void mce_syscore_resume(void) { - __mcheck_cpu_init_generic(); __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); __mcheck_cpu_init_prepare_banks(); + __mcheck_cpu_init_generic(); } =20 static struct syscore_ops mce_syscore_ops =3D { @@ -2474,8 +2460,8 @@ static void mce_cpu_restart(void *data) { if (!mce_available(raw_cpu_ptr(&cpu_info))) return; - __mcheck_cpu_init_generic(); __mcheck_cpu_init_prepare_banks(); + __mcheck_cpu_init_generic(); __mcheck_cpu_init_timer(); } =20 --=20 2.49.0