From nobody Wed Oct 8 22:30:20 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C82B1DEFE6 for ; Tue, 24 Jun 2025 04:40:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750740055; cv=none; b=hpcyIWahIKR6Ko8L57YaG5GShexIcwZcZ2g1J1k61SdCfX3zG+uF1adnywQ1/40URLJbidk3d1QULdHBEv+K1A9hXvTElh2O2ZiqNQahBb1ZAgmLfl+mrOJpsCqbOiCXrP3Jj9D1vdr5Uo+3yBpurCFG3yvGhaJ8xe9qbdHwBvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750740055; c=relaxed/simple; bh=pKNCgLJnf6kMka63qFgcEq8rakhenaJR7dI+6P8r2ww=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:To:CC; b=Eu/+AKJH1fxqf7jYe1l8owSrVRnLwJyDxC/faHOLPoEcHN7H+eSe3+dYxsKCQ/6eLIP6B24Ug2/hipMCRc6h+4cGDpJ1RnPZVIwu8U4Hc1urqbWW/QdrhqhSHI5y4sJxQP/bDtl9t2+XDEYGMKaPbBqibbwbBSwpP86DgLR4ac8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=wuirvd9A; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="wuirvd9A" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750740054; x=1782276054; h=from:date:subject:mime-version:content-transfer-encoding: message-id:to:cc; bh=pKNCgLJnf6kMka63qFgcEq8rakhenaJR7dI+6P8r2ww=; b=wuirvd9AohdkdJmO1IO4rD63EoRxgX1bEx0biYWBe4vscFfVflbNYCd6 Jd9m/ENUQmQwaBC4rU1jSUrJXe2AgA4yhRX+spV6TE8cYMHrBujy71UyB D7MNjqTUGDTK097d1KHPiuj0vAM/yKq8ZxpaBlwu6qeWQ9sGOe0PP4Z6H ELtQ0os5Jsh4fiAqIs0spq/nZ/FwhuYnGqQv1eZaX+Rt5NwZy/r6TkxNF NTu8nlFJrunM8XqroAe6P6XZnplf/XZdn62F73BEEz5Gsg1M0Kdk9keAZ xXtepD2sfJsDAEi6HBwIWX0lfUP9fulmIh+6r3kZq4xu85btXMmfcMwtF A==; X-CSE-ConnectionGUID: GtONl7zMSai6tNbRkKAjGw== X-CSE-MsgGUID: XKy5sicpT0OGvGLTHsMnCQ== X-IronPort-AV: E=Sophos;i="6.16,260,1744095600"; d="scan'208";a="43142583" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Jun 2025 21:40:53 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 23 Jun 2025 21:40:34 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 23 Jun 2025 21:40:28 -0700 From: Dharma Balasubiramani Date: Tue, 24 Jun 2025 10:10:25 +0530 Subject: [PATCH v3] drm/bridge: microchip-lvds: fix bus format mismatch with VESA displays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250624-microchip-lvds-v3-1-c3c6f1e40516@microchip.com> X-B4-Tracking: v=1; b=H4sIADgsWmgC/3XMzwrCMAwG8FcZOVtZu3V/PPke4qFLowu4dbRSl LF3t9tBRJGQw/eR/GYI5JkCHLIZPEUO7MYUil0G2JvxSoJtyqBypfNKNmJg9A57nsQt2iC6Wmp p2ypvSwPpafJ04ccGns4p9xzuzj83P8q1/UtFKdKQIW3Q1qZRx/fBHt0AKxfVB6GKH0IloiHsT IdV2vKbWJblBQfIgnPzAAAA To: Manikandan Muralidharan , Andrzej Hajda , Neil Armstrong , "Robert Foss" , Laurent Pinchart , Jonas Karlman , "Jernej Skrabec" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , "Sandeep Sheriker M" , Dharma Balasubiramani X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750740026; l=6378; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=8SIX3YXqjCEtRZTW6QbWQPaH0ZBHGs4QIObijOpd9GQ=; b=vaVv2H8IrmgDDLaeIQ0pLj1YjRohi4JHZd6bantEQA+cwls6BW5qxyygT0zj/pOLAZx7FeDpi p/dpGe4X+/yDnN4cgJ+bag6hK9yjSniqQjj89HM2MTlfRRyLk6N5TT3 X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= From: Sandeep Sheriker M The LVDS controller was hardcoded to JEIDA mapping, which leads to distorted output on panels expecting VESA mapping. Update the driver to dynamically select the appropriate mapping and pixel size based on the panel's advertised media bus format. This ensures compatibility with both JEIDA and VESA displays. Modernize the bridge ops to use atomic_enable/disable, and retrieve the bus format from the connector via the atomic bridge state. Additionally, drop the drm_panel field as it is unused. Signed-off-by: Sandeep Sheriker M Signed-off-by: Dharma Balasubiramani --- Changes in v3: - Use BIT(0) instead of 1. - Drop the panel field of the mchp_lvds structure. - Drop the inner parentheses in write in serialiser_on(). - Link to v2: https://lore.kernel.org/r/20250623-microchip-lvds-v2-1-8ecbab= c6abc4@microchip.com Changes in v2: - Switch to atomic bridge functions - Drop custom connector creation - Use drm_atomic_get_new_connector_for_encoder() - Link to v1: https://lore.kernel.org/r/20250618-microchip-lvds-v1-1-1eae5a= cd7a82@microchip.com --- drivers/gpu/drm/bridge/microchip-lvds.c | 70 +++++++++++++++++++++++++----= ---- 1 file changed, 54 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/brid= ge/microchip-lvds.c index 9f4ff82bc6b4..e7b68fb4bec0 100644 --- a/drivers/gpu/drm/bridge/microchip-lvds.c +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -41,9 +42,11 @@ =20 /* Bitfields in LVDSC_CFGR (Configuration Register) */ #define LVDSC_CFGR_PIXSIZE_24BITS 0 +#define LVDSC_CFGR_PIXSIZE_18BITS BIT(0) #define LVDSC_CFGR_DEN_POL_HIGH 0 #define LVDSC_CFGR_DC_UNBALANCED 0 #define LVDSC_CFGR_MAPPING_JEIDA BIT(6) +#define LVDSC_CFGR_MAPPING_VESA 0 =20 /*Bitfields in LVDSC_SR */ #define LVDSC_SR_CS BIT(0) @@ -56,7 +59,6 @@ struct mchp_lvds { struct device *dev; void __iomem *regs; struct clk *pclk; - struct drm_panel *panel; struct drm_bridge bridge; struct drm_bridge *panel_bridge; }; @@ -76,9 +78,10 @@ static inline void lvds_writel(struct mchp_lvds *lvds, u= 32 offset, u32 val) writel_relaxed(val, lvds->regs + offset); } =20 -static void lvds_serialiser_on(struct mchp_lvds *lvds) +static void lvds_serialiser_on(struct mchp_lvds *lvds, u32 bus_format) { unsigned long timeout =3D jiffies + msecs_to_jiffies(LVDS_POLL_TIMEOUT_MS= ); + u8 map, pix_size; =20 /* The LVDSC registers can only be written if WPEN is cleared */ lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD & @@ -93,11 +96,24 @@ static void lvds_serialiser_on(struct mchp_lvds *lvds) usleep_range(1000, 2000); } =20 + switch (bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + map =3D LVDSC_CFGR_MAPPING_JEIDA; + pix_size =3D LVDSC_CFGR_PIXSIZE_18BITS; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + map =3D LVDSC_CFGR_MAPPING_VESA; + pix_size =3D LVDSC_CFGR_PIXSIZE_24BITS; + break; + default: + map =3D LVDSC_CFGR_MAPPING_JEIDA; + pix_size =3D LVDSC_CFGR_PIXSIZE_24BITS; + break; + } + /* Configure the LVDSC */ - lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA | - LVDSC_CFGR_DC_UNBALANCED | - LVDSC_CFGR_DEN_POL_HIGH | - LVDSC_CFGR_PIXSIZE_24BITS)); + lvds_writel(lvds, LVDSC_CFGR, map | LVDSC_CFGR_DC_UNBALANCED | + LVDSC_CFGR_DEN_POL_HIGH | pix_size); =20 /* Enable the LVDS serializer */ lvds_writel(lvds, LVDSC_CR, LVDSC_CR_SER_EN); @@ -113,7 +129,8 @@ static int mchp_lvds_attach(struct drm_bridge *bridge, bridge, flags); } =20 -static void mchp_lvds_enable(struct drm_bridge *bridge) +static void mchp_lvds_atomic_pre_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) { struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); int ret; @@ -129,11 +146,35 @@ static void mchp_lvds_enable(struct drm_bridge *bridg= e) dev_err(lvds->dev, "failed to get pm runtime: %d\n", ret); return; } +} + +static void mchp_lvds_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); + struct drm_connector *connector; + + /* default to jeida-24 */ + u32 bus_format =3D MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA; + + connector =3D drm_atomic_get_new_connector_for_encoder(state, bridge->enc= oder); + if (connector && connector->display_info.num_bus_formats) + bus_format =3D connector->display_info.bus_formats[0]; =20 - lvds_serialiser_on(lvds); + lvds_serialiser_on(lvds, bus_format); } =20 -static void mchp_lvds_disable(struct drm_bridge *bridge) +static void mchp_lvds_atomic_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); + + /* Turn off the serialiser */ + lvds_writel(lvds, LVDSC_CR, 0); +} + +static void mchp_lvds_atomic_post_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) { struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); =20 @@ -143,8 +184,10 @@ static void mchp_lvds_disable(struct drm_bridge *bridg= e) =20 static const struct drm_bridge_funcs mchp_lvds_bridge_funcs =3D { .attach =3D mchp_lvds_attach, - .enable =3D mchp_lvds_enable, - .disable =3D mchp_lvds_disable, + .atomic_pre_enable =3D mchp_lvds_atomic_pre_enable, + .atomic_enable =3D mchp_lvds_atomic_enable, + .atomic_disable =3D mchp_lvds_atomic_disable, + .atomic_post_disable =3D mchp_lvds_atomic_post_disable, }; =20 static int mchp_lvds_probe(struct platform_device *pdev) @@ -179,13 +222,8 @@ static int mchp_lvds_probe(struct platform_device *pde= v) "can't find port point, please init lvds panel port!\n"); return -ENODEV; } - - lvds->panel =3D of_drm_find_panel(port); of_node_put(port); =20 - if (IS_ERR(lvds->panel)) - return -EPROBE_DEFER; - lvds->panel_bridge =3D devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); =20 if (IS_ERR(lvds->panel_bridge)) --- base-commit: 4325743c7e209ae7845293679a4de94b969f2bef change-id: 20250618-microchip-lvds-b7151d96094a Best regards, --=20 Dharma Balasubiramani