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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski As the first step in removing the fields specific to the gpio-mmio module from struct gpio_chip, we introduce a new set of generic GPIO chip interfaces that are meant to replace the existing bgpio_ ones. The new initialization function - gpio_generic_chip_init() - takes a configuration structure as argument instead of 9 separate parameters. This will allow easy extension if needed in the future. We hide the locking details behind a set of helpers in order to be able to move the raw spinlock out of struct gpio_chip without the users noticing. For now, the new APIs just wrap the existing ones. Once all users have been converted to the new interfaces, we'll pull them into gpio-mmio and implement them in a backward-compatible way while also moving all fields specific to the generic GPIO chip into struct gpio_generic_chip. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- include/linux/gpio/generic.h | 120 +++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 120 insertions(+) diff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h new file mode 100644 index 0000000000000000000000000000000000000000..b511acd58ab0099b727bf929b7a= 4e9f9836cd5bc --- /dev/null +++ b/include/linux/gpio/generic.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __LINUX_GPIO_GENERIC_H +#define __LINUX_GPIO_GENERIC_H + +#include +#include +#include + +struct device; + +/** + * struct gpio_generic_chip_config - Generic GPIO chip configuration data + * @dev: Parent device of the new GPIO chip (compulsory). + * @sz: Size (width) of the MMIO registers in bytes, typically 1, 2 or 4. + * @dat: MMIO address for the register to READ the value of the GPIO lines= , it + * is expected that a 1 in the corresponding bit in this register me= ans + * the line is asserted. + * @set: MMIO address for the register to SET the value of the GPIO lines,= it + * is expected that we write the line with 1 in this register to dri= ve + * the GPIO line high. + * @clr: MMIO address for the register to CLEAR the value of the GPIO line= s, + * it is expected that we write the line with 1 in this register to + * drive the GPIO line low. It is allowed to leave this address as N= ULL, + * in that case the SET register will be assumed to also clear the G= PIO + * lines, by actively writing the line with 0. + * @dirout: MMIO address for the register to set the line as OUTPUT. It is + * assumed that setting a line to 1 in this register will turn th= at + * line into an output line. Conversely, setting the line to 0 wi= ll + * turn that line into an input. + * @dirin: MMIO address for the register to set this line as INPUT. It is + * assumed that setting a line to 1 in this register will turn that + * line into an input line. Conversely, setting the line to 0 will + * turn that line into an output. + * @flags: Different flags that will affect the behaviour of the device, s= uch + * as endianness etc. + */ +struct gpio_generic_chip_config { + struct device *dev; + unsigned long sz; + void __iomem *dat; + void __iomem *set; + void __iomem *clr; + void __iomem *dirout; + void __iomem *dirin; + unsigned long flags; +}; + +/** + * struct gpio_generic_chip - Generic GPIO chip implementation. + * @gc: The underlying struct gpio_chip object, implementing low-level GPIO + * chip routines. + */ +struct gpio_generic_chip { + struct gpio_chip gc; +}; + +/** + * gpio_generic_chip_init() - Initialize a generic GPIO chip. + * @chip: Generic GPIO chip to set up. + * @cfg: Generic GPIO chip configuration. + * + * Returns 0 on success, negative error number on failure. + */ +static inline int +gpio_generic_chip_init(struct gpio_generic_chip *chip, + const struct gpio_generic_chip_config *cfg) +{ + return bgpio_init(&chip->gc, cfg->dev, cfg->sz, cfg->dat, cfg->set, + cfg->clr, cfg->dirout, cfg->dirin, cfg->flags); +} + +/** + * gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO c= hip. + * @chip: Generic GPIO chip to use. + * @offset: Hardware offset of the line to set. + * @value: New GPIO line value. + * + * Some modules using the generic GPIO chip, need to set line values in th= eir + * direction setters but they don't have access to the gpio-mmio symbols so + * they use the function pointer in struct gpio_chip directly. This is not + * optimal and can lead to crashes at run-time in some instances. This wra= pper + * provides a safe interface for users. + * + * Returns: 0 on success, negative error number of failure. + */ +static inline int +gpio_generic_chip_set(struct gpio_generic_chip *chip, unsigned int offset, + int value) +{ + if (WARN_ON(!chip->gc.set_rv)) + return -EOPNOTSUPP; + + return chip->gc.set_rv(&chip->gc, offset, value); +} + +#define gpio_generic_chip_lock(gen_gc) \ + raw_spin_lock(&(gen_gc)->gc.bgpio_lock) + +#define gpio_generic_chip_unlock(gen_gc) \ + raw_spin_unlock(&(gen_gc)->gc.bgpio_lock) + +#define gpio_generic_chip_lock_irqsave(gen_gc, flags) \ + raw_spin_lock_irqsave(&(gen_gc)->gc.bgpio_lock, flags) + +#define gpio_generic_chip_unlock_irqrestore(gen_gc, flags) \ + raw_spin_unlock_irqrestore(&(gen_gc)->gc.bgpio_lock, flags) + +DEFINE_LOCK_GUARD_1(gpio_generic_lock, + struct gpio_generic_chip, + gpio_generic_chip_lock(_T->lock), + gpio_generic_chip_unlock(_T->lock)) + +DEFINE_LOCK_GUARD_1(gpio_generic_lock_irqsave, + struct gpio_generic_chip, + gpio_generic_chip_lock_irqsave(_T->lock, _T->flags), + gpio_generic_chip_unlock_irqrestore(_T->lock, _T->flags), + unsigned long flags) + +#endif /* __LINUX_GPIO_GENERIC_H */ --=20 2.48.1 From nobody Wed Oct 8 20:52:46 2025 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 303AD2C15A1 for ; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Simplify the code by using lock guards for the bgpio_lock. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mxc.c | 50 ++++++++++++++++++++++-----------------------= ---- 1 file changed, 22 insertions(+), 28 deletions(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 4af5a2972d12f68909dd87d9396921c80445f87c..1c37168c8d0a657d7f93067d9ac= 95cfbd821f757 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -7,6 +7,7 @@ // Authors: Daniel Mack, Juergen Beisert. // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserv= ed. =20 +#include #include #include #include @@ -161,7 +162,6 @@ static int gpio_set_irq_type(struct irq_data *d, u32 ty= pe) { struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port =3D gc->private; - unsigned long flags; u32 bit, val; u32 gpio_idx =3D d->hwirq; int edge; @@ -200,41 +200,38 @@ static int gpio_set_irq_type(struct irq_data *d, u32 = type) return -EINVAL; } =20 - raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); + scoped_guard(raw_spinlock_irqsave, &port->gc.bgpio_lock) { + if (GPIO_EDGE_SEL >=3D 0) { + val =3D readl(port->base + GPIO_EDGE_SEL); + if (edge =3D=3D GPIO_INT_BOTH_EDGES) + writel(val | (1 << gpio_idx), + port->base + GPIO_EDGE_SEL); + else + writel(val & ~(1 << gpio_idx), + port->base + GPIO_EDGE_SEL); + } =20 - if (GPIO_EDGE_SEL >=3D 0) { - val =3D readl(port->base + GPIO_EDGE_SEL); - if (edge =3D=3D GPIO_INT_BOTH_EDGES) - writel(val | (1 << gpio_idx), - port->base + GPIO_EDGE_SEL); - else - writel(val & ~(1 << gpio_idx), - port->base + GPIO_EDGE_SEL); + if (edge !=3D GPIO_INT_BOTH_EDGES) { + reg +=3D GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper regist= er */ + bit =3D gpio_idx & 0xf; + val =3D readl(reg) & ~(0x3 << (bit << 1)); + writel(val | (edge << (bit << 1)), reg); + } + + writel(1 << gpio_idx, port->base + GPIO_ISR); + port->pad_type[gpio_idx] =3D type; } =20 - if (edge !=3D GPIO_INT_BOTH_EDGES) { - reg +=3D GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper registe= r */ - bit =3D gpio_idx & 0xf; - val =3D readl(reg) & ~(0x3 << (bit << 1)); - writel(val | (edge << (bit << 1)), reg); - } - - writel(1 << gpio_idx, port->base + GPIO_ISR); - port->pad_type[gpio_idx] =3D type; - - raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); - return port->gc.direction_input(&port->gc, gpio_idx); } =20 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) { void __iomem *reg =3D port->base; - unsigned long flags; u32 bit, val; int edge; =20 - raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); + guard(raw_spinlock_irqsave)(&port->gc.bgpio_lock); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mxc.c | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 1c37168c8d0a657d7f93067d9ac95cfbd821f757..433cbadc3a4cc67ebc89a470228= 0975fa8d2c9bc 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include =20 @@ -65,7 +66,7 @@ struct mxc_gpio_port { int irq_high; void (*mx_irq_handler)(struct irq_desc *desc); struct irq_domain *domain; - struct gpio_chip gc; + struct gpio_generic_chip gen_gc; struct device *dev; u32 both_edges; struct mxc_gpio_reg_saved gpio_saved_reg; @@ -179,7 +180,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 ty= pe) if (GPIO_EDGE_SEL >=3D 0) { edge =3D GPIO_INT_BOTH_EDGES; } else { - val =3D port->gc.get(&port->gc, gpio_idx); + val =3D port->gen_gc.gc.get(&port->gen_gc.gc, gpio_idx); if (val) { edge =3D GPIO_INT_LOW_LEV; pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); @@ -200,7 +201,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 ty= pe) return -EINVAL; } =20 - scoped_guard(raw_spinlock_irqsave, &port->gc.bgpio_lock) { + scoped_guard(gpio_generic_lock_irqsave, &port->gen_gc) { if (GPIO_EDGE_SEL >=3D 0) { val =3D readl(port->base + GPIO_EDGE_SEL); if (edge =3D=3D GPIO_INT_BOTH_EDGES) @@ -222,7 +223,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 ty= pe) port->pad_type[gpio_idx] =3D type; } =20 - return port->gc.direction_input(&port->gc, gpio_idx); + return port->gen_gc.gc.direction_input(&port->gen_gc.gc, gpio_idx); } =20 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) @@ -231,7 +232,7 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u= 32 gpio) u32 bit, val; int edge; =20 - guard(raw_spinlock_irqsave)(&port->gc.bgpio_lock); + guard(gpio_generic_lock_irqsave)(&port->gen_gc); =20 reg +=3D GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ bit =3D gpio & 0xf; @@ -414,6 +415,7 @@ static void mxc_update_irq_chained_handler(struct mxc_g= pio_port *port, bool enab =20 static int mxc_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config =3D { }; struct device_node *np =3D pdev->dev.of_node; struct mxc_gpio_port *port; int irq_count; @@ -473,27 +475,31 @@ static int mxc_gpio_probe(struct platform_device *pde= v) port->mx_irq_handler =3D mx3_gpio_irq_handler; =20 mxc_update_irq_chained_handler(port, true); - err =3D bgpio_init(&port->gc, &pdev->dev, 4, - port->base + GPIO_PSR, - port->base + GPIO_DR, NULL, - port->base + GPIO_GDIR, NULL, - BGPIOF_READ_OUTPUT_REG_SET); + + config.dev =3D &pdev->dev; + config.sz =3D 4; + config.dat =3D port->base + GPIO_PSR; + config.set =3D port->base + GPIO_DR; + config.dirout =3D port->base + GPIO_GDIR; + config.flags =3D BGPIOF_READ_OUTPUT_REG_SET; + + err =3D gpio_generic_chip_init(&port->gen_gc, &config); if (err) goto out_bgio; =20 - port->gc.request =3D mxc_gpio_request; - port->gc.free =3D mxc_gpio_free; - port->gc.to_irq =3D mxc_gpio_to_irq; + port->gen_gc.gc.request =3D mxc_gpio_request; + port->gen_gc.gc.free =3D mxc_gpio_free; + port->gen_gc.gc.to_irq =3D mxc_gpio_to_irq; /* * Driver is DT-only, so a fixed base needs only be maintained for legacy * userspace with sysfs interface. */ if (IS_ENABLED(CONFIG_GPIO_SYSFS)) - port->gc.base =3D of_alias_get_id(np, "gpio") * 32; + port->gen_gc.gc.base =3D of_alias_get_id(np, "gpio") * 32; else /* silence boot time warning */ - port->gc.base =3D -1; + port->gen_gc.gc.base =3D -1; =20 - err =3D devm_gpiochip_add_data(&pdev->dev, &port->gc, port); + err =3D devm_gpiochip_add_data(&pdev->dev, &port->gen_gc.gc, port); if (err) goto out_bgio; =20 @@ -567,7 +573,8 @@ static bool mxc_gpio_generic_config(struct mxc_gpio_por= t *port, if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") || of_device_is_compatible(np, "fsl,imx8qxp-gpio") || of_device_is_compatible(np, "fsl,imx8qm-gpio")) - return (gpiochip_generic_config(&port->gc, offset, conf) =3D=3D 0); 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Tue, 24 Jun 2025 06:27:47 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:34d2:109c:3293:19e9]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-453632312a3sm152588485e9.1.2025.06.24.06.27.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 06:27:46 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 24 Jun 2025 15:27:36 +0200 Subject: [PATCH 4/8] gpio: clps711x: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250624-gpio-mmio-rework-v1-4-aea12209d258@linaro.org> References: <20250624-gpio-mmio-rework-v1-0-aea12209d258@linaro.org> In-Reply-To: <20250624-gpio-mmio-rework-v1-0-aea12209d258@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-clps711x.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c index d69a24dd4828975b4d62f66b011964456976bfa6..397b347ad6e8b036edbfff75b6a= 31f2170334f66 100644 --- a/drivers/gpio/gpio-clps711x.c +++ b/drivers/gpio/gpio-clps711x.c @@ -8,13 +8,15 @@ #include #include #include +#include #include =20 static int clps711x_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config =3D { }; struct device_node *np =3D pdev->dev.of_node; + struct gpio_generic_chip *gen_gc; void __iomem *dat, *dir; - struct gpio_chip *gc; int err, id; =20 if (!np) @@ -24,8 +26,8 @@ static int clps711x_gpio_probe(struct platform_device *pd= ev) if ((id < 0) || (id > 4)) return -ENODEV; =20 - gc =3D devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); - if (!gc) + gen_gc =3D devm_kzalloc(&pdev->dev, sizeof(*gen_gc), GFP_KERNEL); + if (!gen_gc) return -ENOMEM; =20 dat =3D devm_platform_ioremap_resource(pdev, 0); @@ -36,35 +38,38 @@ static int clps711x_gpio_probe(struct platform_device *= pdev) if (IS_ERR(dir)) return PTR_ERR(dir); =20 + config.dev =3D &pdev->dev; + config.sz =3D 1; + config.dat =3D dat; + switch (id) { case 3: /* PORTD is inverted logic for direction register */ - err =3D bgpio_init(gc, &pdev->dev, 1, dat, NULL, NULL, - NULL, dir, 0); + config.dirin =3D dir; break; default: - err =3D bgpio_init(gc, &pdev->dev, 1, dat, NULL, NULL, - dir, NULL, 0); + config.dirout =3D dir; break; } =20 + err =3D gpio_generic_chip_init(gen_gc, &config); if (err) return err; =20 switch (id) { case 4: /* PORTE is 3 lines only */ - gc->ngpio =3D 3; + gen_gc->gc.ngpio =3D 3; break; default: break; } =20 - gc->base =3D -1; - gc->owner =3D THIS_MODULE; - platform_set_drvdata(pdev, gc); + gen_gc->gc.base =3D -1; + gen_gc->gc.owner =3D THIS_MODULE; + platform_set_drvdata(pdev, &gen_gc->gc); =20 - return devm_gpiochip_add_data(&pdev->dev, gc, NULL); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Simplify the code by using lock guards for the bgpio_lock. While at it: move the gpio/driver.h include into its correct place alphabetically. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-cadence.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio-cadence.c b/drivers/gpio/gpio-cadence.c index e9dd2564c54f879cf1d49442dfa3db0004473d35..e6ec341d55e9047b2fa8718799b= a72d54624388e 100644 --- a/drivers/gpio/gpio-cadence.c +++ b/drivers/gpio/gpio-cadence.c @@ -8,8 +8,9 @@ * Boris Brezillon */ =20 -#include +#include #include +#include #include #include #include @@ -38,29 +39,24 @@ struct cdns_gpio_chip { static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct cdns_gpio_chip *cgpio =3D gpiochip_get_data(chip); - unsigned long flags; =20 - raw_spin_lock_irqsave(&chip->bgpio_lock, flags); + guard(raw_spinlock)(&chip->bgpio_lock); =20 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset), cgpio->regs + CDNS_GPIO_BYPASS_MODE); =20 - raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags); return 0; } =20 static void cdns_gpio_free(struct gpio_chip *chip, unsigned int offset) { struct cdns_gpio_chip *cgpio =3D gpiochip_get_data(chip); - unsigned long flags; =20 - raw_spin_lock_irqsave(&chip->bgpio_lock, flags); + guard(raw_spinlock)(&chip->bgpio_lock); =20 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) | (BIT(offset) & cgpio->bypass_orig), cgpio->regs + CDNS_GPIO_BYPASS_MODE); - - raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags); } =20 static void cdns_gpio_irq_mask(struct irq_data *d) @@ -85,13 +81,12 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, u= nsigned int type) { struct gpio_chip *chip =3D irq_data_get_irq_chip_data(d); struct cdns_gpio_chip *cgpio =3D gpiochip_get_data(chip); - unsigned long flags; u32 int_value; u32 int_type; u32 mask =3D BIT(d->hwirq); int ret =3D 0; =20 - raw_spin_lock_irqsave(&chip->bgpio_lock, flags); + guard(raw_spinlock)(&chip->bgpio_lock); =20 int_value =3D ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask; int_type =3D ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask; @@ -108,15 +103,12 @@ static int cdns_gpio_irq_set_type(struct irq_data *d,= unsigned int type) } else if (type =3D=3D IRQ_TYPE_LEVEL_LOW) { int_type |=3D mask; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-cadence.c | 46 ++++++++++++++++++++++++-----------------= ---- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/drivers/gpio/gpio-cadence.c b/drivers/gpio/gpio-cadence.c index e6ec341d55e9047b2fa8718799ba72d54624388e..8243eddcd5bbe537bab1bedc72c= 80ee88839f5d3 100644 --- a/drivers/gpio/gpio-cadence.c +++ b/drivers/gpio/gpio-cadence.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -31,7 +33,7 @@ #define CDNS_GPIO_IRQ_ANY_EDGE 0x2c =20 struct cdns_gpio_chip { - struct gpio_chip gc; + struct gpio_generic_chip gen_gc; void __iomem *regs; u32 bypass_orig; }; @@ -40,7 +42,7 @@ static int cdns_gpio_request(struct gpio_chip *chip, unsi= gned int offset) { struct cdns_gpio_chip *cgpio =3D gpiochip_get_data(chip); =20 - guard(raw_spinlock)(&chip->bgpio_lock); + guard(gpio_generic_lock)(&cgpio->gen_gc); =20 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset), cgpio->regs + CDNS_GPIO_BYPASS_MODE); @@ -52,7 +54,7 @@ static void cdns_gpio_free(struct gpio_chip *chip, unsign= ed int offset) { struct cdns_gpio_chip *cgpio =3D gpiochip_get_data(chip); =20 - guard(raw_spinlock)(&chip->bgpio_lock); + guard(gpio_generic_lock)(&cgpio->gen_gc); =20 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) | (BIT(offset) & cgpio->bypass_orig), @@ -86,7 +88,7 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, uns= igned int type) u32 mask =3D BIT(d->hwirq); int ret =3D 0; =20 - guard(raw_spinlock)(&chip->bgpio_lock); + guard(gpio_generic_lock)(&cgpio->gen_gc); =20 int_value =3D ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask; int_type =3D ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask; @@ -142,6 +144,7 @@ static const struct irq_chip cdns_gpio_irqchip =3D { =20 static int cdns_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config =3D { }; struct cdns_gpio_chip *cgpio; int ret, irq; u32 dir_prev; @@ -168,32 +171,33 @@ static int cdns_gpio_probe(struct platform_device *pd= ev) * gpiochip_lock_as_irq: * tried to flag a GPIO set as output for IRQ * Generic GPIO driver stores the direction value internally, - * so it needs to be changed before bgpio_init() is called. + * so it needs to be changed before gpio_generic_chip_init() is called. */ dir_prev =3D ioread32(cgpio->regs + CDNS_GPIO_DIRECTION_MODE); iowrite32(GENMASK(num_gpios - 1, 0), cgpio->regs + CDNS_GPIO_DIRECTION_MODE); =20 - ret =3D bgpio_init(&cgpio->gc, &pdev->dev, 4, - cgpio->regs + CDNS_GPIO_INPUT_VALUE, - cgpio->regs + CDNS_GPIO_OUTPUT_VALUE, - NULL, - NULL, - cgpio->regs + CDNS_GPIO_DIRECTION_MODE, - BGPIOF_READ_OUTPUT_REG_SET); + config.dev =3D &pdev->dev; + config.sz =3D 4; + config.dat =3D cgpio->regs + CDNS_GPIO_INPUT_VALUE; + config.set =3D cgpio->regs + CDNS_GPIO_OUTPUT_VALUE; + config.dirin =3D cgpio->regs + CDNS_GPIO_DIRECTION_MODE; + config.flags =3D BGPIOF_READ_OUTPUT_REG_SET; + + ret =3D gpio_generic_chip_init(&cgpio->gen_gc, &config); if (ret) { dev_err(&pdev->dev, "Failed to register generic gpio, %d\n", ret); goto err_revert_dir; } =20 - cgpio->gc.label =3D dev_name(&pdev->dev); - cgpio->gc.ngpio =3D num_gpios; - cgpio->gc.parent =3D &pdev->dev; - cgpio->gc.base =3D -1; - cgpio->gc.owner =3D THIS_MODULE; - cgpio->gc.request =3D cdns_gpio_request; - cgpio->gc.free =3D cdns_gpio_free; + cgpio->gen_gc.gc.label =3D dev_name(&pdev->dev); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-74xx-mmio.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-74xx-mmio.c b/drivers/gpio/gpio-74xx-mmio.c index 3ba21add3a1c669171578ceaf9cc1728c060d401..bd2cc5f4f851650a499382b050a= 556506f4c5031 100644 --- a/drivers/gpio/gpio-74xx-mmio.c +++ b/drivers/gpio/gpio-74xx-mmio.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -18,8 +19,8 @@ #define MMIO_74XX_BIT_CNT(x) ((x) & GENMASK(7, 0)) =20 struct mmio_74xx_gpio_priv { - struct gpio_chip gc; - unsigned flags; + struct gpio_generic_chip gen_gc; + unsigned int flags; }; =20 static const struct of_device_id mmio_74xx_gpio_ids[] =3D { @@ -99,16 +100,15 @@ static int mmio_74xx_dir_out(struct gpio_chip *gc, uns= igned int gpio, int val) { struct mmio_74xx_gpio_priv *priv =3D gpiochip_get_data(gc); =20 - if (priv->flags & MMIO_74XX_DIR_OUT) { - gc->set_rv(gc, gpio, val); - return 0; - } + if (priv->flags & MMIO_74XX_DIR_OUT) + return gpio_generic_chip_set(&priv->gen_gc, gpio, val); =20 return -ENOTSUPP; } =20 static int mmio_74xx_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config =3D { }; struct mmio_74xx_gpio_priv *priv; void __iomem *dat; int err; @@ -123,19 +123,21 @@ static int mmio_74xx_gpio_probe(struct platform_devic= e *pdev) if (IS_ERR(dat)) return PTR_ERR(dat); =20 - err =3D bgpio_init(&priv->gc, &pdev->dev, - DIV_ROUND_UP(MMIO_74XX_BIT_CNT(priv->flags), 8), - dat, NULL, NULL, NULL, NULL, 0); + config.dev =3D &pdev->dev; + config.sz =3D DIV_ROUND_UP(MMIO_74XX_BIT_CNT(priv->flags), 8); + config.dat =3D dat; + + err =3D gpio_generic_chip_init(&priv->gen_gc, &config); if (err) return err; =20 - priv->gc.direction_input =3D mmio_74xx_dir_in; - priv->gc.direction_output =3D mmio_74xx_dir_out; - priv->gc.get_direction =3D mmio_74xx_get_direction; - priv->gc.ngpio =3D MMIO_74XX_BIT_CNT(priv->flags); - priv->gc.owner =3D THIS_MODULE; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-en7523.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpio/gpio-en7523.c b/drivers/gpio/gpio-en7523.c index c08069d0d1045e9df4a76cad4600bf25d4e3a7c5..cf47afc578a9cea1fb1adb97f51= b143b13c66ab1 100644 --- a/drivers/gpio/gpio-en7523.c +++ b/drivers/gpio/gpio-en7523.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -13,28 +14,23 @@ =20 /** * struct airoha_gpio_ctrl - Airoha GPIO driver data - * @gc: Associated gpio_chip instance. + * @gen_gc: Associated gpio_generic_chip instance. * @data: The data register. * @dir: [0] The direction register for the lower 16 pins. * [1]: The direction register for the higher 16 pins. * @output: The output enable register. */ struct airoha_gpio_ctrl { - struct gpio_chip gc; + struct gpio_generic_chip gen_gc; void __iomem *data; void __iomem *dir[2]; void __iomem *output; }; =20 -static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc) -{ - return container_of(gc, struct airoha_gpio_ctrl, gc); -} - static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio, int val, int out) { - struct airoha_gpio_ctrl *ctrl =3D gc_to_ctrl(gc); + struct airoha_gpio_ctrl *ctrl =3D gpiochip_get_data(gc); u32 dir =3D ioread32(ctrl->dir[gpio / 16]); u32 output =3D ioread32(ctrl->output); u32 mask =3D BIT((gpio % 16) * 2); @@ -50,7 +46,7 @@ static int airoha_dir_set(struct gpio_chip *gc, unsigned = int gpio, iowrite32(dir, ctrl->dir[gpio / 16]); =20 if (out) - gc->set_rv(gc, gpio, val); + gpio_generic_chip_set(&ctrl->gen_gc, gpio, val); =20 iowrite32(output, ctrl->output); =20 @@ -70,7 +66,7 @@ static int airoha_dir_in(struct gpio_chip *gc, unsigned i= nt gpio) =20 static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio) { - struct airoha_gpio_ctrl *ctrl =3D gc_to_ctrl(gc); + struct airoha_gpio_ctrl *ctrl =3D gpiochip_get_data(gc); u32 dir =3D ioread32(ctrl->dir[gpio / 16]); u32 mask =3D BIT((gpio % 16) * 2); =20 @@ -79,6 +75,7 @@ static int airoha_get_dir(struct gpio_chip *gc, unsigned = int gpio) =20 static int airoha_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config =3D { }; struct device *dev =3D &pdev->dev; struct airoha_gpio_ctrl *ctrl; int err; @@ -103,18 +100,21 @@ static int airoha_gpio_probe(struct platform_device *= pdev) if (IS_ERR(ctrl->output)) return PTR_ERR(ctrl->output); =20 - err =3D bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL, - NULL, NULL, NULL, 0); + config.dev =3D dev; + config.sz =3D 4; + config.dat =3D ctrl->data; + + err =3D gpio_generic_chip_init(&ctrl->gen_gc, &config); if (err) return dev_err_probe(dev, err, "unable to init generic GPIO"); =20 - ctrl->gc.ngpio =3D AIROHA_GPIO_MAX; - ctrl->gc.owner =3D THIS_MODULE; - ctrl->gc.direction_output =3D airoha_dir_out; - ctrl->gc.direction_input =3D airoha_dir_in; - ctrl->gc.get_direction =3D airoha_get_dir; + ctrl->gen_gc.gc.ngpio =3D AIROHA_GPIO_MAX; + ctrl->gen_gc.gc.owner =3D THIS_MODULE; + ctrl->gen_gc.gc.direction_output =3D airoha_dir_out; + ctrl->gen_gc.gc.direction_input =3D airoha_dir_in; + ctrl->gen_gc.gc.get_direction =3D airoha_get_dir; =20 - return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); + return devm_gpiochip_add_data(dev, &ctrl->gen_gc.gc, ctrl); } =20 static const struct of_device_id airoha_gpio_of_match[] =3D { --=20 2.48.1